xref: /openbmc/linux/arch/m68k/Kconfig.cpu (revision 8497f696)
1comment "Processor Type"
2
3choice
4	prompt "CPU family support"
5	default M68KCLASSIC if MMU
6	default COLDFIRE if !MMU
7	help
8	  The Freescale (was Motorola) M68K family of processors implements
9	  the full 68000 processor instruction set.
10	  The Freescale ColdFire family of processors is a modern derivative
11	  of the 68000 processor family. They are mainly targeted at embedded
12	  applications, and are all System-On-Chip (SOC) devices, as opposed
13	  to stand alone CPUs. They implement a subset of the original 68000
14	  processor instruction set.
15	  If you anticipate running this kernel on a computer with a classic
16	  MC68xxx processor, select M68KCLASSIC.
17	  If you anticipate running this kernel on a computer with a ColdFire
18	  processor, select COLDFIRE.
19
20config M68KCLASSIC
21	bool "Classic M68K CPU family support"
22
23config COLDFIRE
24	bool "Coldfire CPU family support"
25	select GENERIC_GPIO
26	select ARCH_REQUIRE_GPIOLIB
27	select ARCH_HAVE_CUSTOM_GPIO_H
28	select CPU_HAS_NO_BITFIELDS
29	select CPU_HAS_NO_MULDIV64
30	select GENERIC_CSUM
31
32endchoice
33
34if M68KCLASSIC
35
36config M68000
37	bool
38	select CPU_HAS_NO_BITFIELDS
39	select CPU_HAS_NO_MULDIV64
40	select GENERIC_CSUM
41	help
42	  The Freescale (was Motorola) 68000 CPU is the first generation of
43	  the well known M68K family of processors. The CPU core as well as
44	  being available as a stand alone CPU was also used in many
45	  System-On-Chip devices (eg 68328, 68302, etc). It does not contain
46	  a paging MMU.
47
48config MCPU32
49	bool
50	select CPU_HAS_NO_BITFIELDS
51	help
52	  The Freescale (was then Motorola) CPU32 is a CPU core that is
53	  based on the 68020 processor. For the most part it is used in
54	  System-On-Chip parts, and does not contain a paging MMU.
55
56config M68020
57	bool "68020 support"
58	depends on MMU
59	select GENERIC_ATOMIC64
60	select CPU_HAS_ADDRESS_SPACES
61	help
62	  If you anticipate running this kernel on a computer with a MC68020
63	  processor, say Y. Otherwise, say N. Note that the 68020 requires a
64	  68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
65	  Sun 3, which provides its own version.
66
67config M68030
68	bool "68030 support"
69	depends on MMU && !MMU_SUN3
70	select GENERIC_ATOMIC64
71	select CPU_HAS_ADDRESS_SPACES
72	help
73	  If you anticipate running this kernel on a computer with a MC68030
74	  processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
75	  work, as it does not include an MMU (Memory Management Unit).
76
77config M68040
78	bool "68040 support"
79	depends on MMU && !MMU_SUN3
80	select GENERIC_ATOMIC64
81	select CPU_HAS_ADDRESS_SPACES
82	help
83	  If you anticipate running this kernel on a computer with a MC68LC040
84	  or MC68040 processor, say Y. Otherwise, say N. Note that an
85	  MC68EC040 will not work, as it does not include an MMU (Memory
86	  Management Unit).
87
88config M68060
89	bool "68060 support"
90	depends on MMU && !MMU_SUN3
91	select GENERIC_ATOMIC64
92	select CPU_HAS_ADDRESS_SPACES
93	help
94	  If you anticipate running this kernel on a computer with a MC68060
95	  processor, say Y. Otherwise, say N.
96
97config M68328
98	bool "MC68328"
99	depends on !MMU
100	select M68000
101	help
102	  Motorola 68328 processor support.
103
104config M68EZ328
105	bool "MC68EZ328"
106	depends on !MMU
107	select M68000
108	help
109	  Motorola 68EX328 processor support.
110
111config M68VZ328
112	bool "MC68VZ328"
113	depends on !MMU
114	select M68000
115	help
116	  Motorola 68VZ328 processor support.
117
118config M68360
119	bool "MC68360"
120	depends on !MMU
121	select MCPU32
122	help
123	  Motorola 68360 processor support.
124
125endif # M68KCLASSIC
126
127if COLDFIRE
128
129config M5206
130	bool "MCF5206"
131	depends on !MMU
132	select COLDFIRE_SW_A7
133	select HAVE_MBAR
134	help
135	  Motorola ColdFire 5206 processor support.
136
137config M5206e
138	bool "MCF5206e"
139	depends on !MMU
140	select COLDFIRE_SW_A7
141	select HAVE_MBAR
142	help
143	  Motorola ColdFire 5206e processor support.
144
145config M520x
146	bool "MCF520x"
147	depends on !MMU
148	select GENERIC_CLOCKEVENTS
149	select HAVE_CACHE_SPLIT
150	help
151	   Freescale Coldfire 5207/5208 processor support.
152
153config M523x
154	bool "MCF523x"
155	depends on !MMU
156	select GENERIC_CLOCKEVENTS
157	select HAVE_CACHE_SPLIT
158	select HAVE_IPSBAR
159	help
160	  Freescale Coldfire 5230/1/2/4/5 processor support
161
162config M5249
163	bool "MCF5249"
164	depends on !MMU
165	select COLDFIRE_SW_A7
166	select HAVE_MBAR
167	help
168	  Motorola ColdFire 5249 processor support.
169
170config M527x
171	bool
172
173config M5271
174	bool "MCF5271"
175	depends on !MMU
176	select M527x
177	select HAVE_CACHE_SPLIT
178	select HAVE_IPSBAR
179	select GENERIC_CLOCKEVENTS
180	help
181	  Freescale (Motorola) ColdFire 5270/5271 processor support.
182
183config M5272
184	bool "MCF5272"
185	depends on !MMU
186	select COLDFIRE_SW_A7
187	select HAVE_MBAR
188	help
189	  Motorola ColdFire 5272 processor support.
190
191config M5275
192	bool "MCF5275"
193	depends on !MMU
194	select M527x
195	select HAVE_CACHE_SPLIT
196	select HAVE_IPSBAR
197	select GENERIC_CLOCKEVENTS
198	help
199	  Freescale (Motorola) ColdFire 5274/5275 processor support.
200
201config M528x
202	bool "MCF528x"
203	depends on !MMU
204	select GENERIC_CLOCKEVENTS
205	select HAVE_CACHE_SPLIT
206	select HAVE_IPSBAR
207	help
208	  Motorola ColdFire 5280/5282 processor support.
209
210config M5307
211	bool "MCF5307"
212	depends on !MMU
213	select COLDFIRE_SW_A7
214	select HAVE_CACHE_CB
215	select HAVE_MBAR
216	help
217	  Motorola ColdFire 5307 processor support.
218
219config M532x
220	bool "MCF532x"
221	depends on !MMU
222	select HAVE_CACHE_CB
223	help
224	  Freescale (Motorola) ColdFire 532x processor support.
225
226config M5407
227	bool "MCF5407"
228	depends on !MMU
229	select COLDFIRE_SW_A7
230	select HAVE_CACHE_CB
231	select HAVE_MBAR
232	help
233	  Motorola ColdFire 5407 processor support.
234
235config M54xx
236	bool
237
238config M547x
239	bool "MCF547x"
240	select M54xx
241	select MMU_COLDFIRE if MMU
242	select HAVE_CACHE_CB
243	select HAVE_MBAR
244	help
245	  Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
246
247config M548x
248	bool "MCF548x"
249	select MMU_COLDFIRE if MMU
250	select M54xx
251	select HAVE_CACHE_CB
252	select HAVE_MBAR
253	help
254	  Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
255
256endif # COLDFIRE
257
258
259comment "Processor Specific Options"
260
261config M68KFPU_EMU
262	bool "Math emulation support (EXPERIMENTAL)"
263	depends on MMU
264	depends on EXPERIMENTAL
265	help
266	  At some point in the future, this will cause floating-point math
267	  instructions to be emulated by the kernel on machines that lack a
268	  floating-point math coprocessor.  Thrill-seekers and chronically
269	  sleep-deprived psychotic hacker types can say Y now, everyone else
270	  should probably wait a while.
271
272config M68KFPU_EMU_EXTRAPREC
273	bool "Math emulation extra precision"
274	depends on M68KFPU_EMU
275	help
276	  The fpu uses normally a few bit more during calculations for
277	  correct rounding, the emulator can (often) do the same but this
278	  extra calculation can cost quite some time, so you can disable
279	  it here. The emulator will then "only" calculate with a 64 bit
280	  mantissa and round slightly incorrect, what is more than enough
281	  for normal usage.
282
283config M68KFPU_EMU_ONLY
284	bool "Math emulation only kernel"
285	depends on M68KFPU_EMU
286	help
287	  This option prevents any floating-point instructions from being
288	  compiled into the kernel, thereby the kernel doesn't save any
289	  floating point context anymore during task switches, so this
290	  kernel will only be usable on machines without a floating-point
291	  math coprocessor. This makes the kernel a bit faster as no tests
292	  needs to be executed whether a floating-point instruction in the
293	  kernel should be executed or not.
294
295config ADVANCED
296	bool "Advanced configuration options"
297	depends on MMU
298	---help---
299	  This gives you access to some advanced options for the CPU. The
300	  defaults should be fine for most users, but these options may make
301	  it possible for you to improve performance somewhat if you know what
302	  you are doing.
303
304	  Note that the answer to this question won't directly affect the
305	  kernel: saying N will just cause the configurator to skip all
306	  the questions about these options.
307
308	  Most users should say N to this question.
309
310config RMW_INSNS
311	bool "Use read-modify-write instructions"
312	depends on ADVANCED
313	---help---
314	  This allows to use certain instructions that work with indivisible
315	  read-modify-write bus cycles. While this is faster than the
316	  workaround of disabling interrupts, it can conflict with DMA
317	  ( = direct memory access) on many Amiga systems, and it is also said
318	  to destabilize other machines. It is very likely that this will
319	  cause serious problems on any Amiga or Atari Medusa if set. The only
320	  configuration where it should work are 68030-based Ataris, where it
321	  apparently improves performance. But you've been warned! Unless you
322	  really know what you are doing, say N. Try Y only if you're quite
323	  adventurous.
324
325config SINGLE_MEMORY_CHUNK
326	bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
327	depends on MMU
328	default y if SUN3
329	select NEED_MULTIPLE_NODES
330	help
331	  Ignore all but the first contiguous chunk of physical memory for VM
332	  purposes.  This will save a few bytes kernel size and may speed up
333	  some operations.  Say N if not sure.
334
335config ARCH_DISCONTIGMEM_ENABLE
336	def_bool MMU && !SINGLE_MEMORY_CHUNK
337
338config 060_WRITETHROUGH
339	bool "Use write-through caching for 68060 supervisor accesses"
340	depends on ADVANCED && M68060
341	---help---
342	  The 68060 generally uses copyback caching of recently accessed data.
343	  Copyback caching means that memory writes will be held in an on-chip
344	  cache and only written back to memory some time later.  Saying Y
345	  here will force supervisor (kernel) accesses to use writethrough
346	  caching.  Writethrough caching means that data is written to memory
347	  straight away, so that cache and memory data always agree.
348	  Writethrough caching is less efficient, but is needed for some
349	  drivers on 68060 based systems where the 68060 bus snooping signal
350	  is hardwired on.  The 53c710 SCSI driver is known to suffer from
351	  this problem.
352
353config M68K_L2_CACHE
354	bool
355	depends on MAC
356	default y
357
358config NODES_SHIFT
359	int
360	default "3"
361	depends on !SINGLE_MEMORY_CHUNK
362
363config FPU
364	bool
365
366config COLDFIRE_SW_A7
367	bool
368
369config HAVE_CACHE_SPLIT
370	bool
371
372config HAVE_CACHE_CB
373	bool
374
375config HAVE_MBAR
376	bool
377
378config HAVE_IPSBAR
379	bool
380
381config CLOCK_SET
382	bool "Enable setting the CPU clock frequency"
383	depends on COLDFIRE
384	default n
385	help
386	  On some CPU's you do not need to know what the core CPU clock
387	  frequency is. On these you can disable clock setting. On some
388	  traditional 68K parts, and on all ColdFire parts you need to set
389	  the appropriate CPU clock frequency. On these devices many of the
390	  onboard peripherals derive their timing from the master CPU clock
391	  frequency.
392
393config CLOCK_FREQ
394	int "Set the core clock frequency"
395	default "66666666"
396	depends on CLOCK_SET
397	help
398	  Define the CPU clock frequency in use. This is the core clock
399	  frequency, it may or may not be the same as the external clock
400	  crystal fitted to your board. Some processors have an internal
401	  PLL and can have their frequency programmed at run time, others
402	  use internal dividers. In general the kernel won't setup a PLL
403	  if it is fitted (there are some exceptions). This value will be
404	  specific to the exact CPU that you are using.
405
406config OLDMASK
407	bool "Old mask 5307 (1H55J) silicon"
408	depends on M5307
409	help
410	  Build support for the older revision ColdFire 5307 silicon.
411	  Specifically this is the 1H55J mask revision.
412
413if HAVE_CACHE_SPLIT
414choice
415	prompt "Split Cache Configuration"
416	default CACHE_I
417
418config CACHE_I
419	bool "Instruction"
420	help
421	  Use all of the ColdFire CPU cache memory as an instruction cache.
422
423config CACHE_D
424	bool "Data"
425	help
426	  Use all of the ColdFire CPU cache memory as a data cache.
427
428config CACHE_BOTH
429	bool "Both"
430	help
431	  Split the ColdFire CPU cache, and use half as an instruction cache
432	  and half as a data cache.
433endchoice
434endif
435
436if HAVE_CACHE_CB
437choice
438	prompt "Data cache mode"
439	default CACHE_WRITETHRU
440
441config CACHE_WRITETHRU
442	bool "Write-through"
443	help
444	  The ColdFire CPU cache is set into Write-through mode.
445
446config CACHE_COPYBACK
447	bool "Copy-back"
448	help
449	  The ColdFire CPU cache is set into Copy-back mode.
450endchoice
451endif
452
453