1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/bug.h> 9 #include <linux/compiler.h> 10 #include <linux/context_tracking.h> 11 #include <linux/entry-common.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/kexec.h> 15 #include <linux/module.h> 16 #include <linux/extable.h> 17 #include <linux/mm.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/debug.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/memblock.h> 24 #include <linux/interrupt.h> 25 #include <linux/ptrace.h> 26 #include <linux/kgdb.h> 27 #include <linux/kdebug.h> 28 #include <linux/kprobes.h> 29 #include <linux/notifier.h> 30 #include <linux/irq.h> 31 #include <linux/perf_event.h> 32 33 #include <asm/addrspace.h> 34 #include <asm/bootinfo.h> 35 #include <asm/branch.h> 36 #include <asm/break.h> 37 #include <asm/cpu.h> 38 #include <asm/fpu.h> 39 #include <asm/inst.h> 40 #include <asm/loongarch.h> 41 #include <asm/mmu_context.h> 42 #include <asm/pgtable.h> 43 #include <asm/ptrace.h> 44 #include <asm/sections.h> 45 #include <asm/siginfo.h> 46 #include <asm/stacktrace.h> 47 #include <asm/tlb.h> 48 #include <asm/types.h> 49 #include <asm/unwind.h> 50 #include <asm/uprobes.h> 51 52 #include "access-helper.h" 53 54 extern asmlinkage void handle_ade(void); 55 extern asmlinkage void handle_ale(void); 56 extern asmlinkage void handle_bce(void); 57 extern asmlinkage void handle_sys(void); 58 extern asmlinkage void handle_bp(void); 59 extern asmlinkage void handle_ri(void); 60 extern asmlinkage void handle_fpu(void); 61 extern asmlinkage void handle_fpe(void); 62 extern asmlinkage void handle_lbt(void); 63 extern asmlinkage void handle_lsx(void); 64 extern asmlinkage void handle_lasx(void); 65 extern asmlinkage void handle_reserved(void); 66 extern asmlinkage void handle_watch(void); 67 extern asmlinkage void handle_vint(void); 68 69 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 70 const char *loglvl, bool user) 71 { 72 unsigned long addr; 73 struct unwind_state state; 74 struct pt_regs *pregs = (struct pt_regs *)regs; 75 76 if (!task) 77 task = current; 78 79 printk("%sCall Trace:", loglvl); 80 for (unwind_start(&state, task, pregs); 81 !unwind_done(&state); unwind_next_frame(&state)) { 82 addr = unwind_get_return_address(&state); 83 print_ip_sym(loglvl, addr); 84 } 85 printk("%s\n", loglvl); 86 } 87 88 static void show_stacktrace(struct task_struct *task, 89 const struct pt_regs *regs, const char *loglvl, bool user) 90 { 91 int i; 92 const int field = 2 * sizeof(unsigned long); 93 unsigned long stackdata; 94 unsigned long *sp = (unsigned long *)regs->regs[3]; 95 96 printk("%sStack :", loglvl); 97 i = 0; 98 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 99 if (i && ((i % (64 / field)) == 0)) { 100 pr_cont("\n"); 101 printk("%s ", loglvl); 102 } 103 if (i > 39) { 104 pr_cont(" ..."); 105 break; 106 } 107 108 if (__get_addr(&stackdata, sp++, user)) { 109 pr_cont(" (Bad stack address)"); 110 break; 111 } 112 113 pr_cont(" %0*lx", field, stackdata); 114 i++; 115 } 116 pr_cont("\n"); 117 show_backtrace(task, regs, loglvl, user); 118 } 119 120 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 121 { 122 struct pt_regs regs; 123 124 regs.csr_crmd = 0; 125 if (sp) { 126 regs.csr_era = 0; 127 regs.regs[1] = 0; 128 regs.regs[3] = (unsigned long)sp; 129 } else { 130 if (!task || task == current) 131 prepare_frametrace(®s); 132 else { 133 regs.csr_era = task->thread.reg01; 134 regs.regs[1] = 0; 135 regs.regs[3] = task->thread.reg03; 136 regs.regs[22] = task->thread.reg22; 137 } 138 } 139 140 show_stacktrace(task, ®s, loglvl, false); 141 } 142 143 static void show_code(unsigned int *pc, bool user) 144 { 145 long i; 146 unsigned int insn; 147 148 printk("Code:"); 149 150 for(i = -3 ; i < 6 ; i++) { 151 if (__get_inst(&insn, pc + i, user)) { 152 pr_cont(" (Bad address in era)\n"); 153 break; 154 } 155 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 156 } 157 pr_cont("\n"); 158 } 159 160 static void print_bool_fragment(const char *key, unsigned long val, bool first) 161 { 162 /* e.g. "+PG", "-DA" */ 163 pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key); 164 } 165 166 static void print_plv_fragment(const char *key, int val) 167 { 168 /* e.g. "PLV0", "PPLV3" */ 169 pr_cont("%s%d", key, val); 170 } 171 172 static void print_memory_type_fragment(const char *key, unsigned long val) 173 { 174 const char *humanized_type; 175 176 switch (val) { 177 case 0: 178 humanized_type = "SUC"; 179 break; 180 case 1: 181 humanized_type = "CC"; 182 break; 183 case 2: 184 humanized_type = "WUC"; 185 break; 186 default: 187 pr_cont(" %s=Reserved(%lu)", key, val); 188 return; 189 } 190 191 /* e.g. " DATM=WUC" */ 192 pr_cont(" %s=%s", key, humanized_type); 193 } 194 195 static void print_intr_fragment(const char *key, unsigned long val) 196 { 197 /* e.g. "LIE=0-1,3,5-7" */ 198 pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val); 199 } 200 201 static void print_crmd(unsigned long x) 202 { 203 printk(" CRMD: %08lx (", x); 204 print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x)); 205 print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false); 206 print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false); 207 print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false); 208 print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x)); 209 print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x)); 210 print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false); 211 pr_cont(")\n"); 212 } 213 214 static void print_prmd(unsigned long x) 215 { 216 printk(" PRMD: %08lx (", x); 217 print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x)); 218 print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false); 219 print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false); 220 pr_cont(")\n"); 221 } 222 223 static void print_euen(unsigned long x) 224 { 225 printk(" EUEN: %08lx (", x); 226 print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true); 227 print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false); 228 print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false); 229 print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false); 230 pr_cont(")\n"); 231 } 232 233 static void print_ecfg(unsigned long x) 234 { 235 printk(" ECFG: %08lx (", x); 236 print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x)); 237 pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x)); 238 } 239 240 static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode) 241 { 242 /* 243 * LoongArch users and developers are probably more familiar with 244 * those names found in the ISA manual, so we are going to print out 245 * the latter. This will require some mapping. 246 */ 247 switch (ecode) { 248 case EXCCODE_RSV: return "INT"; 249 case EXCCODE_TLBL: return "PIL"; 250 case EXCCODE_TLBS: return "PIS"; 251 case EXCCODE_TLBI: return "PIF"; 252 case EXCCODE_TLBM: return "PME"; 253 case EXCCODE_TLBNR: return "PNR"; 254 case EXCCODE_TLBNX: return "PNX"; 255 case EXCCODE_TLBPE: return "PPI"; 256 case EXCCODE_ADE: 257 switch (esubcode) { 258 case EXSUBCODE_ADEF: return "ADEF"; 259 case EXSUBCODE_ADEM: return "ADEM"; 260 } 261 break; 262 case EXCCODE_ALE: return "ALE"; 263 case EXCCODE_BCE: return "BCE"; 264 case EXCCODE_SYS: return "SYS"; 265 case EXCCODE_BP: return "BRK"; 266 case EXCCODE_INE: return "INE"; 267 case EXCCODE_IPE: return "IPE"; 268 case EXCCODE_FPDIS: return "FPD"; 269 case EXCCODE_LSXDIS: return "SXD"; 270 case EXCCODE_LASXDIS: return "ASXD"; 271 case EXCCODE_FPE: 272 switch (esubcode) { 273 case EXCSUBCODE_FPE: return "FPE"; 274 case EXCSUBCODE_VFPE: return "VFPE"; 275 } 276 break; 277 case EXCCODE_WATCH: 278 switch (esubcode) { 279 case EXCSUBCODE_WPEF: return "WPEF"; 280 case EXCSUBCODE_WPEM: return "WPEM"; 281 } 282 break; 283 case EXCCODE_BTDIS: return "BTD"; 284 case EXCCODE_BTE: return "BTE"; 285 case EXCCODE_GSPR: return "GSPR"; 286 case EXCCODE_HVC: return "HVC"; 287 case EXCCODE_GCM: 288 switch (esubcode) { 289 case EXCSUBCODE_GCSC: return "GCSC"; 290 case EXCSUBCODE_GCHC: return "GCHC"; 291 } 292 break; 293 /* 294 * The manual did not mention the EXCCODE_SE case, but print out it 295 * nevertheless. 296 */ 297 case EXCCODE_SE: return "SE"; 298 } 299 300 return "???"; 301 } 302 303 static void print_estat(unsigned long x) 304 { 305 unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x); 306 unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x); 307 308 printk("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode)); 309 print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x)); 310 pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode); 311 } 312 313 static void __show_regs(const struct pt_regs *regs) 314 { 315 const int field = 2 * sizeof(unsigned long); 316 unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat); 317 318 show_regs_print_info(KERN_DEFAULT); 319 320 /* Print saved GPRs except $zero (substituting with PC/ERA) */ 321 #define GPR_FIELD(x) field, regs->regs[x] 322 printk("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n", 323 field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3)); 324 printk("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n", 325 GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7)); 326 printk("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n", 327 GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11)); 328 printk("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n", 329 GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15)); 330 printk("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n", 331 GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19)); 332 printk("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n", 333 GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23)); 334 printk("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n", 335 GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27)); 336 printk("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n", 337 GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31)); 338 339 /* The slot for $zero is reused as the syscall restart flag */ 340 if (regs->regs[0]) 341 printk("syscall restart flag: %0*lx\n", GPR_FIELD(0)); 342 343 if (user_mode(regs)) { 344 printk(" ra: %0*lx\n", GPR_FIELD(1)); 345 printk(" ERA: %0*lx\n", field, regs->csr_era); 346 } else { 347 printk(" ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]); 348 printk(" ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era); 349 } 350 #undef GPR_FIELD 351 352 /* Print saved important CSRs */ 353 print_crmd(regs->csr_crmd); 354 print_prmd(regs->csr_prmd); 355 print_euen(regs->csr_euen); 356 print_ecfg(regs->csr_ecfg); 357 print_estat(regs->csr_estat); 358 359 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE) 360 printk(" BADV: %0*lx\n", field, regs->csr_badvaddr); 361 362 printk(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0), 363 cpu_family_string(), cpu_full_name_string()); 364 } 365 366 void show_regs(struct pt_regs *regs) 367 { 368 __show_regs((struct pt_regs *)regs); 369 dump_stack(); 370 } 371 372 void show_registers(struct pt_regs *regs) 373 { 374 __show_regs(regs); 375 print_modules(); 376 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 377 current->comm, current->pid, current_thread_info(), current); 378 379 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 380 show_code((void *)regs->csr_era, user_mode(regs)); 381 printk("\n"); 382 } 383 384 static DEFINE_RAW_SPINLOCK(die_lock); 385 386 void __noreturn die(const char *str, struct pt_regs *regs) 387 { 388 static int die_counter; 389 int sig = SIGSEGV; 390 391 oops_enter(); 392 393 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 394 SIGSEGV) == NOTIFY_STOP) 395 sig = 0; 396 397 console_verbose(); 398 raw_spin_lock_irq(&die_lock); 399 bust_spinlocks(1); 400 401 printk("%s[#%d]:\n", str, ++die_counter); 402 show_registers(regs); 403 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 404 raw_spin_unlock_irq(&die_lock); 405 406 oops_exit(); 407 408 if (regs && kexec_should_crash(current)) 409 crash_kexec(regs); 410 411 if (in_interrupt()) 412 panic("Fatal exception in interrupt"); 413 414 if (panic_on_oops) 415 panic("Fatal exception"); 416 417 make_task_dead(sig); 418 } 419 420 static inline void setup_vint_size(unsigned int size) 421 { 422 unsigned int vs; 423 424 vs = ilog2(size/4); 425 426 if (vs == 0 || vs > 7) 427 panic("vint_size %d Not support yet", vs); 428 429 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG); 430 } 431 432 /* 433 * Send SIGFPE according to FCSR Cause bits, which must have already 434 * been masked against Enable bits. This is impotant as Inexact can 435 * happen together with Overflow or Underflow, and `ptrace' can set 436 * any bits. 437 */ 438 void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr, 439 struct task_struct *tsk) 440 { 441 int si_code = FPE_FLTUNK; 442 443 if (fcsr & FPU_CSR_INV_X) 444 si_code = FPE_FLTINV; 445 else if (fcsr & FPU_CSR_DIV_X) 446 si_code = FPE_FLTDIV; 447 else if (fcsr & FPU_CSR_OVF_X) 448 si_code = FPE_FLTOVF; 449 else if (fcsr & FPU_CSR_UDF_X) 450 si_code = FPE_FLTUND; 451 else if (fcsr & FPU_CSR_INE_X) 452 si_code = FPE_FLTRES; 453 454 force_sig_fault(SIGFPE, si_code, fault_addr); 455 } 456 457 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr) 458 { 459 int si_code; 460 461 switch (sig) { 462 case 0: 463 return 0; 464 465 case SIGFPE: 466 force_fcsr_sig(fcsr, fault_addr, current); 467 return 1; 468 469 case SIGBUS: 470 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 471 return 1; 472 473 case SIGSEGV: 474 mmap_read_lock(current->mm); 475 if (vma_lookup(current->mm, (unsigned long)fault_addr)) 476 si_code = SEGV_ACCERR; 477 else 478 si_code = SEGV_MAPERR; 479 mmap_read_unlock(current->mm); 480 force_sig_fault(SIGSEGV, si_code, fault_addr); 481 return 1; 482 483 default: 484 force_sig(sig); 485 return 1; 486 } 487 } 488 489 /* 490 * Delayed fp exceptions when doing a lazy ctx switch 491 */ 492 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 493 { 494 int sig; 495 void __user *fault_addr; 496 irqentry_state_t state = irqentry_enter(regs); 497 498 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 499 SIGFPE) == NOTIFY_STOP) 500 goto out; 501 502 /* Clear FCSR.Cause before enabling interrupts */ 503 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr)); 504 local_irq_enable(); 505 506 die_if_kernel("FP exception in kernel code", regs); 507 508 sig = SIGFPE; 509 fault_addr = (void __user *) regs->csr_era; 510 511 /* Send a signal if required. */ 512 process_fpemu_return(sig, fault_addr, fcsr); 513 514 out: 515 local_irq_disable(); 516 irqentry_exit(regs, state); 517 } 518 519 asmlinkage void noinstr do_ade(struct pt_regs *regs) 520 { 521 irqentry_state_t state = irqentry_enter(regs); 522 523 die_if_kernel("Kernel ade access", regs); 524 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr); 525 526 irqentry_exit(regs, state); 527 } 528 529 /* sysctl hooks */ 530 int unaligned_enabled __read_mostly = 1; /* Enabled by default */ 531 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */ 532 533 asmlinkage void noinstr do_ale(struct pt_regs *regs) 534 { 535 irqentry_state_t state = irqentry_enter(regs); 536 537 #ifndef CONFIG_ARCH_STRICT_ALIGN 538 die_if_kernel("Kernel ale access", regs); 539 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 540 #else 541 unsigned int *pc; 542 543 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr); 544 545 /* 546 * Did we catch a fault trying to load an instruction? 547 */ 548 if (regs->csr_badvaddr == regs->csr_era) 549 goto sigbus; 550 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) 551 goto sigbus; 552 if (!unaligned_enabled) 553 goto sigbus; 554 if (!no_unaligned_warning) 555 show_registers(regs); 556 557 pc = (unsigned int *)exception_era(regs); 558 559 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc); 560 561 goto out; 562 563 sigbus: 564 die_if_kernel("Kernel ale access", regs); 565 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 566 out: 567 #endif 568 irqentry_exit(regs, state); 569 } 570 571 #ifdef CONFIG_GENERIC_BUG 572 int is_valid_bugaddr(unsigned long addr) 573 { 574 return 1; 575 } 576 #endif /* CONFIG_GENERIC_BUG */ 577 578 static void bug_handler(struct pt_regs *regs) 579 { 580 switch (report_bug(regs->csr_era, regs)) { 581 case BUG_TRAP_TYPE_BUG: 582 case BUG_TRAP_TYPE_NONE: 583 die_if_kernel("Oops - BUG", regs); 584 force_sig(SIGTRAP); 585 break; 586 587 case BUG_TRAP_TYPE_WARN: 588 /* Skip the BUG instruction and continue */ 589 regs->csr_era += LOONGARCH_INSN_SIZE; 590 break; 591 } 592 } 593 594 asmlinkage void noinstr do_bce(struct pt_regs *regs) 595 { 596 bool user = user_mode(regs); 597 unsigned long era = exception_era(regs); 598 u64 badv = 0, lower = 0, upper = ULONG_MAX; 599 union loongarch_instruction insn; 600 irqentry_state_t state = irqentry_enter(regs); 601 602 if (regs->csr_prmd & CSR_PRMD_PIE) 603 local_irq_enable(); 604 605 current->thread.trap_nr = read_csr_excode(); 606 607 die_if_kernel("Bounds check error in kernel code", regs); 608 609 /* 610 * Pull out the address that failed bounds checking, and the lower / 611 * upper bound, by minimally looking at the faulting instruction word 612 * and reading from the correct register. 613 */ 614 if (__get_inst(&insn.word, (u32 *)era, user)) 615 goto bad_era; 616 617 switch (insn.reg3_format.opcode) { 618 case asrtle_op: 619 if (insn.reg3_format.rd != 0) 620 break; /* not asrtle */ 621 badv = regs->regs[insn.reg3_format.rj]; 622 upper = regs->regs[insn.reg3_format.rk]; 623 break; 624 625 case asrtgt_op: 626 if (insn.reg3_format.rd != 0) 627 break; /* not asrtgt */ 628 badv = regs->regs[insn.reg3_format.rj]; 629 lower = regs->regs[insn.reg3_format.rk]; 630 break; 631 632 case ldleb_op: 633 case ldleh_op: 634 case ldlew_op: 635 case ldled_op: 636 case stleb_op: 637 case stleh_op: 638 case stlew_op: 639 case stled_op: 640 case fldles_op: 641 case fldled_op: 642 case fstles_op: 643 case fstled_op: 644 badv = regs->regs[insn.reg3_format.rj]; 645 upper = regs->regs[insn.reg3_format.rk]; 646 break; 647 648 case ldgtb_op: 649 case ldgth_op: 650 case ldgtw_op: 651 case ldgtd_op: 652 case stgtb_op: 653 case stgth_op: 654 case stgtw_op: 655 case stgtd_op: 656 case fldgts_op: 657 case fldgtd_op: 658 case fstgts_op: 659 case fstgtd_op: 660 badv = regs->regs[insn.reg3_format.rj]; 661 lower = regs->regs[insn.reg3_format.rk]; 662 break; 663 } 664 665 force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper); 666 667 out: 668 if (regs->csr_prmd & CSR_PRMD_PIE) 669 local_irq_disable(); 670 671 irqentry_exit(regs, state); 672 return; 673 674 bad_era: 675 /* 676 * Cannot pull out the instruction word, hence cannot provide more 677 * info than a regular SIGSEGV in this case. 678 */ 679 force_sig(SIGSEGV); 680 goto out; 681 } 682 683 asmlinkage void noinstr do_bp(struct pt_regs *regs) 684 { 685 bool user = user_mode(regs); 686 unsigned int opcode, bcode; 687 unsigned long era = exception_era(regs); 688 irqentry_state_t state = irqentry_enter(regs); 689 690 if (regs->csr_prmd & CSR_PRMD_PIE) 691 local_irq_enable(); 692 693 if (__get_inst(&opcode, (u32 *)era, user)) 694 goto out_sigsegv; 695 696 bcode = (opcode & 0x7fff); 697 698 /* 699 * notify the kprobe handlers, if instruction is likely to 700 * pertain to them. 701 */ 702 switch (bcode) { 703 case BRK_KPROBE_BP: 704 if (kprobe_breakpoint_handler(regs)) 705 goto out; 706 else 707 break; 708 case BRK_KPROBE_SSTEPBP: 709 if (kprobe_singlestep_handler(regs)) 710 goto out; 711 else 712 break; 713 case BRK_UPROBE_BP: 714 if (uprobe_breakpoint_handler(regs)) 715 goto out; 716 else 717 break; 718 case BRK_UPROBE_XOLBP: 719 if (uprobe_singlestep_handler(regs)) 720 goto out; 721 else 722 break; 723 default: 724 current->thread.trap_nr = read_csr_excode(); 725 if (notify_die(DIE_TRAP, "Break", regs, bcode, 726 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 727 goto out; 728 else 729 break; 730 } 731 732 switch (bcode) { 733 case BRK_BUG: 734 bug_handler(regs); 735 break; 736 case BRK_DIVZERO: 737 die_if_kernel("Break instruction in kernel code", regs); 738 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era); 739 break; 740 case BRK_OVERFLOW: 741 die_if_kernel("Break instruction in kernel code", regs); 742 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era); 743 break; 744 default: 745 die_if_kernel("Break instruction in kernel code", regs); 746 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era); 747 break; 748 } 749 750 out: 751 if (regs->csr_prmd & CSR_PRMD_PIE) 752 local_irq_disable(); 753 754 irqentry_exit(regs, state); 755 return; 756 757 out_sigsegv: 758 force_sig(SIGSEGV); 759 goto out; 760 } 761 762 asmlinkage void noinstr do_watch(struct pt_regs *regs) 763 { 764 irqentry_state_t state = irqentry_enter(regs); 765 766 #ifndef CONFIG_HAVE_HW_BREAKPOINT 767 pr_warn("Hardware watch point handler not implemented!\n"); 768 #else 769 if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) { 770 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1); 771 unsigned long pc = instruction_pointer(regs); 772 union loongarch_instruction *ip = (union loongarch_instruction *)pc; 773 774 if (llbit) { 775 /* 776 * When the ll-sc combo is encountered, it is regarded as an single 777 * instruction. So don't clear llbit and reset CSR.FWPS.Skip until 778 * the llsc execution is completed. 779 */ 780 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 781 csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL); 782 goto out; 783 } 784 785 if (pc == current->thread.single_step) { 786 /* 787 * Certain insns are occasionally not skipped when CSR.FWPS.Skip is 788 * set, such as fld.d/fst.d. So singlestep needs to compare whether 789 * the csr_era is equal to the value of singlestep which last time set. 790 */ 791 if (!is_self_loop_ins(ip, regs)) { 792 /* 793 * Check if the given instruction the target pc is equal to the 794 * current pc, If yes, then we should not set the CSR.FWPS.SKIP 795 * bit to break the original instruction stream. 796 */ 797 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 798 goto out; 799 } 800 } 801 } else { 802 breakpoint_handler(regs); 803 watchpoint_handler(regs); 804 } 805 806 force_sig(SIGTRAP); 807 out: 808 #endif 809 irqentry_exit(regs, state); 810 } 811 812 asmlinkage void noinstr do_ri(struct pt_regs *regs) 813 { 814 int status = SIGILL; 815 unsigned int opcode = 0; 816 unsigned int __user *era = (unsigned int __user *)exception_era(regs); 817 irqentry_state_t state = irqentry_enter(regs); 818 819 local_irq_enable(); 820 current->thread.trap_nr = read_csr_excode(); 821 822 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 823 SIGILL) == NOTIFY_STOP) 824 goto out; 825 826 die_if_kernel("Reserved instruction in kernel code", regs); 827 828 if (unlikely(get_user(opcode, era) < 0)) { 829 status = SIGSEGV; 830 current->thread.error_code = 1; 831 } 832 833 force_sig(status); 834 835 out: 836 local_irq_disable(); 837 irqentry_exit(regs, state); 838 } 839 840 static void init_restore_fp(void) 841 { 842 if (!used_math()) { 843 /* First time FP context user. */ 844 init_fpu(); 845 } else { 846 /* This task has formerly used the FP context */ 847 if (!is_fpu_owner()) 848 own_fpu_inatomic(1); 849 } 850 851 BUG_ON(!is_fp_enabled()); 852 } 853 854 static void init_restore_lsx(void) 855 { 856 enable_lsx(); 857 858 if (!thread_lsx_context_live()) { 859 /* First time LSX context user */ 860 init_restore_fp(); 861 init_lsx_upper(); 862 set_thread_flag(TIF_LSX_CTX_LIVE); 863 } else { 864 if (!is_simd_owner()) { 865 if (is_fpu_owner()) { 866 restore_lsx_upper(current); 867 } else { 868 __own_fpu(); 869 restore_lsx(current); 870 } 871 } 872 } 873 874 set_thread_flag(TIF_USEDSIMD); 875 876 BUG_ON(!is_fp_enabled()); 877 BUG_ON(!is_lsx_enabled()); 878 } 879 880 static void init_restore_lasx(void) 881 { 882 enable_lasx(); 883 884 if (!thread_lasx_context_live()) { 885 /* First time LASX context user */ 886 init_restore_lsx(); 887 init_lasx_upper(); 888 set_thread_flag(TIF_LASX_CTX_LIVE); 889 } else { 890 if (is_fpu_owner() || is_simd_owner()) { 891 init_restore_lsx(); 892 restore_lasx_upper(current); 893 } else { 894 __own_fpu(); 895 enable_lsx(); 896 restore_lasx(current); 897 } 898 } 899 900 set_thread_flag(TIF_USEDSIMD); 901 902 BUG_ON(!is_fp_enabled()); 903 BUG_ON(!is_lsx_enabled()); 904 BUG_ON(!is_lasx_enabled()); 905 } 906 907 asmlinkage void noinstr do_fpu(struct pt_regs *regs) 908 { 909 irqentry_state_t state = irqentry_enter(regs); 910 911 local_irq_enable(); 912 die_if_kernel("do_fpu invoked from kernel context!", regs); 913 BUG_ON(is_lsx_enabled()); 914 BUG_ON(is_lasx_enabled()); 915 916 preempt_disable(); 917 init_restore_fp(); 918 preempt_enable(); 919 920 local_irq_disable(); 921 irqentry_exit(regs, state); 922 } 923 924 asmlinkage void noinstr do_lsx(struct pt_regs *regs) 925 { 926 irqentry_state_t state = irqentry_enter(regs); 927 928 local_irq_enable(); 929 if (!cpu_has_lsx) { 930 force_sig(SIGILL); 931 goto out; 932 } 933 934 die_if_kernel("do_lsx invoked from kernel context!", regs); 935 BUG_ON(is_lasx_enabled()); 936 937 preempt_disable(); 938 init_restore_lsx(); 939 preempt_enable(); 940 941 out: 942 local_irq_disable(); 943 irqentry_exit(regs, state); 944 } 945 946 asmlinkage void noinstr do_lasx(struct pt_regs *regs) 947 { 948 irqentry_state_t state = irqentry_enter(regs); 949 950 local_irq_enable(); 951 if (!cpu_has_lasx) { 952 force_sig(SIGILL); 953 goto out; 954 } 955 956 die_if_kernel("do_lasx invoked from kernel context!", regs); 957 958 preempt_disable(); 959 init_restore_lasx(); 960 preempt_enable(); 961 962 out: 963 local_irq_disable(); 964 irqentry_exit(regs, state); 965 } 966 967 asmlinkage void noinstr do_lbt(struct pt_regs *regs) 968 { 969 irqentry_state_t state = irqentry_enter(regs); 970 971 local_irq_enable(); 972 force_sig(SIGILL); 973 local_irq_disable(); 974 975 irqentry_exit(regs, state); 976 } 977 978 asmlinkage void noinstr do_reserved(struct pt_regs *regs) 979 { 980 irqentry_state_t state = irqentry_enter(regs); 981 982 local_irq_enable(); 983 /* 984 * Game over - no way to handle this if it ever occurs. Most probably 985 * caused by a fatal error after another hardware/software error. 986 */ 987 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n", 988 read_csr_excode(), current->pid, current->comm); 989 die_if_kernel("do_reserved exception", regs); 990 force_sig(SIGUNUSED); 991 992 local_irq_disable(); 993 994 irqentry_exit(regs, state); 995 } 996 997 asmlinkage void cache_parity_error(void) 998 { 999 /* For the moment, report the problem and hang. */ 1000 pr_err("Cache error exception:\n"); 1001 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); 1002 pr_err("csr_merrera == %016lx\n", csr_read64(LOONGARCH_CSR_MERRERA)); 1003 panic("Can't handle the cache error!"); 1004 } 1005 1006 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs) 1007 { 1008 struct pt_regs *old_regs; 1009 1010 irq_enter_rcu(); 1011 old_regs = set_irq_regs(regs); 1012 handle_arch_irq(regs); 1013 set_irq_regs(old_regs); 1014 irq_exit_rcu(); 1015 } 1016 1017 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) 1018 { 1019 register int cpu; 1020 register unsigned long stack; 1021 irqentry_state_t state = irqentry_enter(regs); 1022 1023 cpu = smp_processor_id(); 1024 1025 if (on_irq_stack(cpu, sp)) 1026 handle_loongarch_irq(regs); 1027 else { 1028 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START; 1029 1030 /* Save task's sp on IRQ stack for unwinding */ 1031 *(unsigned long *)stack = sp; 1032 1033 __asm__ __volatile__( 1034 "move $s0, $sp \n" /* Preserve sp */ 1035 "move $sp, %[stk] \n" /* Switch stack */ 1036 "move $a0, %[regs] \n" 1037 "bl handle_loongarch_irq \n" 1038 "move $sp, $s0 \n" /* Restore sp */ 1039 : /* No outputs */ 1040 : [stk] "r" (stack), [regs] "r" (regs) 1041 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0", 1042 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", 1043 "memory"); 1044 } 1045 1046 irqentry_exit(regs, state); 1047 } 1048 1049 unsigned long eentry; 1050 unsigned long tlbrentry; 1051 1052 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); 1053 1054 static void configure_exception_vector(void) 1055 { 1056 eentry = (unsigned long)exception_handlers; 1057 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 1058 1059 csr_write64(eentry, LOONGARCH_CSR_EENTRY); 1060 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 1061 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 1062 } 1063 1064 void per_cpu_trap_init(int cpu) 1065 { 1066 unsigned int i; 1067 1068 setup_vint_size(VECSIZE); 1069 1070 configure_exception_vector(); 1071 1072 if (!cpu_data[cpu].asid_cache) 1073 cpu_data[cpu].asid_cache = asid_first_version(cpu); 1074 1075 mmgrab(&init_mm); 1076 current->active_mm = &init_mm; 1077 BUG_ON(current->mm); 1078 enter_lazy_tlb(&init_mm, current); 1079 1080 /* Initialise exception handlers */ 1081 if (cpu == 0) 1082 for (i = 0; i < 64; i++) 1083 set_handler(i * VECSIZE, handle_reserved, VECSIZE); 1084 1085 tlb_init(cpu); 1086 cpu_cache_init(); 1087 } 1088 1089 /* Install CPU exception handler */ 1090 void set_handler(unsigned long offset, void *addr, unsigned long size) 1091 { 1092 memcpy((void *)(eentry + offset), addr, size); 1093 local_flush_icache_range(eentry + offset, eentry + offset + size); 1094 } 1095 1096 static const char panic_null_cerr[] = 1097 "Trying to set NULL cache error exception handler\n"; 1098 1099 /* 1100 * Install uncached CPU exception handler. 1101 * This is suitable only for the cache error exception which is the only 1102 * exception handler that is being run uncached. 1103 */ 1104 void set_merr_handler(unsigned long offset, void *addr, unsigned long size) 1105 { 1106 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry)); 1107 1108 if (!addr) 1109 panic(panic_null_cerr); 1110 1111 memcpy((void *)(uncached_eentry + offset), addr, size); 1112 } 1113 1114 void __init trap_init(void) 1115 { 1116 long i; 1117 1118 /* Set interrupt vector handler */ 1119 for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++) 1120 set_handler(i * VECSIZE, handle_vint, VECSIZE); 1121 1122 set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); 1123 set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); 1124 set_handler(EXCCODE_BCE * VECSIZE, handle_bce, VECSIZE); 1125 set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); 1126 set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); 1127 set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); 1128 set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE); 1129 set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE); 1130 set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE); 1131 set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE); 1132 set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE); 1133 set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE); 1134 set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE); 1135 1136 cache_error_setup(); 1137 1138 local_flush_icache_range(eentry, eentry + 0x400); 1139 } 1140