1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 #include <linux/bitops.h> 7 #include <linux/bug.h> 8 #include <linux/compiler.h> 9 #include <linux/context_tracking.h> 10 #include <linux/entry-common.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/kexec.h> 14 #include <linux/module.h> 15 #include <linux/extable.h> 16 #include <linux/mm.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/debug.h> 19 #include <linux/smp.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/memblock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ptrace.h> 25 #include <linux/kgdb.h> 26 #include <linux/kdebug.h> 27 #include <linux/kprobes.h> 28 #include <linux/notifier.h> 29 #include <linux/irq.h> 30 #include <linux/perf_event.h> 31 32 #include <asm/addrspace.h> 33 #include <asm/bootinfo.h> 34 #include <asm/branch.h> 35 #include <asm/break.h> 36 #include <asm/cpu.h> 37 #include <asm/fpu.h> 38 #include <asm/loongarch.h> 39 #include <asm/mmu_context.h> 40 #include <asm/pgtable.h> 41 #include <asm/ptrace.h> 42 #include <asm/sections.h> 43 #include <asm/siginfo.h> 44 #include <asm/stacktrace.h> 45 #include <asm/tlb.h> 46 #include <asm/types.h> 47 #include <asm/unwind.h> 48 49 #include "access-helper.h" 50 51 extern asmlinkage void handle_ade(void); 52 extern asmlinkage void handle_ale(void); 53 extern asmlinkage void handle_sys(void); 54 extern asmlinkage void handle_bp(void); 55 extern asmlinkage void handle_ri(void); 56 extern asmlinkage void handle_fpu(void); 57 extern asmlinkage void handle_fpe(void); 58 extern asmlinkage void handle_lbt(void); 59 extern asmlinkage void handle_lsx(void); 60 extern asmlinkage void handle_lasx(void); 61 extern asmlinkage void handle_reserved(void); 62 extern asmlinkage void handle_watch(void); 63 extern asmlinkage void handle_vint(void); 64 65 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 66 const char *loglvl, bool user) 67 { 68 unsigned long addr; 69 struct unwind_state state; 70 struct pt_regs *pregs = (struct pt_regs *)regs; 71 72 if (!task) 73 task = current; 74 75 printk("%sCall Trace:", loglvl); 76 for (unwind_start(&state, task, pregs); 77 !unwind_done(&state); unwind_next_frame(&state)) { 78 addr = unwind_get_return_address(&state); 79 print_ip_sym(loglvl, addr); 80 } 81 printk("%s\n", loglvl); 82 } 83 84 static void show_stacktrace(struct task_struct *task, 85 const struct pt_regs *regs, const char *loglvl, bool user) 86 { 87 int i; 88 const int field = 2 * sizeof(unsigned long); 89 unsigned long stackdata; 90 unsigned long *sp = (unsigned long *)regs->regs[3]; 91 92 printk("%sStack :", loglvl); 93 i = 0; 94 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 95 if (i && ((i % (64 / field)) == 0)) { 96 pr_cont("\n"); 97 printk("%s ", loglvl); 98 } 99 if (i > 39) { 100 pr_cont(" ..."); 101 break; 102 } 103 104 if (__get_addr(&stackdata, sp++, user)) { 105 pr_cont(" (Bad stack address)"); 106 break; 107 } 108 109 pr_cont(" %0*lx", field, stackdata); 110 i++; 111 } 112 pr_cont("\n"); 113 show_backtrace(task, regs, loglvl, user); 114 } 115 116 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 117 { 118 struct pt_regs regs; 119 120 regs.csr_crmd = 0; 121 if (sp) { 122 regs.csr_era = 0; 123 regs.regs[1] = 0; 124 regs.regs[3] = (unsigned long)sp; 125 } else { 126 if (!task || task == current) 127 prepare_frametrace(®s); 128 else { 129 regs.csr_era = task->thread.reg01; 130 regs.regs[1] = 0; 131 regs.regs[3] = task->thread.reg03; 132 regs.regs[22] = task->thread.reg22; 133 } 134 } 135 136 show_stacktrace(task, ®s, loglvl, false); 137 } 138 139 static void show_code(unsigned int *pc, bool user) 140 { 141 long i; 142 unsigned int insn; 143 144 printk("Code:"); 145 146 for(i = -3 ; i < 6 ; i++) { 147 if (__get_inst(&insn, pc + i, user)) { 148 pr_cont(" (Bad address in era)\n"); 149 break; 150 } 151 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 152 } 153 pr_cont("\n"); 154 } 155 156 static void __show_regs(const struct pt_regs *regs) 157 { 158 const int field = 2 * sizeof(unsigned long); 159 unsigned int excsubcode; 160 unsigned int exccode; 161 int i; 162 163 show_regs_print_info(KERN_DEFAULT); 164 165 /* 166 * Saved main processor registers 167 */ 168 for (i = 0; i < 32; ) { 169 if ((i % 4) == 0) 170 printk("$%2d :", i); 171 pr_cont(" %0*lx", field, regs->regs[i]); 172 173 i++; 174 if ((i % 4) == 0) 175 pr_cont("\n"); 176 } 177 178 /* 179 * Saved csr registers 180 */ 181 printk("era : %0*lx %pS\n", field, regs->csr_era, 182 (void *) regs->csr_era); 183 printk("ra : %0*lx %pS\n", field, regs->regs[1], 184 (void *) regs->regs[1]); 185 186 printk("CSR crmd: %08lx ", regs->csr_crmd); 187 printk("CSR prmd: %08lx ", regs->csr_prmd); 188 printk("CSR euen: %08lx ", regs->csr_euen); 189 printk("CSR ecfg: %08lx ", regs->csr_ecfg); 190 printk("CSR estat: %08lx ", regs->csr_estat); 191 192 pr_cont("\n"); 193 194 exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 195 excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT; 196 printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode); 197 198 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE) 199 printk("BadVA : %0*lx\n", field, regs->csr_badvaddr); 200 201 printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0), 202 cpu_family_string()); 203 } 204 205 void show_regs(struct pt_regs *regs) 206 { 207 __show_regs((struct pt_regs *)regs); 208 dump_stack(); 209 } 210 211 void show_registers(struct pt_regs *regs) 212 { 213 __show_regs(regs); 214 print_modules(); 215 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 216 current->comm, current->pid, current_thread_info(), current); 217 218 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 219 show_code((void *)regs->csr_era, user_mode(regs)); 220 printk("\n"); 221 } 222 223 static DEFINE_RAW_SPINLOCK(die_lock); 224 225 void __noreturn die(const char *str, struct pt_regs *regs) 226 { 227 static int die_counter; 228 int sig = SIGSEGV; 229 230 oops_enter(); 231 232 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 233 SIGSEGV) == NOTIFY_STOP) 234 sig = 0; 235 236 console_verbose(); 237 raw_spin_lock_irq(&die_lock); 238 bust_spinlocks(1); 239 240 printk("%s[#%d]:\n", str, ++die_counter); 241 show_registers(regs); 242 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 243 raw_spin_unlock_irq(&die_lock); 244 245 oops_exit(); 246 247 if (regs && kexec_should_crash(current)) 248 crash_kexec(regs); 249 250 if (in_interrupt()) 251 panic("Fatal exception in interrupt"); 252 253 if (panic_on_oops) 254 panic("Fatal exception"); 255 256 make_task_dead(sig); 257 } 258 259 static inline void setup_vint_size(unsigned int size) 260 { 261 unsigned int vs; 262 263 vs = ilog2(size/4); 264 265 if (vs == 0 || vs > 7) 266 panic("vint_size %d Not support yet", vs); 267 268 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG); 269 } 270 271 /* 272 * Send SIGFPE according to FCSR Cause bits, which must have already 273 * been masked against Enable bits. This is impotant as Inexact can 274 * happen together with Overflow or Underflow, and `ptrace' can set 275 * any bits. 276 */ 277 void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr, 278 struct task_struct *tsk) 279 { 280 int si_code = FPE_FLTUNK; 281 282 if (fcsr & FPU_CSR_INV_X) 283 si_code = FPE_FLTINV; 284 else if (fcsr & FPU_CSR_DIV_X) 285 si_code = FPE_FLTDIV; 286 else if (fcsr & FPU_CSR_OVF_X) 287 si_code = FPE_FLTOVF; 288 else if (fcsr & FPU_CSR_UDF_X) 289 si_code = FPE_FLTUND; 290 else if (fcsr & FPU_CSR_INE_X) 291 si_code = FPE_FLTRES; 292 293 force_sig_fault(SIGFPE, si_code, fault_addr); 294 } 295 296 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr) 297 { 298 int si_code; 299 300 switch (sig) { 301 case 0: 302 return 0; 303 304 case SIGFPE: 305 force_fcsr_sig(fcsr, fault_addr, current); 306 return 1; 307 308 case SIGBUS: 309 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 310 return 1; 311 312 case SIGSEGV: 313 mmap_read_lock(current->mm); 314 if (vma_lookup(current->mm, (unsigned long)fault_addr)) 315 si_code = SEGV_ACCERR; 316 else 317 si_code = SEGV_MAPERR; 318 mmap_read_unlock(current->mm); 319 force_sig_fault(SIGSEGV, si_code, fault_addr); 320 return 1; 321 322 default: 323 force_sig(sig); 324 return 1; 325 } 326 } 327 328 /* 329 * Delayed fp exceptions when doing a lazy ctx switch 330 */ 331 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 332 { 333 int sig; 334 void __user *fault_addr; 335 irqentry_state_t state = irqentry_enter(regs); 336 337 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 338 SIGFPE) == NOTIFY_STOP) 339 goto out; 340 341 /* Clear FCSR.Cause before enabling interrupts */ 342 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr)); 343 local_irq_enable(); 344 345 die_if_kernel("FP exception in kernel code", regs); 346 347 sig = SIGFPE; 348 fault_addr = (void __user *) regs->csr_era; 349 350 /* Send a signal if required. */ 351 process_fpemu_return(sig, fault_addr, fcsr); 352 353 out: 354 local_irq_disable(); 355 irqentry_exit(regs, state); 356 } 357 358 asmlinkage void noinstr do_ade(struct pt_regs *regs) 359 { 360 irqentry_state_t state = irqentry_enter(regs); 361 362 die_if_kernel("Kernel ade access", regs); 363 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr); 364 365 irqentry_exit(regs, state); 366 } 367 368 /* sysctl hooks */ 369 int unaligned_enabled __read_mostly = 1; /* Enabled by default */ 370 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */ 371 372 asmlinkage void noinstr do_ale(struct pt_regs *regs) 373 { 374 irqentry_state_t state = irqentry_enter(regs); 375 376 #ifndef CONFIG_ARCH_STRICT_ALIGN 377 die_if_kernel("Kernel ale access", regs); 378 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 379 #else 380 unsigned int *pc; 381 382 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr); 383 384 /* 385 * Did we catch a fault trying to load an instruction? 386 */ 387 if (regs->csr_badvaddr == regs->csr_era) 388 goto sigbus; 389 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) 390 goto sigbus; 391 if (!unaligned_enabled) 392 goto sigbus; 393 if (!no_unaligned_warning) 394 show_registers(regs); 395 396 pc = (unsigned int *)exception_era(regs); 397 398 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc); 399 400 goto out; 401 402 sigbus: 403 die_if_kernel("Kernel ale access", regs); 404 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 405 out: 406 #endif 407 irqentry_exit(regs, state); 408 } 409 410 #ifdef CONFIG_GENERIC_BUG 411 int is_valid_bugaddr(unsigned long addr) 412 { 413 return 1; 414 } 415 #endif /* CONFIG_GENERIC_BUG */ 416 417 static void bug_handler(struct pt_regs *regs) 418 { 419 switch (report_bug(regs->csr_era, regs)) { 420 case BUG_TRAP_TYPE_BUG: 421 case BUG_TRAP_TYPE_NONE: 422 die_if_kernel("Oops - BUG", regs); 423 force_sig(SIGTRAP); 424 break; 425 426 case BUG_TRAP_TYPE_WARN: 427 /* Skip the BUG instruction and continue */ 428 regs->csr_era += LOONGARCH_INSN_SIZE; 429 break; 430 } 431 } 432 433 asmlinkage void noinstr do_bp(struct pt_regs *regs) 434 { 435 bool user = user_mode(regs); 436 unsigned int opcode, bcode; 437 unsigned long era = exception_era(regs); 438 irqentry_state_t state = irqentry_enter(regs); 439 440 if (regs->csr_prmd & CSR_PRMD_PIE) 441 local_irq_enable(); 442 443 current->thread.trap_nr = read_csr_excode(); 444 if (__get_inst(&opcode, (u32 *)era, user)) 445 goto out_sigsegv; 446 447 bcode = (opcode & 0x7fff); 448 449 /* 450 * notify the kprobe handlers, if instruction is likely to 451 * pertain to them. 452 */ 453 switch (bcode) { 454 case BRK_KPROBE_BP: 455 if (kprobe_breakpoint_handler(regs)) 456 goto out; 457 else 458 break; 459 case BRK_KPROBE_SSTEPBP: 460 if (kprobe_singlestep_handler(regs)) 461 goto out; 462 else 463 break; 464 case BRK_UPROBE_BP: 465 if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode, 466 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 467 goto out; 468 else 469 break; 470 case BRK_UPROBE_XOLBP: 471 if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode, 472 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 473 goto out; 474 else 475 break; 476 default: 477 if (notify_die(DIE_TRAP, "Break", regs, bcode, 478 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 479 goto out; 480 else 481 break; 482 } 483 484 switch (bcode) { 485 case BRK_BUG: 486 bug_handler(regs); 487 break; 488 case BRK_DIVZERO: 489 die_if_kernel("Break instruction in kernel code", regs); 490 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era); 491 break; 492 case BRK_OVERFLOW: 493 die_if_kernel("Break instruction in kernel code", regs); 494 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era); 495 break; 496 default: 497 die_if_kernel("Break instruction in kernel code", regs); 498 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era); 499 break; 500 } 501 502 out: 503 if (regs->csr_prmd & CSR_PRMD_PIE) 504 local_irq_disable(); 505 506 irqentry_exit(regs, state); 507 return; 508 509 out_sigsegv: 510 force_sig(SIGSEGV); 511 goto out; 512 } 513 514 asmlinkage void noinstr do_watch(struct pt_regs *regs) 515 { 516 irqentry_state_t state = irqentry_enter(regs); 517 518 #ifndef CONFIG_HAVE_HW_BREAKPOINT 519 pr_warn("Hardware watch point handler not implemented!\n"); 520 #else 521 if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) { 522 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1); 523 unsigned long pc = instruction_pointer(regs); 524 union loongarch_instruction *ip = (union loongarch_instruction *)pc; 525 526 if (llbit) { 527 /* 528 * When the ll-sc combo is encountered, it is regarded as an single 529 * instruction. So don't clear llbit and reset CSR.FWPS.Skip until 530 * the llsc execution is completed. 531 */ 532 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 533 csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL); 534 goto out; 535 } 536 537 if (pc == current->thread.single_step) { 538 /* 539 * Certain insns are occasionally not skipped when CSR.FWPS.Skip is 540 * set, such as fld.d/fst.d. So singlestep needs to compare whether 541 * the csr_era is equal to the value of singlestep which last time set. 542 */ 543 if (!is_self_loop_ins(ip, regs)) { 544 /* 545 * Check if the given instruction the target pc is equal to the 546 * current pc, If yes, then we should not set the CSR.FWPS.SKIP 547 * bit to break the original instruction stream. 548 */ 549 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 550 goto out; 551 } 552 } 553 } else { 554 breakpoint_handler(regs); 555 watchpoint_handler(regs); 556 } 557 558 force_sig(SIGTRAP); 559 out: 560 #endif 561 irqentry_exit(regs, state); 562 } 563 564 asmlinkage void noinstr do_ri(struct pt_regs *regs) 565 { 566 int status = SIGILL; 567 unsigned int opcode = 0; 568 unsigned int __user *era = (unsigned int __user *)exception_era(regs); 569 irqentry_state_t state = irqentry_enter(regs); 570 571 local_irq_enable(); 572 current->thread.trap_nr = read_csr_excode(); 573 574 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 575 SIGILL) == NOTIFY_STOP) 576 goto out; 577 578 die_if_kernel("Reserved instruction in kernel code", regs); 579 580 if (unlikely(get_user(opcode, era) < 0)) { 581 status = SIGSEGV; 582 current->thread.error_code = 1; 583 } 584 585 force_sig(status); 586 587 out: 588 local_irq_disable(); 589 irqentry_exit(regs, state); 590 } 591 592 static void init_restore_fp(void) 593 { 594 if (!used_math()) { 595 /* First time FP context user. */ 596 init_fpu(); 597 } else { 598 /* This task has formerly used the FP context */ 599 if (!is_fpu_owner()) 600 own_fpu_inatomic(1); 601 } 602 603 BUG_ON(!is_fp_enabled()); 604 } 605 606 asmlinkage void noinstr do_fpu(struct pt_regs *regs) 607 { 608 irqentry_state_t state = irqentry_enter(regs); 609 610 local_irq_enable(); 611 die_if_kernel("do_fpu invoked from kernel context!", regs); 612 613 preempt_disable(); 614 init_restore_fp(); 615 preempt_enable(); 616 617 local_irq_disable(); 618 irqentry_exit(regs, state); 619 } 620 621 asmlinkage void noinstr do_lsx(struct pt_regs *regs) 622 { 623 irqentry_state_t state = irqentry_enter(regs); 624 625 local_irq_enable(); 626 force_sig(SIGILL); 627 local_irq_disable(); 628 629 irqentry_exit(regs, state); 630 } 631 632 asmlinkage void noinstr do_lasx(struct pt_regs *regs) 633 { 634 irqentry_state_t state = irqentry_enter(regs); 635 636 local_irq_enable(); 637 force_sig(SIGILL); 638 local_irq_disable(); 639 640 irqentry_exit(regs, state); 641 } 642 643 asmlinkage void noinstr do_lbt(struct pt_regs *regs) 644 { 645 irqentry_state_t state = irqentry_enter(regs); 646 647 local_irq_enable(); 648 force_sig(SIGILL); 649 local_irq_disable(); 650 651 irqentry_exit(regs, state); 652 } 653 654 asmlinkage void noinstr do_reserved(struct pt_regs *regs) 655 { 656 irqentry_state_t state = irqentry_enter(regs); 657 658 local_irq_enable(); 659 /* 660 * Game over - no way to handle this if it ever occurs. Most probably 661 * caused by a fatal error after another hardware/software error. 662 */ 663 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n", 664 read_csr_excode(), current->pid, current->comm); 665 die_if_kernel("do_reserved exception", regs); 666 force_sig(SIGUNUSED); 667 668 local_irq_disable(); 669 670 irqentry_exit(regs, state); 671 } 672 673 asmlinkage void cache_parity_error(void) 674 { 675 /* For the moment, report the problem and hang. */ 676 pr_err("Cache error exception:\n"); 677 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); 678 pr_err("csr_merrera == %016llx\n", csr_read64(LOONGARCH_CSR_MERRERA)); 679 panic("Can't handle the cache error!"); 680 } 681 682 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs) 683 { 684 struct pt_regs *old_regs; 685 686 irq_enter_rcu(); 687 old_regs = set_irq_regs(regs); 688 handle_arch_irq(regs); 689 set_irq_regs(old_regs); 690 irq_exit_rcu(); 691 } 692 693 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) 694 { 695 register int cpu; 696 register unsigned long stack; 697 irqentry_state_t state = irqentry_enter(regs); 698 699 cpu = smp_processor_id(); 700 701 if (on_irq_stack(cpu, sp)) 702 handle_loongarch_irq(regs); 703 else { 704 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START; 705 706 /* Save task's sp on IRQ stack for unwinding */ 707 *(unsigned long *)stack = sp; 708 709 __asm__ __volatile__( 710 "move $s0, $sp \n" /* Preserve sp */ 711 "move $sp, %[stk] \n" /* Switch stack */ 712 "move $a0, %[regs] \n" 713 "bl handle_loongarch_irq \n" 714 "move $sp, $s0 \n" /* Restore sp */ 715 : /* No outputs */ 716 : [stk] "r" (stack), [regs] "r" (regs) 717 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0", 718 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", 719 "memory"); 720 } 721 722 irqentry_exit(regs, state); 723 } 724 725 unsigned long eentry; 726 unsigned long tlbrentry; 727 728 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); 729 730 static void configure_exception_vector(void) 731 { 732 eentry = (unsigned long)exception_handlers; 733 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 734 735 csr_write64(eentry, LOONGARCH_CSR_EENTRY); 736 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 737 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 738 } 739 740 void per_cpu_trap_init(int cpu) 741 { 742 unsigned int i; 743 744 setup_vint_size(VECSIZE); 745 746 configure_exception_vector(); 747 748 if (!cpu_data[cpu].asid_cache) 749 cpu_data[cpu].asid_cache = asid_first_version(cpu); 750 751 mmgrab(&init_mm); 752 current->active_mm = &init_mm; 753 BUG_ON(current->mm); 754 enter_lazy_tlb(&init_mm, current); 755 756 /* Initialise exception handlers */ 757 if (cpu == 0) 758 for (i = 0; i < 64; i++) 759 set_handler(i * VECSIZE, handle_reserved, VECSIZE); 760 761 tlb_init(cpu); 762 cpu_cache_init(); 763 } 764 765 /* Install CPU exception handler */ 766 void set_handler(unsigned long offset, void *addr, unsigned long size) 767 { 768 memcpy((void *)(eentry + offset), addr, size); 769 local_flush_icache_range(eentry + offset, eentry + offset + size); 770 } 771 772 static const char panic_null_cerr[] = 773 "Trying to set NULL cache error exception handler\n"; 774 775 /* 776 * Install uncached CPU exception handler. 777 * This is suitable only for the cache error exception which is the only 778 * exception handler that is being run uncached. 779 */ 780 void set_merr_handler(unsigned long offset, void *addr, unsigned long size) 781 { 782 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry)); 783 784 if (!addr) 785 panic(panic_null_cerr); 786 787 memcpy((void *)(uncached_eentry + offset), addr, size); 788 } 789 790 void __init trap_init(void) 791 { 792 long i; 793 794 /* Set interrupt vector handler */ 795 for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++) 796 set_handler(i * VECSIZE, handle_vint, VECSIZE); 797 798 set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); 799 set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); 800 set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); 801 set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); 802 set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); 803 set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE); 804 set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE); 805 set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE); 806 set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE); 807 set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE); 808 set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE); 809 set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE); 810 811 cache_error_setup(); 812 813 local_flush_icache_range(eentry, eentry + 0x400); 814 } 815