1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 #include <linux/bitops.h> 7 #include <linux/bug.h> 8 #include <linux/compiler.h> 9 #include <linux/context_tracking.h> 10 #include <linux/entry-common.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/extable.h> 15 #include <linux/mm.h> 16 #include <linux/sched/mm.h> 17 #include <linux/sched/debug.h> 18 #include <linux/smp.h> 19 #include <linux/spinlock.h> 20 #include <linux/kallsyms.h> 21 #include <linux/memblock.h> 22 #include <linux/interrupt.h> 23 #include <linux/ptrace.h> 24 #include <linux/kgdb.h> 25 #include <linux/kdebug.h> 26 #include <linux/kprobes.h> 27 #include <linux/notifier.h> 28 #include <linux/irq.h> 29 #include <linux/perf_event.h> 30 31 #include <asm/addrspace.h> 32 #include <asm/bootinfo.h> 33 #include <asm/branch.h> 34 #include <asm/break.h> 35 #include <asm/cpu.h> 36 #include <asm/fpu.h> 37 #include <asm/loongarch.h> 38 #include <asm/mmu_context.h> 39 #include <asm/pgtable.h> 40 #include <asm/ptrace.h> 41 #include <asm/sections.h> 42 #include <asm/siginfo.h> 43 #include <asm/stacktrace.h> 44 #include <asm/tlb.h> 45 #include <asm/types.h> 46 #include <asm/unwind.h> 47 48 #include "access-helper.h" 49 50 extern asmlinkage void handle_ade(void); 51 extern asmlinkage void handle_ale(void); 52 extern asmlinkage void handle_sys(void); 53 extern asmlinkage void handle_bp(void); 54 extern asmlinkage void handle_ri(void); 55 extern asmlinkage void handle_fpu(void); 56 extern asmlinkage void handle_fpe(void); 57 extern asmlinkage void handle_lbt(void); 58 extern asmlinkage void handle_lsx(void); 59 extern asmlinkage void handle_lasx(void); 60 extern asmlinkage void handle_reserved(void); 61 extern asmlinkage void handle_watch(void); 62 extern asmlinkage void handle_vint(void); 63 64 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 65 const char *loglvl, bool user) 66 { 67 unsigned long addr; 68 struct unwind_state state; 69 struct pt_regs *pregs = (struct pt_regs *)regs; 70 71 if (!task) 72 task = current; 73 74 if (user_mode(regs)) 75 state.type = UNWINDER_GUESS; 76 77 printk("%sCall Trace:", loglvl); 78 for (unwind_start(&state, task, pregs); 79 !unwind_done(&state); unwind_next_frame(&state)) { 80 addr = unwind_get_return_address(&state); 81 print_ip_sym(loglvl, addr); 82 } 83 printk("%s\n", loglvl); 84 } 85 86 static void show_stacktrace(struct task_struct *task, 87 const struct pt_regs *regs, const char *loglvl, bool user) 88 { 89 int i; 90 const int field = 2 * sizeof(unsigned long); 91 unsigned long stackdata; 92 unsigned long *sp = (unsigned long *)regs->regs[3]; 93 94 printk("%sStack :", loglvl); 95 i = 0; 96 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 97 if (i && ((i % (64 / field)) == 0)) { 98 pr_cont("\n"); 99 printk("%s ", loglvl); 100 } 101 if (i > 39) { 102 pr_cont(" ..."); 103 break; 104 } 105 106 if (__get_addr(&stackdata, sp++, user)) { 107 pr_cont(" (Bad stack address)"); 108 break; 109 } 110 111 pr_cont(" %0*lx", field, stackdata); 112 i++; 113 } 114 pr_cont("\n"); 115 show_backtrace(task, regs, loglvl, user); 116 } 117 118 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 119 { 120 struct pt_regs regs; 121 122 regs.csr_crmd = 0; 123 if (sp) { 124 regs.csr_era = 0; 125 regs.regs[1] = 0; 126 regs.regs[3] = (unsigned long)sp; 127 } else { 128 if (!task || task == current) 129 prepare_frametrace(®s); 130 else { 131 regs.csr_era = task->thread.reg01; 132 regs.regs[1] = 0; 133 regs.regs[3] = task->thread.reg03; 134 regs.regs[22] = task->thread.reg22; 135 } 136 } 137 138 show_stacktrace(task, ®s, loglvl, false); 139 } 140 141 static void show_code(unsigned int *pc, bool user) 142 { 143 long i; 144 unsigned int insn; 145 146 printk("Code:"); 147 148 for(i = -3 ; i < 6 ; i++) { 149 if (__get_inst(&insn, pc + i, user)) { 150 pr_cont(" (Bad address in era)\n"); 151 break; 152 } 153 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 154 } 155 pr_cont("\n"); 156 } 157 158 static void __show_regs(const struct pt_regs *regs) 159 { 160 const int field = 2 * sizeof(unsigned long); 161 unsigned int excsubcode; 162 unsigned int exccode; 163 int i; 164 165 show_regs_print_info(KERN_DEFAULT); 166 167 /* 168 * Saved main processor registers 169 */ 170 for (i = 0; i < 32; ) { 171 if ((i % 4) == 0) 172 printk("$%2d :", i); 173 pr_cont(" %0*lx", field, regs->regs[i]); 174 175 i++; 176 if ((i % 4) == 0) 177 pr_cont("\n"); 178 } 179 180 /* 181 * Saved csr registers 182 */ 183 printk("era : %0*lx %pS\n", field, regs->csr_era, 184 (void *) regs->csr_era); 185 printk("ra : %0*lx %pS\n", field, regs->regs[1], 186 (void *) regs->regs[1]); 187 188 printk("CSR crmd: %08lx ", regs->csr_crmd); 189 printk("CSR prmd: %08lx ", regs->csr_prmd); 190 printk("CSR euen: %08lx ", regs->csr_euen); 191 printk("CSR ecfg: %08lx ", regs->csr_ecfg); 192 printk("CSR estat: %08lx ", regs->csr_estat); 193 194 pr_cont("\n"); 195 196 exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 197 excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT; 198 printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode); 199 200 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE) 201 printk("BadVA : %0*lx\n", field, regs->csr_badvaddr); 202 203 printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0), 204 cpu_family_string()); 205 } 206 207 void show_regs(struct pt_regs *regs) 208 { 209 __show_regs((struct pt_regs *)regs); 210 dump_stack(); 211 } 212 213 void show_registers(struct pt_regs *regs) 214 { 215 __show_regs(regs); 216 print_modules(); 217 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 218 current->comm, current->pid, current_thread_info(), current); 219 220 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 221 show_code((void *)regs->csr_era, user_mode(regs)); 222 printk("\n"); 223 } 224 225 static DEFINE_RAW_SPINLOCK(die_lock); 226 227 void __noreturn die(const char *str, struct pt_regs *regs) 228 { 229 static int die_counter; 230 int sig = SIGSEGV; 231 232 oops_enter(); 233 234 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 235 SIGSEGV) == NOTIFY_STOP) 236 sig = 0; 237 238 console_verbose(); 239 raw_spin_lock_irq(&die_lock); 240 bust_spinlocks(1); 241 242 printk("%s[#%d]:\n", str, ++die_counter); 243 show_registers(regs); 244 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 245 raw_spin_unlock_irq(&die_lock); 246 247 oops_exit(); 248 249 if (in_interrupt()) 250 panic("Fatal exception in interrupt"); 251 252 if (panic_on_oops) 253 panic("Fatal exception"); 254 255 make_task_dead(sig); 256 } 257 258 static inline void setup_vint_size(unsigned int size) 259 { 260 unsigned int vs; 261 262 vs = ilog2(size/4); 263 264 if (vs == 0 || vs > 7) 265 panic("vint_size %d Not support yet", vs); 266 267 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG); 268 } 269 270 /* 271 * Send SIGFPE according to FCSR Cause bits, which must have already 272 * been masked against Enable bits. This is impotant as Inexact can 273 * happen together with Overflow or Underflow, and `ptrace' can set 274 * any bits. 275 */ 276 void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr, 277 struct task_struct *tsk) 278 { 279 int si_code = FPE_FLTUNK; 280 281 if (fcsr & FPU_CSR_INV_X) 282 si_code = FPE_FLTINV; 283 else if (fcsr & FPU_CSR_DIV_X) 284 si_code = FPE_FLTDIV; 285 else if (fcsr & FPU_CSR_OVF_X) 286 si_code = FPE_FLTOVF; 287 else if (fcsr & FPU_CSR_UDF_X) 288 si_code = FPE_FLTUND; 289 else if (fcsr & FPU_CSR_INE_X) 290 si_code = FPE_FLTRES; 291 292 force_sig_fault(SIGFPE, si_code, fault_addr); 293 } 294 295 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr) 296 { 297 int si_code; 298 299 switch (sig) { 300 case 0: 301 return 0; 302 303 case SIGFPE: 304 force_fcsr_sig(fcsr, fault_addr, current); 305 return 1; 306 307 case SIGBUS: 308 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 309 return 1; 310 311 case SIGSEGV: 312 mmap_read_lock(current->mm); 313 if (vma_lookup(current->mm, (unsigned long)fault_addr)) 314 si_code = SEGV_ACCERR; 315 else 316 si_code = SEGV_MAPERR; 317 mmap_read_unlock(current->mm); 318 force_sig_fault(SIGSEGV, si_code, fault_addr); 319 return 1; 320 321 default: 322 force_sig(sig); 323 return 1; 324 } 325 } 326 327 /* 328 * Delayed fp exceptions when doing a lazy ctx switch 329 */ 330 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 331 { 332 int sig; 333 void __user *fault_addr; 334 irqentry_state_t state = irqentry_enter(regs); 335 336 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 337 SIGFPE) == NOTIFY_STOP) 338 goto out; 339 340 /* Clear FCSR.Cause before enabling interrupts */ 341 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr)); 342 local_irq_enable(); 343 344 die_if_kernel("FP exception in kernel code", regs); 345 346 sig = SIGFPE; 347 fault_addr = (void __user *) regs->csr_era; 348 349 /* Send a signal if required. */ 350 process_fpemu_return(sig, fault_addr, fcsr); 351 352 out: 353 local_irq_disable(); 354 irqentry_exit(regs, state); 355 } 356 357 asmlinkage void noinstr do_ade(struct pt_regs *regs) 358 { 359 irqentry_state_t state = irqentry_enter(regs); 360 361 die_if_kernel("Kernel ade access", regs); 362 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr); 363 364 irqentry_exit(regs, state); 365 } 366 367 asmlinkage void noinstr do_ale(struct pt_regs *regs) 368 { 369 irqentry_state_t state = irqentry_enter(regs); 370 371 die_if_kernel("Kernel ale access", regs); 372 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 373 374 irqentry_exit(regs, state); 375 } 376 377 asmlinkage void noinstr do_bp(struct pt_regs *regs) 378 { 379 bool user = user_mode(regs); 380 unsigned int opcode, bcode; 381 unsigned long era = exception_era(regs); 382 irqentry_state_t state = irqentry_enter(regs); 383 384 local_irq_enable(); 385 current->thread.trap_nr = read_csr_excode(); 386 if (__get_inst(&opcode, (u32 *)era, user)) 387 goto out_sigsegv; 388 389 bcode = (opcode & 0x7fff); 390 391 /* 392 * notify the kprobe handlers, if instruction is likely to 393 * pertain to them. 394 */ 395 switch (bcode) { 396 case BRK_KPROBE_BP: 397 if (notify_die(DIE_BREAK, "Kprobe", regs, bcode, 398 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 399 goto out; 400 else 401 break; 402 case BRK_KPROBE_SSTEPBP: 403 if (notify_die(DIE_SSTEPBP, "Kprobe_SingleStep", regs, bcode, 404 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 405 goto out; 406 else 407 break; 408 case BRK_UPROBE_BP: 409 if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode, 410 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 411 goto out; 412 else 413 break; 414 case BRK_UPROBE_XOLBP: 415 if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode, 416 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 417 goto out; 418 else 419 break; 420 default: 421 if (notify_die(DIE_TRAP, "Break", regs, bcode, 422 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 423 goto out; 424 else 425 break; 426 } 427 428 switch (bcode) { 429 case BRK_BUG: 430 die_if_kernel("Kernel bug detected", regs); 431 force_sig(SIGTRAP); 432 break; 433 case BRK_DIVZERO: 434 die_if_kernel("Break instruction in kernel code", regs); 435 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era); 436 break; 437 case BRK_OVERFLOW: 438 die_if_kernel("Break instruction in kernel code", regs); 439 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era); 440 break; 441 default: 442 die_if_kernel("Break instruction in kernel code", regs); 443 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era); 444 break; 445 } 446 447 out: 448 local_irq_disable(); 449 irqentry_exit(regs, state); 450 return; 451 452 out_sigsegv: 453 force_sig(SIGSEGV); 454 goto out; 455 } 456 457 asmlinkage void noinstr do_watch(struct pt_regs *regs) 458 { 459 pr_warn("Hardware watch point handler not implemented!\n"); 460 } 461 462 asmlinkage void noinstr do_ri(struct pt_regs *regs) 463 { 464 int status = -1; 465 unsigned int opcode = 0; 466 unsigned int __user *era = (unsigned int __user *)exception_era(regs); 467 unsigned long old_era = regs->csr_era; 468 unsigned long old_ra = regs->regs[1]; 469 irqentry_state_t state = irqentry_enter(regs); 470 471 local_irq_enable(); 472 current->thread.trap_nr = read_csr_excode(); 473 474 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 475 SIGILL) == NOTIFY_STOP) 476 goto out; 477 478 die_if_kernel("Reserved instruction in kernel code", regs); 479 480 compute_return_era(regs); 481 482 if (unlikely(get_user(opcode, era) < 0)) { 483 status = SIGSEGV; 484 current->thread.error_code = 1; 485 } 486 487 if (status < 0) 488 status = SIGILL; 489 490 if (unlikely(status > 0)) { 491 regs->csr_era = old_era; /* Undo skip-over. */ 492 regs->regs[1] = old_ra; 493 force_sig(status); 494 } 495 496 out: 497 local_irq_disable(); 498 irqentry_exit(regs, state); 499 } 500 501 static void init_restore_fp(void) 502 { 503 if (!used_math()) { 504 /* First time FP context user. */ 505 init_fpu(); 506 } else { 507 /* This task has formerly used the FP context */ 508 if (!is_fpu_owner()) 509 own_fpu_inatomic(1); 510 } 511 512 BUG_ON(!is_fp_enabled()); 513 } 514 515 asmlinkage void noinstr do_fpu(struct pt_regs *regs) 516 { 517 irqentry_state_t state = irqentry_enter(regs); 518 519 local_irq_enable(); 520 die_if_kernel("do_fpu invoked from kernel context!", regs); 521 522 preempt_disable(); 523 init_restore_fp(); 524 preempt_enable(); 525 526 local_irq_disable(); 527 irqentry_exit(regs, state); 528 } 529 530 asmlinkage void noinstr do_lsx(struct pt_regs *regs) 531 { 532 irqentry_state_t state = irqentry_enter(regs); 533 534 local_irq_enable(); 535 force_sig(SIGILL); 536 local_irq_disable(); 537 538 irqentry_exit(regs, state); 539 } 540 541 asmlinkage void noinstr do_lasx(struct pt_regs *regs) 542 { 543 irqentry_state_t state = irqentry_enter(regs); 544 545 local_irq_enable(); 546 force_sig(SIGILL); 547 local_irq_disable(); 548 549 irqentry_exit(regs, state); 550 } 551 552 asmlinkage void noinstr do_lbt(struct pt_regs *regs) 553 { 554 irqentry_state_t state = irqentry_enter(regs); 555 556 local_irq_enable(); 557 force_sig(SIGILL); 558 local_irq_disable(); 559 560 irqentry_exit(regs, state); 561 } 562 563 asmlinkage void noinstr do_reserved(struct pt_regs *regs) 564 { 565 irqentry_state_t state = irqentry_enter(regs); 566 567 local_irq_enable(); 568 /* 569 * Game over - no way to handle this if it ever occurs. Most probably 570 * caused by a fatal error after another hardware/software error. 571 */ 572 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n", 573 read_csr_excode(), current->pid, current->comm); 574 die_if_kernel("do_reserved exception", regs); 575 force_sig(SIGUNUSED); 576 577 local_irq_disable(); 578 579 irqentry_exit(regs, state); 580 } 581 582 asmlinkage void cache_parity_error(void) 583 { 584 /* For the moment, report the problem and hang. */ 585 pr_err("Cache error exception:\n"); 586 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); 587 pr_err("csr_merrera == %016llx\n", csr_read64(LOONGARCH_CSR_MERRERA)); 588 panic("Can't handle the cache error!"); 589 } 590 591 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs) 592 { 593 struct pt_regs *old_regs; 594 595 irq_enter_rcu(); 596 old_regs = set_irq_regs(regs); 597 handle_arch_irq(regs); 598 set_irq_regs(old_regs); 599 irq_exit_rcu(); 600 } 601 602 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) 603 { 604 register int cpu; 605 register unsigned long stack; 606 irqentry_state_t state = irqentry_enter(regs); 607 608 cpu = smp_processor_id(); 609 610 if (on_irq_stack(cpu, sp)) 611 handle_loongarch_irq(regs); 612 else { 613 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START; 614 615 /* Save task's sp on IRQ stack for unwinding */ 616 *(unsigned long *)stack = sp; 617 618 __asm__ __volatile__( 619 "move $s0, $sp \n" /* Preserve sp */ 620 "move $sp, %[stk] \n" /* Switch stack */ 621 "move $a0, %[regs] \n" 622 "bl handle_loongarch_irq \n" 623 "move $sp, $s0 \n" /* Restore sp */ 624 : /* No outputs */ 625 : [stk] "r" (stack), [regs] "r" (regs) 626 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0", 627 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", 628 "memory"); 629 } 630 631 irqentry_exit(regs, state); 632 } 633 634 extern void tlb_init(int cpu); 635 extern void cache_error_setup(void); 636 637 unsigned long eentry; 638 unsigned long tlbrentry; 639 640 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); 641 642 static void configure_exception_vector(void) 643 { 644 eentry = (unsigned long)exception_handlers; 645 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 646 647 csr_write64(eentry, LOONGARCH_CSR_EENTRY); 648 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 649 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 650 } 651 652 void per_cpu_trap_init(int cpu) 653 { 654 unsigned int i; 655 656 setup_vint_size(VECSIZE); 657 658 configure_exception_vector(); 659 660 if (!cpu_data[cpu].asid_cache) 661 cpu_data[cpu].asid_cache = asid_first_version(cpu); 662 663 mmgrab(&init_mm); 664 current->active_mm = &init_mm; 665 BUG_ON(current->mm); 666 enter_lazy_tlb(&init_mm, current); 667 668 /* Initialise exception handlers */ 669 if (cpu == 0) 670 for (i = 0; i < 64; i++) 671 set_handler(i * VECSIZE, handle_reserved, VECSIZE); 672 673 tlb_init(cpu); 674 cpu_cache_init(); 675 } 676 677 /* Install CPU exception handler */ 678 void set_handler(unsigned long offset, void *addr, unsigned long size) 679 { 680 memcpy((void *)(eentry + offset), addr, size); 681 local_flush_icache_range(eentry + offset, eentry + offset + size); 682 } 683 684 static const char panic_null_cerr[] = 685 "Trying to set NULL cache error exception handler\n"; 686 687 /* 688 * Install uncached CPU exception handler. 689 * This is suitable only for the cache error exception which is the only 690 * exception handler that is being run uncached. 691 */ 692 void set_merr_handler(unsigned long offset, void *addr, unsigned long size) 693 { 694 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry)); 695 696 if (!addr) 697 panic(panic_null_cerr); 698 699 memcpy((void *)(uncached_eentry + offset), addr, size); 700 } 701 702 void __init trap_init(void) 703 { 704 long i; 705 706 /* Set interrupt vector handler */ 707 for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++) 708 set_handler(i * VECSIZE, handle_vint, VECSIZE); 709 710 set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); 711 set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); 712 set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); 713 set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); 714 set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); 715 set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE); 716 set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE); 717 set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE); 718 set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE); 719 set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE); 720 set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE); 721 set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE); 722 723 cache_error_setup(); 724 725 local_flush_icache_range(eentry, eentry + 0x400); 726 } 727