1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 #include <linux/bitops.h> 7 #include <linux/bug.h> 8 #include <linux/compiler.h> 9 #include <linux/context_tracking.h> 10 #include <linux/entry-common.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/kexec.h> 14 #include <linux/module.h> 15 #include <linux/extable.h> 16 #include <linux/mm.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/debug.h> 19 #include <linux/smp.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/memblock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ptrace.h> 25 #include <linux/kgdb.h> 26 #include <linux/kdebug.h> 27 #include <linux/kprobes.h> 28 #include <linux/notifier.h> 29 #include <linux/irq.h> 30 #include <linux/perf_event.h> 31 32 #include <asm/addrspace.h> 33 #include <asm/bootinfo.h> 34 #include <asm/branch.h> 35 #include <asm/break.h> 36 #include <asm/cpu.h> 37 #include <asm/fpu.h> 38 #include <asm/loongarch.h> 39 #include <asm/mmu_context.h> 40 #include <asm/pgtable.h> 41 #include <asm/ptrace.h> 42 #include <asm/sections.h> 43 #include <asm/siginfo.h> 44 #include <asm/stacktrace.h> 45 #include <asm/tlb.h> 46 #include <asm/types.h> 47 #include <asm/unwind.h> 48 49 #include "access-helper.h" 50 51 extern asmlinkage void handle_ade(void); 52 extern asmlinkage void handle_ale(void); 53 extern asmlinkage void handle_sys(void); 54 extern asmlinkage void handle_bp(void); 55 extern asmlinkage void handle_ri(void); 56 extern asmlinkage void handle_fpu(void); 57 extern asmlinkage void handle_fpe(void); 58 extern asmlinkage void handle_lbt(void); 59 extern asmlinkage void handle_lsx(void); 60 extern asmlinkage void handle_lasx(void); 61 extern asmlinkage void handle_reserved(void); 62 extern asmlinkage void handle_watch(void); 63 extern asmlinkage void handle_vint(void); 64 65 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 66 const char *loglvl, bool user) 67 { 68 unsigned long addr; 69 struct unwind_state state; 70 struct pt_regs *pregs = (struct pt_regs *)regs; 71 72 if (!task) 73 task = current; 74 75 if (user_mode(regs)) 76 state.type = UNWINDER_GUESS; 77 78 printk("%sCall Trace:", loglvl); 79 for (unwind_start(&state, task, pregs); 80 !unwind_done(&state); unwind_next_frame(&state)) { 81 addr = unwind_get_return_address(&state); 82 print_ip_sym(loglvl, addr); 83 } 84 printk("%s\n", loglvl); 85 } 86 87 static void show_stacktrace(struct task_struct *task, 88 const struct pt_regs *regs, const char *loglvl, bool user) 89 { 90 int i; 91 const int field = 2 * sizeof(unsigned long); 92 unsigned long stackdata; 93 unsigned long *sp = (unsigned long *)regs->regs[3]; 94 95 printk("%sStack :", loglvl); 96 i = 0; 97 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 98 if (i && ((i % (64 / field)) == 0)) { 99 pr_cont("\n"); 100 printk("%s ", loglvl); 101 } 102 if (i > 39) { 103 pr_cont(" ..."); 104 break; 105 } 106 107 if (__get_addr(&stackdata, sp++, user)) { 108 pr_cont(" (Bad stack address)"); 109 break; 110 } 111 112 pr_cont(" %0*lx", field, stackdata); 113 i++; 114 } 115 pr_cont("\n"); 116 show_backtrace(task, regs, loglvl, user); 117 } 118 119 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 120 { 121 struct pt_regs regs; 122 123 regs.csr_crmd = 0; 124 if (sp) { 125 regs.csr_era = 0; 126 regs.regs[1] = 0; 127 regs.regs[3] = (unsigned long)sp; 128 } else { 129 if (!task || task == current) 130 prepare_frametrace(®s); 131 else { 132 regs.csr_era = task->thread.reg01; 133 regs.regs[1] = 0; 134 regs.regs[3] = task->thread.reg03; 135 regs.regs[22] = task->thread.reg22; 136 } 137 } 138 139 show_stacktrace(task, ®s, loglvl, false); 140 } 141 142 static void show_code(unsigned int *pc, bool user) 143 { 144 long i; 145 unsigned int insn; 146 147 printk("Code:"); 148 149 for(i = -3 ; i < 6 ; i++) { 150 if (__get_inst(&insn, pc + i, user)) { 151 pr_cont(" (Bad address in era)\n"); 152 break; 153 } 154 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 155 } 156 pr_cont("\n"); 157 } 158 159 static void __show_regs(const struct pt_regs *regs) 160 { 161 const int field = 2 * sizeof(unsigned long); 162 unsigned int excsubcode; 163 unsigned int exccode; 164 int i; 165 166 show_regs_print_info(KERN_DEFAULT); 167 168 /* 169 * Saved main processor registers 170 */ 171 for (i = 0; i < 32; ) { 172 if ((i % 4) == 0) 173 printk("$%2d :", i); 174 pr_cont(" %0*lx", field, regs->regs[i]); 175 176 i++; 177 if ((i % 4) == 0) 178 pr_cont("\n"); 179 } 180 181 /* 182 * Saved csr registers 183 */ 184 printk("era : %0*lx %pS\n", field, regs->csr_era, 185 (void *) regs->csr_era); 186 printk("ra : %0*lx %pS\n", field, regs->regs[1], 187 (void *) regs->regs[1]); 188 189 printk("CSR crmd: %08lx ", regs->csr_crmd); 190 printk("CSR prmd: %08lx ", regs->csr_prmd); 191 printk("CSR euen: %08lx ", regs->csr_euen); 192 printk("CSR ecfg: %08lx ", regs->csr_ecfg); 193 printk("CSR estat: %08lx ", regs->csr_estat); 194 195 pr_cont("\n"); 196 197 exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 198 excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT; 199 printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode); 200 201 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE) 202 printk("BadVA : %0*lx\n", field, regs->csr_badvaddr); 203 204 printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0), 205 cpu_family_string()); 206 } 207 208 void show_regs(struct pt_regs *regs) 209 { 210 __show_regs((struct pt_regs *)regs); 211 dump_stack(); 212 } 213 214 void show_registers(struct pt_regs *regs) 215 { 216 __show_regs(regs); 217 print_modules(); 218 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 219 current->comm, current->pid, current_thread_info(), current); 220 221 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 222 show_code((void *)regs->csr_era, user_mode(regs)); 223 printk("\n"); 224 } 225 226 static DEFINE_RAW_SPINLOCK(die_lock); 227 228 void __noreturn die(const char *str, struct pt_regs *regs) 229 { 230 static int die_counter; 231 int sig = SIGSEGV; 232 233 oops_enter(); 234 235 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 236 SIGSEGV) == NOTIFY_STOP) 237 sig = 0; 238 239 console_verbose(); 240 raw_spin_lock_irq(&die_lock); 241 bust_spinlocks(1); 242 243 printk("%s[#%d]:\n", str, ++die_counter); 244 show_registers(regs); 245 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 246 raw_spin_unlock_irq(&die_lock); 247 248 oops_exit(); 249 250 if (regs && kexec_should_crash(current)) 251 crash_kexec(regs); 252 253 if (in_interrupt()) 254 panic("Fatal exception in interrupt"); 255 256 if (panic_on_oops) 257 panic("Fatal exception"); 258 259 make_task_dead(sig); 260 } 261 262 static inline void setup_vint_size(unsigned int size) 263 { 264 unsigned int vs; 265 266 vs = ilog2(size/4); 267 268 if (vs == 0 || vs > 7) 269 panic("vint_size %d Not support yet", vs); 270 271 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG); 272 } 273 274 /* 275 * Send SIGFPE according to FCSR Cause bits, which must have already 276 * been masked against Enable bits. This is impotant as Inexact can 277 * happen together with Overflow or Underflow, and `ptrace' can set 278 * any bits. 279 */ 280 void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr, 281 struct task_struct *tsk) 282 { 283 int si_code = FPE_FLTUNK; 284 285 if (fcsr & FPU_CSR_INV_X) 286 si_code = FPE_FLTINV; 287 else if (fcsr & FPU_CSR_DIV_X) 288 si_code = FPE_FLTDIV; 289 else if (fcsr & FPU_CSR_OVF_X) 290 si_code = FPE_FLTOVF; 291 else if (fcsr & FPU_CSR_UDF_X) 292 si_code = FPE_FLTUND; 293 else if (fcsr & FPU_CSR_INE_X) 294 si_code = FPE_FLTRES; 295 296 force_sig_fault(SIGFPE, si_code, fault_addr); 297 } 298 299 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr) 300 { 301 int si_code; 302 303 switch (sig) { 304 case 0: 305 return 0; 306 307 case SIGFPE: 308 force_fcsr_sig(fcsr, fault_addr, current); 309 return 1; 310 311 case SIGBUS: 312 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 313 return 1; 314 315 case SIGSEGV: 316 mmap_read_lock(current->mm); 317 if (vma_lookup(current->mm, (unsigned long)fault_addr)) 318 si_code = SEGV_ACCERR; 319 else 320 si_code = SEGV_MAPERR; 321 mmap_read_unlock(current->mm); 322 force_sig_fault(SIGSEGV, si_code, fault_addr); 323 return 1; 324 325 default: 326 force_sig(sig); 327 return 1; 328 } 329 } 330 331 /* 332 * Delayed fp exceptions when doing a lazy ctx switch 333 */ 334 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 335 { 336 int sig; 337 void __user *fault_addr; 338 irqentry_state_t state = irqentry_enter(regs); 339 340 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 341 SIGFPE) == NOTIFY_STOP) 342 goto out; 343 344 /* Clear FCSR.Cause before enabling interrupts */ 345 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr)); 346 local_irq_enable(); 347 348 die_if_kernel("FP exception in kernel code", regs); 349 350 sig = SIGFPE; 351 fault_addr = (void __user *) regs->csr_era; 352 353 /* Send a signal if required. */ 354 process_fpemu_return(sig, fault_addr, fcsr); 355 356 out: 357 local_irq_disable(); 358 irqentry_exit(regs, state); 359 } 360 361 asmlinkage void noinstr do_ade(struct pt_regs *regs) 362 { 363 irqentry_state_t state = irqentry_enter(regs); 364 365 die_if_kernel("Kernel ade access", regs); 366 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr); 367 368 irqentry_exit(regs, state); 369 } 370 371 /* sysctl hooks */ 372 int unaligned_enabled __read_mostly = 1; /* Enabled by default */ 373 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */ 374 375 asmlinkage void noinstr do_ale(struct pt_regs *regs) 376 { 377 unsigned int *pc; 378 irqentry_state_t state = irqentry_enter(regs); 379 380 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr); 381 382 /* 383 * Did we catch a fault trying to load an instruction? 384 */ 385 if (regs->csr_badvaddr == regs->csr_era) 386 goto sigbus; 387 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) 388 goto sigbus; 389 if (!unaligned_enabled) 390 goto sigbus; 391 if (!no_unaligned_warning) 392 show_registers(regs); 393 394 pc = (unsigned int *)exception_era(regs); 395 396 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc); 397 398 goto out; 399 400 sigbus: 401 die_if_kernel("Kernel ale access", regs); 402 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 403 404 out: 405 irqentry_exit(regs, state); 406 } 407 408 #ifdef CONFIG_GENERIC_BUG 409 int is_valid_bugaddr(unsigned long addr) 410 { 411 return 1; 412 } 413 #endif /* CONFIG_GENERIC_BUG */ 414 415 static void bug_handler(struct pt_regs *regs) 416 { 417 switch (report_bug(regs->csr_era, regs)) { 418 case BUG_TRAP_TYPE_BUG: 419 case BUG_TRAP_TYPE_NONE: 420 die_if_kernel("Oops - BUG", regs); 421 force_sig(SIGTRAP); 422 break; 423 424 case BUG_TRAP_TYPE_WARN: 425 /* Skip the BUG instruction and continue */ 426 regs->csr_era += LOONGARCH_INSN_SIZE; 427 break; 428 } 429 } 430 431 asmlinkage void noinstr do_bp(struct pt_regs *regs) 432 { 433 bool user = user_mode(regs); 434 unsigned int opcode, bcode; 435 unsigned long era = exception_era(regs); 436 irqentry_state_t state = irqentry_enter(regs); 437 438 local_irq_enable(); 439 current->thread.trap_nr = read_csr_excode(); 440 if (__get_inst(&opcode, (u32 *)era, user)) 441 goto out_sigsegv; 442 443 bcode = (opcode & 0x7fff); 444 445 /* 446 * notify the kprobe handlers, if instruction is likely to 447 * pertain to them. 448 */ 449 switch (bcode) { 450 case BRK_KPROBE_BP: 451 if (notify_die(DIE_BREAK, "Kprobe", regs, bcode, 452 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 453 goto out; 454 else 455 break; 456 case BRK_KPROBE_SSTEPBP: 457 if (notify_die(DIE_SSTEPBP, "Kprobe_SingleStep", regs, bcode, 458 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 459 goto out; 460 else 461 break; 462 case BRK_UPROBE_BP: 463 if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode, 464 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 465 goto out; 466 else 467 break; 468 case BRK_UPROBE_XOLBP: 469 if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode, 470 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 471 goto out; 472 else 473 break; 474 default: 475 if (notify_die(DIE_TRAP, "Break", regs, bcode, 476 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 477 goto out; 478 else 479 break; 480 } 481 482 switch (bcode) { 483 case BRK_BUG: 484 bug_handler(regs); 485 break; 486 case BRK_DIVZERO: 487 die_if_kernel("Break instruction in kernel code", regs); 488 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era); 489 break; 490 case BRK_OVERFLOW: 491 die_if_kernel("Break instruction in kernel code", regs); 492 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era); 493 break; 494 default: 495 die_if_kernel("Break instruction in kernel code", regs); 496 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era); 497 break; 498 } 499 500 out: 501 local_irq_disable(); 502 irqentry_exit(regs, state); 503 return; 504 505 out_sigsegv: 506 force_sig(SIGSEGV); 507 goto out; 508 } 509 510 asmlinkage void noinstr do_watch(struct pt_regs *regs) 511 { 512 pr_warn("Hardware watch point handler not implemented!\n"); 513 } 514 515 asmlinkage void noinstr do_ri(struct pt_regs *regs) 516 { 517 int status = SIGILL; 518 unsigned int opcode = 0; 519 unsigned int __user *era = (unsigned int __user *)exception_era(regs); 520 irqentry_state_t state = irqentry_enter(regs); 521 522 local_irq_enable(); 523 current->thread.trap_nr = read_csr_excode(); 524 525 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 526 SIGILL) == NOTIFY_STOP) 527 goto out; 528 529 die_if_kernel("Reserved instruction in kernel code", regs); 530 531 if (unlikely(get_user(opcode, era) < 0)) { 532 status = SIGSEGV; 533 current->thread.error_code = 1; 534 } 535 536 force_sig(status); 537 538 out: 539 local_irq_disable(); 540 irqentry_exit(regs, state); 541 } 542 543 static void init_restore_fp(void) 544 { 545 if (!used_math()) { 546 /* First time FP context user. */ 547 init_fpu(); 548 } else { 549 /* This task has formerly used the FP context */ 550 if (!is_fpu_owner()) 551 own_fpu_inatomic(1); 552 } 553 554 BUG_ON(!is_fp_enabled()); 555 } 556 557 asmlinkage void noinstr do_fpu(struct pt_regs *regs) 558 { 559 irqentry_state_t state = irqentry_enter(regs); 560 561 local_irq_enable(); 562 die_if_kernel("do_fpu invoked from kernel context!", regs); 563 564 preempt_disable(); 565 init_restore_fp(); 566 preempt_enable(); 567 568 local_irq_disable(); 569 irqentry_exit(regs, state); 570 } 571 572 asmlinkage void noinstr do_lsx(struct pt_regs *regs) 573 { 574 irqentry_state_t state = irqentry_enter(regs); 575 576 local_irq_enable(); 577 force_sig(SIGILL); 578 local_irq_disable(); 579 580 irqentry_exit(regs, state); 581 } 582 583 asmlinkage void noinstr do_lasx(struct pt_regs *regs) 584 { 585 irqentry_state_t state = irqentry_enter(regs); 586 587 local_irq_enable(); 588 force_sig(SIGILL); 589 local_irq_disable(); 590 591 irqentry_exit(regs, state); 592 } 593 594 asmlinkage void noinstr do_lbt(struct pt_regs *regs) 595 { 596 irqentry_state_t state = irqentry_enter(regs); 597 598 local_irq_enable(); 599 force_sig(SIGILL); 600 local_irq_disable(); 601 602 irqentry_exit(regs, state); 603 } 604 605 asmlinkage void noinstr do_reserved(struct pt_regs *regs) 606 { 607 irqentry_state_t state = irqentry_enter(regs); 608 609 local_irq_enable(); 610 /* 611 * Game over - no way to handle this if it ever occurs. Most probably 612 * caused by a fatal error after another hardware/software error. 613 */ 614 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n", 615 read_csr_excode(), current->pid, current->comm); 616 die_if_kernel("do_reserved exception", regs); 617 force_sig(SIGUNUSED); 618 619 local_irq_disable(); 620 621 irqentry_exit(regs, state); 622 } 623 624 asmlinkage void cache_parity_error(void) 625 { 626 /* For the moment, report the problem and hang. */ 627 pr_err("Cache error exception:\n"); 628 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); 629 pr_err("csr_merrera == %016llx\n", csr_read64(LOONGARCH_CSR_MERRERA)); 630 panic("Can't handle the cache error!"); 631 } 632 633 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs) 634 { 635 struct pt_regs *old_regs; 636 637 irq_enter_rcu(); 638 old_regs = set_irq_regs(regs); 639 handle_arch_irq(regs); 640 set_irq_regs(old_regs); 641 irq_exit_rcu(); 642 } 643 644 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) 645 { 646 register int cpu; 647 register unsigned long stack; 648 irqentry_state_t state = irqentry_enter(regs); 649 650 cpu = smp_processor_id(); 651 652 if (on_irq_stack(cpu, sp)) 653 handle_loongarch_irq(regs); 654 else { 655 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START; 656 657 /* Save task's sp on IRQ stack for unwinding */ 658 *(unsigned long *)stack = sp; 659 660 __asm__ __volatile__( 661 "move $s0, $sp \n" /* Preserve sp */ 662 "move $sp, %[stk] \n" /* Switch stack */ 663 "move $a0, %[regs] \n" 664 "bl handle_loongarch_irq \n" 665 "move $sp, $s0 \n" /* Restore sp */ 666 : /* No outputs */ 667 : [stk] "r" (stack), [regs] "r" (regs) 668 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0", 669 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", 670 "memory"); 671 } 672 673 irqentry_exit(regs, state); 674 } 675 676 unsigned long eentry; 677 unsigned long tlbrentry; 678 679 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); 680 681 static void configure_exception_vector(void) 682 { 683 eentry = (unsigned long)exception_handlers; 684 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 685 686 csr_write64(eentry, LOONGARCH_CSR_EENTRY); 687 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 688 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 689 } 690 691 void per_cpu_trap_init(int cpu) 692 { 693 unsigned int i; 694 695 setup_vint_size(VECSIZE); 696 697 configure_exception_vector(); 698 699 if (!cpu_data[cpu].asid_cache) 700 cpu_data[cpu].asid_cache = asid_first_version(cpu); 701 702 mmgrab(&init_mm); 703 current->active_mm = &init_mm; 704 BUG_ON(current->mm); 705 enter_lazy_tlb(&init_mm, current); 706 707 /* Initialise exception handlers */ 708 if (cpu == 0) 709 for (i = 0; i < 64; i++) 710 set_handler(i * VECSIZE, handle_reserved, VECSIZE); 711 712 tlb_init(cpu); 713 cpu_cache_init(); 714 } 715 716 /* Install CPU exception handler */ 717 void set_handler(unsigned long offset, void *addr, unsigned long size) 718 { 719 memcpy((void *)(eentry + offset), addr, size); 720 local_flush_icache_range(eentry + offset, eentry + offset + size); 721 } 722 723 static const char panic_null_cerr[] = 724 "Trying to set NULL cache error exception handler\n"; 725 726 /* 727 * Install uncached CPU exception handler. 728 * This is suitable only for the cache error exception which is the only 729 * exception handler that is being run uncached. 730 */ 731 void set_merr_handler(unsigned long offset, void *addr, unsigned long size) 732 { 733 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry)); 734 735 if (!addr) 736 panic(panic_null_cerr); 737 738 memcpy((void *)(uncached_eentry + offset), addr, size); 739 } 740 741 void __init trap_init(void) 742 { 743 long i; 744 745 /* Set interrupt vector handler */ 746 for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++) 747 set_handler(i * VECSIZE, handle_vint, VECSIZE); 748 749 set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); 750 set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); 751 set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); 752 set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); 753 set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); 754 set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE); 755 set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE); 756 set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE); 757 set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE); 758 set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE); 759 set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE); 760 set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE); 761 762 cache_error_setup(); 763 764 local_flush_icache_range(eentry, eentry + 0x400); 765 } 766