1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Hanlu Li <lihanlu@loongson.cn> 4 * Huacai Chen <chenhuacai@loongson.cn> 5 * 6 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 7 * 8 * Derived from MIPS: 9 * Copyright (C) 1992 Ross Biro 10 * Copyright (C) Linus Torvalds 11 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle 12 * Copyright (C) 1996 David S. Miller 13 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 14 * Copyright (C) 1999 MIPS Technologies, Inc. 15 * Copyright (C) 2000 Ulf Carlsson 16 */ 17 #include <linux/kernel.h> 18 #include <linux/audit.h> 19 #include <linux/compiler.h> 20 #include <linux/context_tracking.h> 21 #include <linux/elf.h> 22 #include <linux/errno.h> 23 #include <linux/hw_breakpoint.h> 24 #include <linux/mm.h> 25 #include <linux/nospec.h> 26 #include <linux/ptrace.h> 27 #include <linux/regset.h> 28 #include <linux/sched.h> 29 #include <linux/sched/task_stack.h> 30 #include <linux/security.h> 31 #include <linux/smp.h> 32 #include <linux/stddef.h> 33 #include <linux/seccomp.h> 34 #include <linux/thread_info.h> 35 #include <linux/uaccess.h> 36 37 #include <asm/byteorder.h> 38 #include <asm/cpu.h> 39 #include <asm/cpu-info.h> 40 #include <asm/fpu.h> 41 #include <asm/lbt.h> 42 #include <asm/loongarch.h> 43 #include <asm/page.h> 44 #include <asm/pgtable.h> 45 #include <asm/processor.h> 46 #include <asm/ptrace.h> 47 #include <asm/reg.h> 48 #include <asm/syscall.h> 49 50 static void init_fp_ctx(struct task_struct *target) 51 { 52 /* The target already has context */ 53 if (tsk_used_math(target)) 54 return; 55 56 /* Begin with data registers set to all 1s... */ 57 memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr)); 58 set_stopped_child_used_math(target); 59 } 60 61 /* 62 * Called by kernel/ptrace.c when detaching.. 63 * 64 * Make sure single step bits etc are not set. 65 */ 66 void ptrace_disable(struct task_struct *child) 67 { 68 /* Don't load the watchpoint registers for the ex-child. */ 69 clear_tsk_thread_flag(child, TIF_LOAD_WATCH); 70 clear_tsk_thread_flag(child, TIF_SINGLESTEP); 71 } 72 73 /* regset get/set implementations */ 74 75 static int gpr_get(struct task_struct *target, 76 const struct user_regset *regset, 77 struct membuf to) 78 { 79 int r; 80 struct pt_regs *regs = task_pt_regs(target); 81 82 r = membuf_write(&to, ®s->regs, sizeof(u64) * GPR_NUM); 83 r = membuf_write(&to, ®s->orig_a0, sizeof(u64)); 84 r = membuf_write(&to, ®s->csr_era, sizeof(u64)); 85 r = membuf_write(&to, ®s->csr_badvaddr, sizeof(u64)); 86 87 return r; 88 } 89 90 static int gpr_set(struct task_struct *target, 91 const struct user_regset *regset, 92 unsigned int pos, unsigned int count, 93 const void *kbuf, const void __user *ubuf) 94 { 95 int err; 96 int a0_start = sizeof(u64) * GPR_NUM; 97 int era_start = a0_start + sizeof(u64); 98 int badvaddr_start = era_start + sizeof(u64); 99 struct pt_regs *regs = task_pt_regs(target); 100 101 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 102 ®s->regs, 103 0, a0_start); 104 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 105 ®s->orig_a0, 106 a0_start, a0_start + sizeof(u64)); 107 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 108 ®s->csr_era, 109 era_start, era_start + sizeof(u64)); 110 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 111 ®s->csr_badvaddr, 112 badvaddr_start, badvaddr_start + sizeof(u64)); 113 114 return err; 115 } 116 117 118 /* 119 * Get the general floating-point registers. 120 */ 121 static int gfpr_get(struct task_struct *target, struct membuf *to) 122 { 123 return membuf_write(to, &target->thread.fpu.fpr, 124 sizeof(elf_fpreg_t) * NUM_FPU_REGS); 125 } 126 127 static int gfpr_get_simd(struct task_struct *target, struct membuf *to) 128 { 129 int i, r; 130 u64 fpr_val; 131 132 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); 133 for (i = 0; i < NUM_FPU_REGS; i++) { 134 fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0); 135 r = membuf_write(to, &fpr_val, sizeof(elf_fpreg_t)); 136 } 137 138 return r; 139 } 140 141 /* 142 * Choose the appropriate helper for general registers, and then copy 143 * the FCC and FCSR registers separately. 144 */ 145 static int fpr_get(struct task_struct *target, 146 const struct user_regset *regset, 147 struct membuf to) 148 { 149 int r; 150 151 save_fpu_regs(target); 152 153 if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) 154 r = gfpr_get(target, &to); 155 else 156 r = gfpr_get_simd(target, &to); 157 158 r = membuf_write(&to, &target->thread.fpu.fcc, sizeof(target->thread.fpu.fcc)); 159 r = membuf_write(&to, &target->thread.fpu.fcsr, sizeof(target->thread.fpu.fcsr)); 160 161 return r; 162 } 163 164 static int gfpr_set(struct task_struct *target, 165 unsigned int *pos, unsigned int *count, 166 const void **kbuf, const void __user **ubuf) 167 { 168 return user_regset_copyin(pos, count, kbuf, ubuf, 169 &target->thread.fpu.fpr, 170 0, NUM_FPU_REGS * sizeof(elf_fpreg_t)); 171 } 172 173 static int gfpr_set_simd(struct task_struct *target, 174 unsigned int *pos, unsigned int *count, 175 const void **kbuf, const void __user **ubuf) 176 { 177 int i, err; 178 u64 fpr_val; 179 180 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); 181 for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) { 182 err = user_regset_copyin(pos, count, kbuf, ubuf, 183 &fpr_val, i * sizeof(elf_fpreg_t), 184 (i + 1) * sizeof(elf_fpreg_t)); 185 if (err) 186 return err; 187 set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val); 188 } 189 190 return 0; 191 } 192 193 /* 194 * Choose the appropriate helper for general registers, and then copy 195 * the FCC register separately. 196 */ 197 static int fpr_set(struct task_struct *target, 198 const struct user_regset *regset, 199 unsigned int pos, unsigned int count, 200 const void *kbuf, const void __user *ubuf) 201 { 202 const int fcc_start = NUM_FPU_REGS * sizeof(elf_fpreg_t); 203 const int fcsr_start = fcc_start + sizeof(u64); 204 int err; 205 206 BUG_ON(count % sizeof(elf_fpreg_t)); 207 if (pos + count > sizeof(elf_fpregset_t)) 208 return -EIO; 209 210 init_fp_ctx(target); 211 212 if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) 213 err = gfpr_set(target, &pos, &count, &kbuf, &ubuf); 214 else 215 err = gfpr_set_simd(target, &pos, &count, &kbuf, &ubuf); 216 if (err) 217 return err; 218 219 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 220 &target->thread.fpu.fcc, fcc_start, 221 fcc_start + sizeof(u64)); 222 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 223 &target->thread.fpu.fcsr, fcsr_start, 224 fcsr_start + sizeof(u32)); 225 226 return err; 227 } 228 229 static int cfg_get(struct task_struct *target, 230 const struct user_regset *regset, 231 struct membuf to) 232 { 233 int i, r; 234 u32 cfg_val; 235 236 i = 0; 237 while (to.left > 0) { 238 cfg_val = read_cpucfg(i++); 239 r = membuf_write(&to, &cfg_val, sizeof(u32)); 240 } 241 242 return r; 243 } 244 245 /* 246 * CFG registers are read-only. 247 */ 248 static int cfg_set(struct task_struct *target, 249 const struct user_regset *regset, 250 unsigned int pos, unsigned int count, 251 const void *kbuf, const void __user *ubuf) 252 { 253 return 0; 254 } 255 256 #ifdef CONFIG_CPU_HAS_LSX 257 258 static void copy_pad_fprs(struct task_struct *target, 259 const struct user_regset *regset, 260 struct membuf *to, unsigned int live_sz) 261 { 262 int i, j; 263 unsigned long long fill = ~0ull; 264 unsigned int cp_sz, pad_sz; 265 266 cp_sz = min(regset->size, live_sz); 267 pad_sz = regset->size - cp_sz; 268 WARN_ON(pad_sz % sizeof(fill)); 269 270 for (i = 0; i < NUM_FPU_REGS; i++) { 271 membuf_write(to, &target->thread.fpu.fpr[i], cp_sz); 272 for (j = 0; j < (pad_sz / sizeof(fill)); j++) { 273 membuf_store(to, fill); 274 } 275 } 276 } 277 278 static int simd_get(struct task_struct *target, 279 const struct user_regset *regset, 280 struct membuf to) 281 { 282 const unsigned int wr_size = NUM_FPU_REGS * regset->size; 283 284 save_fpu_regs(target); 285 286 if (!tsk_used_math(target)) { 287 /* The task hasn't used FP or LSX, fill with 0xff */ 288 copy_pad_fprs(target, regset, &to, 0); 289 } else if (!test_tsk_thread_flag(target, TIF_LSX_CTX_LIVE)) { 290 /* Copy scalar FP context, fill the rest with 0xff */ 291 copy_pad_fprs(target, regset, &to, 8); 292 #ifdef CONFIG_CPU_HAS_LASX 293 } else if (!test_tsk_thread_flag(target, TIF_LASX_CTX_LIVE)) { 294 /* Copy LSX 128 Bit context, fill the rest with 0xff */ 295 copy_pad_fprs(target, regset, &to, 16); 296 #endif 297 } else if (sizeof(target->thread.fpu.fpr[0]) == regset->size) { 298 /* Trivially copy the vector registers */ 299 membuf_write(&to, &target->thread.fpu.fpr, wr_size); 300 } else { 301 /* Copy as much context as possible, fill the rest with 0xff */ 302 copy_pad_fprs(target, regset, &to, sizeof(target->thread.fpu.fpr[0])); 303 } 304 305 return 0; 306 } 307 308 static int simd_set(struct task_struct *target, 309 const struct user_regset *regset, 310 unsigned int pos, unsigned int count, 311 const void *kbuf, const void __user *ubuf) 312 { 313 const unsigned int wr_size = NUM_FPU_REGS * regset->size; 314 unsigned int cp_sz; 315 int i, err, start; 316 317 init_fp_ctx(target); 318 319 if (sizeof(target->thread.fpu.fpr[0]) == regset->size) { 320 /* Trivially copy the vector registers */ 321 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 322 &target->thread.fpu.fpr, 323 0, wr_size); 324 } else { 325 /* Copy as much context as possible */ 326 cp_sz = min_t(unsigned int, regset->size, 327 sizeof(target->thread.fpu.fpr[0])); 328 329 i = start = err = 0; 330 for (; i < NUM_FPU_REGS; i++, start += regset->size) { 331 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 332 &target->thread.fpu.fpr[i], 333 start, start + cp_sz); 334 } 335 } 336 337 return err; 338 } 339 340 #endif /* CONFIG_CPU_HAS_LSX */ 341 342 #ifdef CONFIG_CPU_HAS_LBT 343 static int lbt_get(struct task_struct *target, 344 const struct user_regset *regset, 345 struct membuf to) 346 { 347 int r; 348 349 r = membuf_write(&to, &target->thread.lbt.scr0, sizeof(target->thread.lbt.scr0)); 350 r = membuf_write(&to, &target->thread.lbt.scr1, sizeof(target->thread.lbt.scr1)); 351 r = membuf_write(&to, &target->thread.lbt.scr2, sizeof(target->thread.lbt.scr2)); 352 r = membuf_write(&to, &target->thread.lbt.scr3, sizeof(target->thread.lbt.scr3)); 353 r = membuf_write(&to, &target->thread.lbt.eflags, sizeof(u32)); 354 r = membuf_write(&to, &target->thread.fpu.ftop, sizeof(u32)); 355 356 return r; 357 } 358 359 static int lbt_set(struct task_struct *target, 360 const struct user_regset *regset, 361 unsigned int pos, unsigned int count, 362 const void *kbuf, const void __user *ubuf) 363 { 364 int err = 0; 365 const int eflags_start = 4 * sizeof(target->thread.lbt.scr0); 366 const int ftop_start = eflags_start + sizeof(u32); 367 368 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 369 &target->thread.lbt.scr0, 370 0, 4 * sizeof(target->thread.lbt.scr0)); 371 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 372 &target->thread.lbt.eflags, 373 eflags_start, ftop_start); 374 err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf, 375 &target->thread.fpu.ftop, 376 ftop_start, ftop_start + sizeof(u32)); 377 378 return err; 379 } 380 #endif /* CONFIG_CPU_HAS_LBT */ 381 382 #ifdef CONFIG_HAVE_HW_BREAKPOINT 383 384 /* 385 * Handle hitting a HW-breakpoint. 386 */ 387 static void ptrace_hbptriggered(struct perf_event *bp, 388 struct perf_sample_data *data, 389 struct pt_regs *regs) 390 { 391 int i; 392 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); 393 394 for (i = 0; i < LOONGARCH_MAX_BRP; ++i) 395 if (current->thread.hbp_break[i] == bp) 396 break; 397 398 for (i = 0; i < LOONGARCH_MAX_WRP; ++i) 399 if (current->thread.hbp_watch[i] == bp) 400 break; 401 402 force_sig_ptrace_errno_trap(i, (void __user *)bkpt->address); 403 } 404 405 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type, 406 struct task_struct *tsk, 407 unsigned long idx) 408 { 409 struct perf_event *bp; 410 411 switch (note_type) { 412 case NT_LOONGARCH_HW_BREAK: 413 if (idx >= LOONGARCH_MAX_BRP) 414 return ERR_PTR(-EINVAL); 415 idx = array_index_nospec(idx, LOONGARCH_MAX_BRP); 416 bp = tsk->thread.hbp_break[idx]; 417 break; 418 case NT_LOONGARCH_HW_WATCH: 419 if (idx >= LOONGARCH_MAX_WRP) 420 return ERR_PTR(-EINVAL); 421 idx = array_index_nospec(idx, LOONGARCH_MAX_WRP); 422 bp = tsk->thread.hbp_watch[idx]; 423 break; 424 } 425 426 return bp; 427 } 428 429 static int ptrace_hbp_set_event(unsigned int note_type, 430 struct task_struct *tsk, 431 unsigned long idx, 432 struct perf_event *bp) 433 { 434 switch (note_type) { 435 case NT_LOONGARCH_HW_BREAK: 436 if (idx >= LOONGARCH_MAX_BRP) 437 return -EINVAL; 438 idx = array_index_nospec(idx, LOONGARCH_MAX_BRP); 439 tsk->thread.hbp_break[idx] = bp; 440 break; 441 case NT_LOONGARCH_HW_WATCH: 442 if (idx >= LOONGARCH_MAX_WRP) 443 return -EINVAL; 444 idx = array_index_nospec(idx, LOONGARCH_MAX_WRP); 445 tsk->thread.hbp_watch[idx] = bp; 446 break; 447 } 448 449 return 0; 450 } 451 452 static struct perf_event *ptrace_hbp_create(unsigned int note_type, 453 struct task_struct *tsk, 454 unsigned long idx) 455 { 456 int err, type; 457 struct perf_event *bp; 458 struct perf_event_attr attr; 459 460 switch (note_type) { 461 case NT_LOONGARCH_HW_BREAK: 462 type = HW_BREAKPOINT_X; 463 break; 464 case NT_LOONGARCH_HW_WATCH: 465 type = HW_BREAKPOINT_RW; 466 break; 467 default: 468 return ERR_PTR(-EINVAL); 469 } 470 471 ptrace_breakpoint_init(&attr); 472 473 /* 474 * Initialise fields to sane defaults 475 * (i.e. values that will pass validation). 476 */ 477 attr.bp_addr = 0; 478 attr.bp_len = HW_BREAKPOINT_LEN_4; 479 attr.bp_type = type; 480 attr.disabled = 1; 481 482 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk); 483 if (IS_ERR(bp)) 484 return bp; 485 486 err = ptrace_hbp_set_event(note_type, tsk, idx, bp); 487 if (err) 488 return ERR_PTR(err); 489 490 return bp; 491 } 492 493 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type, 494 struct arch_hw_breakpoint_ctrl ctrl, 495 struct perf_event_attr *attr) 496 { 497 int err, len, type; 498 499 err = arch_bp_generic_fields(ctrl, &len, &type); 500 if (err) 501 return err; 502 503 attr->bp_len = len; 504 attr->bp_type = type; 505 506 return 0; 507 } 508 509 static int ptrace_hbp_get_resource_info(unsigned int note_type, u64 *info) 510 { 511 u8 num; 512 u64 reg = 0; 513 514 switch (note_type) { 515 case NT_LOONGARCH_HW_BREAK: 516 num = hw_breakpoint_slots(TYPE_INST); 517 break; 518 case NT_LOONGARCH_HW_WATCH: 519 num = hw_breakpoint_slots(TYPE_DATA); 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 *info = reg | num; 526 527 return 0; 528 } 529 530 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type, 531 struct task_struct *tsk, 532 unsigned long idx) 533 { 534 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 535 536 if (!bp) 537 bp = ptrace_hbp_create(note_type, tsk, idx); 538 539 return bp; 540 } 541 542 static int ptrace_hbp_get_ctrl(unsigned int note_type, 543 struct task_struct *tsk, 544 unsigned long idx, u32 *ctrl) 545 { 546 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 547 548 if (IS_ERR(bp)) 549 return PTR_ERR(bp); 550 551 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0; 552 553 return 0; 554 } 555 556 static int ptrace_hbp_get_mask(unsigned int note_type, 557 struct task_struct *tsk, 558 unsigned long idx, u64 *mask) 559 { 560 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 561 562 if (IS_ERR(bp)) 563 return PTR_ERR(bp); 564 565 *mask = bp ? counter_arch_bp(bp)->mask : 0; 566 567 return 0; 568 } 569 570 static int ptrace_hbp_get_addr(unsigned int note_type, 571 struct task_struct *tsk, 572 unsigned long idx, u64 *addr) 573 { 574 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx); 575 576 if (IS_ERR(bp)) 577 return PTR_ERR(bp); 578 579 *addr = bp ? counter_arch_bp(bp)->address : 0; 580 581 return 0; 582 } 583 584 static int ptrace_hbp_set_ctrl(unsigned int note_type, 585 struct task_struct *tsk, 586 unsigned long idx, u32 uctrl) 587 { 588 int err; 589 struct perf_event *bp; 590 struct perf_event_attr attr; 591 struct arch_hw_breakpoint_ctrl ctrl; 592 593 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 594 if (IS_ERR(bp)) 595 return PTR_ERR(bp); 596 597 attr = bp->attr; 598 599 switch (note_type) { 600 case NT_LOONGARCH_HW_BREAK: 601 ctrl.type = LOONGARCH_BREAKPOINT_EXECUTE; 602 ctrl.len = LOONGARCH_BREAKPOINT_LEN_4; 603 break; 604 case NT_LOONGARCH_HW_WATCH: 605 decode_ctrl_reg(uctrl, &ctrl); 606 break; 607 default: 608 return -EINVAL; 609 } 610 611 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr); 612 if (err) 613 return err; 614 615 return modify_user_hw_breakpoint(bp, &attr); 616 } 617 618 static int ptrace_hbp_set_mask(unsigned int note_type, 619 struct task_struct *tsk, 620 unsigned long idx, u64 mask) 621 { 622 struct perf_event *bp; 623 struct perf_event_attr attr; 624 struct arch_hw_breakpoint *info; 625 626 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 627 if (IS_ERR(bp)) 628 return PTR_ERR(bp); 629 630 attr = bp->attr; 631 info = counter_arch_bp(bp); 632 info->mask = mask; 633 634 return modify_user_hw_breakpoint(bp, &attr); 635 } 636 637 static int ptrace_hbp_set_addr(unsigned int note_type, 638 struct task_struct *tsk, 639 unsigned long idx, u64 addr) 640 { 641 struct perf_event *bp; 642 struct perf_event_attr attr; 643 644 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 645 if (IS_ERR(bp)) 646 return PTR_ERR(bp); 647 648 attr = bp->attr; 649 attr.bp_addr = addr; 650 651 return modify_user_hw_breakpoint(bp, &attr); 652 } 653 654 #define PTRACE_HBP_ADDR_SZ sizeof(u64) 655 #define PTRACE_HBP_MASK_SZ sizeof(u64) 656 #define PTRACE_HBP_CTRL_SZ sizeof(u32) 657 #define PTRACE_HBP_PAD_SZ sizeof(u32) 658 659 static int hw_break_get(struct task_struct *target, 660 const struct user_regset *regset, 661 struct membuf to) 662 { 663 u64 info; 664 u32 ctrl; 665 u64 addr, mask; 666 int ret, idx = 0; 667 unsigned int note_type = regset->core_note_type; 668 669 /* Resource info */ 670 ret = ptrace_hbp_get_resource_info(note_type, &info); 671 if (ret) 672 return ret; 673 674 membuf_write(&to, &info, sizeof(info)); 675 676 /* (address, mask, ctrl) registers */ 677 while (to.left) { 678 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr); 679 if (ret) 680 return ret; 681 682 ret = ptrace_hbp_get_mask(note_type, target, idx, &mask); 683 if (ret) 684 return ret; 685 686 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl); 687 if (ret) 688 return ret; 689 690 membuf_store(&to, addr); 691 membuf_store(&to, mask); 692 membuf_store(&to, ctrl); 693 membuf_zero(&to, sizeof(u32)); 694 idx++; 695 } 696 697 return 0; 698 } 699 700 static int hw_break_set(struct task_struct *target, 701 const struct user_regset *regset, 702 unsigned int pos, unsigned int count, 703 const void *kbuf, const void __user *ubuf) 704 { 705 u32 ctrl; 706 u64 addr, mask; 707 int ret, idx = 0, offset, limit; 708 unsigned int note_type = regset->core_note_type; 709 710 /* Resource info */ 711 offset = offsetof(struct user_watch_state, dbg_regs); 712 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset); 713 714 /* (address, mask, ctrl) registers */ 715 limit = regset->n * regset->size; 716 while (count && offset < limit) { 717 if (count < PTRACE_HBP_ADDR_SZ) 718 return -EINVAL; 719 720 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr, 721 offset, offset + PTRACE_HBP_ADDR_SZ); 722 if (ret) 723 return ret; 724 725 ret = ptrace_hbp_set_addr(note_type, target, idx, addr); 726 if (ret) 727 return ret; 728 offset += PTRACE_HBP_ADDR_SZ; 729 730 if (!count) 731 break; 732 733 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &mask, 734 offset, offset + PTRACE_HBP_MASK_SZ); 735 if (ret) 736 return ret; 737 738 ret = ptrace_hbp_set_mask(note_type, target, idx, mask); 739 if (ret) 740 return ret; 741 offset += PTRACE_HBP_MASK_SZ; 742 743 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 744 offset, offset + PTRACE_HBP_CTRL_SZ); 745 if (ret) 746 return ret; 747 748 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl); 749 if (ret) 750 return ret; 751 offset += PTRACE_HBP_CTRL_SZ; 752 753 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 754 offset, offset + PTRACE_HBP_PAD_SZ); 755 offset += PTRACE_HBP_PAD_SZ; 756 757 idx++; 758 } 759 760 return 0; 761 } 762 763 #endif 764 765 struct pt_regs_offset { 766 const char *name; 767 int offset; 768 }; 769 770 #define REG_OFFSET_NAME(n, r) {.name = #n, .offset = offsetof(struct pt_regs, r)} 771 #define REG_OFFSET_END {.name = NULL, .offset = 0} 772 773 static const struct pt_regs_offset regoffset_table[] = { 774 REG_OFFSET_NAME(r0, regs[0]), 775 REG_OFFSET_NAME(r1, regs[1]), 776 REG_OFFSET_NAME(r2, regs[2]), 777 REG_OFFSET_NAME(r3, regs[3]), 778 REG_OFFSET_NAME(r4, regs[4]), 779 REG_OFFSET_NAME(r5, regs[5]), 780 REG_OFFSET_NAME(r6, regs[6]), 781 REG_OFFSET_NAME(r7, regs[7]), 782 REG_OFFSET_NAME(r8, regs[8]), 783 REG_OFFSET_NAME(r9, regs[9]), 784 REG_OFFSET_NAME(r10, regs[10]), 785 REG_OFFSET_NAME(r11, regs[11]), 786 REG_OFFSET_NAME(r12, regs[12]), 787 REG_OFFSET_NAME(r13, regs[13]), 788 REG_OFFSET_NAME(r14, regs[14]), 789 REG_OFFSET_NAME(r15, regs[15]), 790 REG_OFFSET_NAME(r16, regs[16]), 791 REG_OFFSET_NAME(r17, regs[17]), 792 REG_OFFSET_NAME(r18, regs[18]), 793 REG_OFFSET_NAME(r19, regs[19]), 794 REG_OFFSET_NAME(r20, regs[20]), 795 REG_OFFSET_NAME(r21, regs[21]), 796 REG_OFFSET_NAME(r22, regs[22]), 797 REG_OFFSET_NAME(r23, regs[23]), 798 REG_OFFSET_NAME(r24, regs[24]), 799 REG_OFFSET_NAME(r25, regs[25]), 800 REG_OFFSET_NAME(r26, regs[26]), 801 REG_OFFSET_NAME(r27, regs[27]), 802 REG_OFFSET_NAME(r28, regs[28]), 803 REG_OFFSET_NAME(r29, regs[29]), 804 REG_OFFSET_NAME(r30, regs[30]), 805 REG_OFFSET_NAME(r31, regs[31]), 806 REG_OFFSET_NAME(orig_a0, orig_a0), 807 REG_OFFSET_NAME(csr_era, csr_era), 808 REG_OFFSET_NAME(csr_badvaddr, csr_badvaddr), 809 REG_OFFSET_NAME(csr_crmd, csr_crmd), 810 REG_OFFSET_NAME(csr_prmd, csr_prmd), 811 REG_OFFSET_NAME(csr_euen, csr_euen), 812 REG_OFFSET_NAME(csr_ecfg, csr_ecfg), 813 REG_OFFSET_NAME(csr_estat, csr_estat), 814 REG_OFFSET_END, 815 }; 816 817 /** 818 * regs_query_register_offset() - query register offset from its name 819 * @name: the name of a register 820 * 821 * regs_query_register_offset() returns the offset of a register in struct 822 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 823 */ 824 int regs_query_register_offset(const char *name) 825 { 826 const struct pt_regs_offset *roff; 827 828 for (roff = regoffset_table; roff->name != NULL; roff++) 829 if (!strcmp(roff->name, name)) 830 return roff->offset; 831 return -EINVAL; 832 } 833 834 enum loongarch_regset { 835 REGSET_GPR, 836 REGSET_FPR, 837 REGSET_CPUCFG, 838 #ifdef CONFIG_CPU_HAS_LSX 839 REGSET_LSX, 840 #endif 841 #ifdef CONFIG_CPU_HAS_LASX 842 REGSET_LASX, 843 #endif 844 #ifdef CONFIG_CPU_HAS_LBT 845 REGSET_LBT, 846 #endif 847 #ifdef CONFIG_HAVE_HW_BREAKPOINT 848 REGSET_HW_BREAK, 849 REGSET_HW_WATCH, 850 #endif 851 }; 852 853 static const struct user_regset loongarch64_regsets[] = { 854 [REGSET_GPR] = { 855 .core_note_type = NT_PRSTATUS, 856 .n = ELF_NGREG, 857 .size = sizeof(elf_greg_t), 858 .align = sizeof(elf_greg_t), 859 .regset_get = gpr_get, 860 .set = gpr_set, 861 }, 862 [REGSET_FPR] = { 863 .core_note_type = NT_PRFPREG, 864 .n = ELF_NFPREG, 865 .size = sizeof(elf_fpreg_t), 866 .align = sizeof(elf_fpreg_t), 867 .regset_get = fpr_get, 868 .set = fpr_set, 869 }, 870 [REGSET_CPUCFG] = { 871 .core_note_type = NT_LOONGARCH_CPUCFG, 872 .n = 64, 873 .size = sizeof(u32), 874 .align = sizeof(u32), 875 .regset_get = cfg_get, 876 .set = cfg_set, 877 }, 878 #ifdef CONFIG_CPU_HAS_LSX 879 [REGSET_LSX] = { 880 .core_note_type = NT_LOONGARCH_LSX, 881 .n = NUM_FPU_REGS, 882 .size = 16, 883 .align = 16, 884 .regset_get = simd_get, 885 .set = simd_set, 886 }, 887 #endif 888 #ifdef CONFIG_CPU_HAS_LASX 889 [REGSET_LASX] = { 890 .core_note_type = NT_LOONGARCH_LASX, 891 .n = NUM_FPU_REGS, 892 .size = 32, 893 .align = 32, 894 .regset_get = simd_get, 895 .set = simd_set, 896 }, 897 #endif 898 #ifdef CONFIG_CPU_HAS_LBT 899 [REGSET_LBT] = { 900 .core_note_type = NT_LOONGARCH_LBT, 901 .n = 5, 902 .size = sizeof(u64), 903 .align = sizeof(u64), 904 .regset_get = lbt_get, 905 .set = lbt_set, 906 }, 907 #endif 908 #ifdef CONFIG_HAVE_HW_BREAKPOINT 909 [REGSET_HW_BREAK] = { 910 .core_note_type = NT_LOONGARCH_HW_BREAK, 911 .n = sizeof(struct user_watch_state) / sizeof(u32), 912 .size = sizeof(u32), 913 .align = sizeof(u32), 914 .regset_get = hw_break_get, 915 .set = hw_break_set, 916 }, 917 [REGSET_HW_WATCH] = { 918 .core_note_type = NT_LOONGARCH_HW_WATCH, 919 .n = sizeof(struct user_watch_state) / sizeof(u32), 920 .size = sizeof(u32), 921 .align = sizeof(u32), 922 .regset_get = hw_break_get, 923 .set = hw_break_set, 924 }, 925 #endif 926 }; 927 928 static const struct user_regset_view user_loongarch64_view = { 929 .name = "loongarch64", 930 .e_machine = ELF_ARCH, 931 .regsets = loongarch64_regsets, 932 .n = ARRAY_SIZE(loongarch64_regsets), 933 }; 934 935 936 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 937 { 938 return &user_loongarch64_view; 939 } 940 941 static inline int read_user(struct task_struct *target, unsigned long addr, 942 unsigned long __user *data) 943 { 944 unsigned long tmp = 0; 945 946 switch (addr) { 947 case 0 ... 31: 948 tmp = task_pt_regs(target)->regs[addr]; 949 break; 950 case ARG0: 951 tmp = task_pt_regs(target)->orig_a0; 952 break; 953 case PC: 954 tmp = task_pt_regs(target)->csr_era; 955 break; 956 case BADVADDR: 957 tmp = task_pt_regs(target)->csr_badvaddr; 958 break; 959 default: 960 return -EIO; 961 } 962 963 return put_user(tmp, data); 964 } 965 966 static inline int write_user(struct task_struct *target, unsigned long addr, 967 unsigned long data) 968 { 969 switch (addr) { 970 case 0 ... 31: 971 task_pt_regs(target)->regs[addr] = data; 972 break; 973 case ARG0: 974 task_pt_regs(target)->orig_a0 = data; 975 break; 976 case PC: 977 task_pt_regs(target)->csr_era = data; 978 break; 979 case BADVADDR: 980 task_pt_regs(target)->csr_badvaddr = data; 981 break; 982 default: 983 return -EIO; 984 } 985 986 return 0; 987 } 988 989 long arch_ptrace(struct task_struct *child, long request, 990 unsigned long addr, unsigned long data) 991 { 992 int ret; 993 unsigned long __user *datap = (void __user *) data; 994 995 switch (request) { 996 case PTRACE_PEEKUSR: 997 ret = read_user(child, addr, datap); 998 break; 999 1000 case PTRACE_POKEUSR: 1001 ret = write_user(child, addr, data); 1002 break; 1003 1004 default: 1005 ret = ptrace_request(child, request, addr, data); 1006 break; 1007 } 1008 1009 return ret; 1010 } 1011 1012 #ifdef CONFIG_HAVE_HW_BREAKPOINT 1013 static void ptrace_triggered(struct perf_event *bp, 1014 struct perf_sample_data *data, struct pt_regs *regs) 1015 { 1016 struct perf_event_attr attr; 1017 1018 attr = bp->attr; 1019 attr.disabled = true; 1020 modify_user_hw_breakpoint(bp, &attr); 1021 } 1022 1023 static int set_single_step(struct task_struct *tsk, unsigned long addr) 1024 { 1025 struct perf_event *bp; 1026 struct perf_event_attr attr; 1027 struct arch_hw_breakpoint *info; 1028 struct thread_struct *thread = &tsk->thread; 1029 1030 bp = thread->hbp_break[0]; 1031 if (!bp) { 1032 ptrace_breakpoint_init(&attr); 1033 1034 attr.bp_addr = addr; 1035 attr.bp_len = HW_BREAKPOINT_LEN_8; 1036 attr.bp_type = HW_BREAKPOINT_X; 1037 1038 bp = register_user_hw_breakpoint(&attr, ptrace_triggered, 1039 NULL, tsk); 1040 if (IS_ERR(bp)) 1041 return PTR_ERR(bp); 1042 1043 thread->hbp_break[0] = bp; 1044 } else { 1045 int err; 1046 1047 attr = bp->attr; 1048 attr.bp_addr = addr; 1049 1050 /* Reenable breakpoint */ 1051 attr.disabled = false; 1052 err = modify_user_hw_breakpoint(bp, &attr); 1053 if (unlikely(err)) 1054 return err; 1055 1056 csr_write64(attr.bp_addr, LOONGARCH_CSR_IB0ADDR); 1057 } 1058 info = counter_arch_bp(bp); 1059 info->mask = TASK_SIZE - 1; 1060 1061 return 0; 1062 } 1063 1064 /* ptrace API */ 1065 void user_enable_single_step(struct task_struct *task) 1066 { 1067 struct thread_info *ti = task_thread_info(task); 1068 1069 set_single_step(task, task_pt_regs(task)->csr_era); 1070 task->thread.single_step = task_pt_regs(task)->csr_era; 1071 set_ti_thread_flag(ti, TIF_SINGLESTEP); 1072 } 1073 1074 void user_disable_single_step(struct task_struct *task) 1075 { 1076 clear_tsk_thread_flag(task, TIF_SINGLESTEP); 1077 } 1078 #endif 1079