1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5#include <linux/init.h> 6#include <linux/threads.h> 7 8#include <asm/addrspace.h> 9#include <asm/asm.h> 10#include <asm/asmmacro.h> 11#include <asm/bug.h> 12#include <asm/regdef.h> 13#include <asm/loongarch.h> 14#include <asm/stackframe.h> 15 16#ifdef CONFIG_EFI_STUB 17 18#include "efi-header.S" 19 20 __HEAD 21 22_head: 23 .word MZ_MAGIC /* "MZ", MS-DOS header */ 24 .org 0x8 25 .dword kernel_entry /* Kernel entry point */ 26 .dword _end - _text /* Kernel image effective size */ 27 .quad 0 /* Kernel image load offset from start of RAM */ 28 .org 0x38 /* 0x20 ~ 0x37 reserved */ 29 .long LINUX_PE_MAGIC 30 .long pe_header - _head /* Offset to the PE header */ 31 32pe_header: 33 __EFI_PE_HEADER 34 35SYM_DATA(kernel_asize, .long _end - _text); 36SYM_DATA(kernel_fsize, .long _edata - _text); 37SYM_DATA(kernel_offset, .long kernel_offset - _text); 38 39#endif 40 41 __REF 42 43 .align 12 44 45SYM_CODE_START(kernel_entry) # kernel entry point 46 47 /* Config direct window and set PG */ 48 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx 49 csrwr t0, LOONGARCH_CSR_DMWIN0 50 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx 51 csrwr t0, LOONGARCH_CSR_DMWIN1 52 53 /* We might not get launched at the address the kernel is linked to, 54 so we jump there. */ 55 la.abs t0, 0f 56 jr t0 570: 58 /* Enable PG */ 59 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 60 csrwr t0, LOONGARCH_CSR_CRMD 61 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 62 csrwr t0, LOONGARCH_CSR_PRMD 63 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 64 csrwr t0, LOONGARCH_CSR_EUEN 65 66 la.pcrel t0, __bss_start # clear .bss 67 st.d zero, t0, 0 68 la.pcrel t1, __bss_stop - LONGSIZE 691: 70 addi.d t0, t0, LONGSIZE 71 st.d zero, t0, 0 72 bne t0, t1, 1b 73 74 la.pcrel t0, fw_arg0 75 st.d a0, t0, 0 # firmware arguments 76 la.pcrel t0, fw_arg1 77 st.d a1, t0, 0 78 la.pcrel t0, fw_arg2 79 st.d a2, t0, 0 80 81 /* KSave3 used for percpu base, initialized as 0 */ 82 csrwr zero, PERCPU_BASE_KS 83 /* GPR21 used for percpu base (runtime), initialized as 0 */ 84 move u0, zero 85 86 la.pcrel tp, init_thread_union 87 /* Set the SP after an empty pt_regs. */ 88 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 89 PTR_ADD sp, sp, tp 90 set_saved_sp sp, t0, t1 91 92 bl start_kernel 93 ASM_BUG() 94 95SYM_CODE_END(kernel_entry) 96 97#ifdef CONFIG_SMP 98 99/* 100 * SMP slave cpus entry point. Board specific code for bootstrap calls this 101 * function after setting up the stack and tp registers. 102 */ 103SYM_CODE_START(smpboot_entry) 104 li.d t0, CSR_DMW0_INIT # UC, PLV0 105 csrwr t0, LOONGARCH_CSR_DMWIN0 106 li.d t0, CSR_DMW1_INIT # CA, PLV0 107 csrwr t0, LOONGARCH_CSR_DMWIN1 108 109 la.abs t0, 0f 110 jr t0 1110: 112 /* Enable PG */ 113 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 114 csrwr t0, LOONGARCH_CSR_CRMD 115 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 116 csrwr t0, LOONGARCH_CSR_PRMD 117 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 118 csrwr t0, LOONGARCH_CSR_EUEN 119 120 la.pcrel t0, cpuboot_data 121 ld.d sp, t0, CPU_BOOT_STACK 122 ld.d tp, t0, CPU_BOOT_TINFO 123 124 bl start_secondary 125 ASM_BUG() 126 127SYM_CODE_END(smpboot_entry) 128 129#endif /* CONFIG_SMP */ 130 131SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) 132