1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5#include <linux/init.h> 6#include <linux/threads.h> 7 8#include <asm/addrspace.h> 9#include <asm/asm.h> 10#include <asm/asmmacro.h> 11#include <asm/regdef.h> 12#include <asm/loongarch.h> 13#include <asm/stackframe.h> 14 15 __REF 16 17SYM_CODE_START(kernel_entry) # kernel entry point 18 19 /* Config direct window and set PG */ 20 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx 21 csrwr t0, LOONGARCH_CSR_DMWIN0 22 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx 23 csrwr t0, LOONGARCH_CSR_DMWIN1 24 /* Enable PG */ 25 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 26 csrwr t0, LOONGARCH_CSR_CRMD 27 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 28 csrwr t0, LOONGARCH_CSR_PRMD 29 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 30 csrwr t0, LOONGARCH_CSR_EUEN 31 32 /* We might not get launched at the address the kernel is linked to, 33 so we jump there. */ 34 la.abs t0, 0f 35 jirl zero, t0, 0 360: 37 la t0, __bss_start # clear .bss 38 st.d zero, t0, 0 39 la t1, __bss_stop - LONGSIZE 401: 41 addi.d t0, t0, LONGSIZE 42 st.d zero, t0, 0 43 bne t0, t1, 1b 44 45 la t0, fw_arg0 46 st.d a0, t0, 0 # firmware arguments 47 la t0, fw_arg1 48 st.d a1, t0, 0 49 50 /* KSave3 used for percpu base, initialized as 0 */ 51 csrwr zero, PERCPU_BASE_KS 52 /* GPR21 used for percpu base (runtime), initialized as 0 */ 53 or u0, zero, zero 54 55 la tp, init_thread_union 56 /* Set the SP after an empty pt_regs. */ 57 PTR_LI sp, (_THREAD_SIZE - 32 - PT_SIZE) 58 PTR_ADD sp, sp, tp 59 set_saved_sp sp, t0, t1 60 PTR_ADDI sp, sp, -4 * SZREG # init stack pointer 61 62 bl start_kernel 63 64SYM_CODE_END(kernel_entry) 65 66#ifdef CONFIG_SMP 67 68/* 69 * SMP slave cpus entry point. Board specific code for bootstrap calls this 70 * function after setting up the stack and tp registers. 71 */ 72SYM_CODE_START(smpboot_entry) 73 li.d t0, CSR_DMW0_INIT # UC, PLV0 74 csrwr t0, LOONGARCH_CSR_DMWIN0 75 li.d t0, CSR_DMW1_INIT # CA, PLV0 76 csrwr t0, LOONGARCH_CSR_DMWIN1 77 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 78 csrwr t0, LOONGARCH_CSR_CRMD 79 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 80 csrwr t0, LOONGARCH_CSR_PRMD 81 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 82 csrwr t0, LOONGARCH_CSR_EUEN 83 84 la.abs t0, cpuboot_data 85 ld.d sp, t0, CPU_BOOT_STACK 86 ld.d tp, t0, CPU_BOOT_TINFO 87 88 la.abs t0, 0f 89 jirl zero, t0, 0 900: 91 bl start_secondary 92SYM_CODE_END(smpboot_entry) 93 94#endif /* CONFIG_SMP */ 95 96SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) 97