1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5#include <linux/init.h> 6#include <linux/threads.h> 7 8#include <asm/addrspace.h> 9#include <asm/asm.h> 10#include <asm/asmmacro.h> 11#include <asm/bug.h> 12#include <asm/regdef.h> 13#include <asm/loongarch.h> 14#include <asm/stackframe.h> 15 16#ifdef CONFIG_EFI_STUB 17 18#include "efi-header.S" 19 20 __HEAD 21 22_head: 23 .word MZ_MAGIC /* "MZ", MS-DOS header */ 24 .org 0x8 25 .dword _kernel_entry /* Kernel entry point (physical address) */ 26 .dword _kernel_asize /* Kernel image effective size */ 27 .quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */ 28 .org 0x38 /* 0x20 ~ 0x37 reserved */ 29 .long LINUX_PE_MAGIC 30 .long pe_header - _head /* Offset to the PE header */ 31 32pe_header: 33 __EFI_PE_HEADER 34 35SYM_DATA(kernel_asize, .long _kernel_asize); 36SYM_DATA(kernel_fsize, .long _kernel_fsize); 37 38#endif 39 40 __REF 41 42 .align 12 43 44SYM_CODE_START(kernel_entry) # kernel entry point 45 46 /* Config direct window and set PG */ 47 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx 48 csrwr t0, LOONGARCH_CSR_DMWIN0 49 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx 50 csrwr t0, LOONGARCH_CSR_DMWIN1 51 52 JUMP_VIRT_ADDR t0, t1 53 54 /* Enable PG */ 55 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 56 csrwr t0, LOONGARCH_CSR_CRMD 57 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 58 csrwr t0, LOONGARCH_CSR_PRMD 59 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 60 csrwr t0, LOONGARCH_CSR_EUEN 61 62 la.pcrel t0, __bss_start # clear .bss 63 st.d zero, t0, 0 64 la.pcrel t1, __bss_stop - LONGSIZE 651: 66 addi.d t0, t0, LONGSIZE 67 st.d zero, t0, 0 68 bne t0, t1, 1b 69 70 la.pcrel t0, fw_arg0 71 st.d a0, t0, 0 # firmware arguments 72 la.pcrel t0, fw_arg1 73 st.d a1, t0, 0 74 la.pcrel t0, fw_arg2 75 st.d a2, t0, 0 76 77 /* KSave3 used for percpu base, initialized as 0 */ 78 csrwr zero, PERCPU_BASE_KS 79 /* GPR21 used for percpu base (runtime), initialized as 0 */ 80 move u0, zero 81 82 la.pcrel tp, init_thread_union 83 /* Set the SP after an empty pt_regs. */ 84 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 85 PTR_ADD sp, sp, tp 86 set_saved_sp sp, t0, t1 87 88#ifdef CONFIG_RELOCATABLE 89 90 bl relocate_kernel 91 92#ifdef CONFIG_RANDOMIZE_BASE 93 /* Repoint the sp into the new kernel */ 94 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 95 PTR_ADD sp, sp, tp 96 set_saved_sp sp, t0, t1 97 98 /* Jump to the new kernel: new_pc = current_pc + random_offset */ 99 pcaddi t0, 0 100 add.d t0, t0, a0 101 jirl zero, t0, 0xc 102#endif /* CONFIG_RANDOMIZE_BASE */ 103 104#endif /* CONFIG_RELOCATABLE */ 105 106#ifdef CONFIG_KASAN 107 bl kasan_early_init 108#endif 109 110 bl start_kernel 111 ASM_BUG() 112 113SYM_CODE_END(kernel_entry) 114 115#ifdef CONFIG_SMP 116 117/* 118 * SMP slave cpus entry point. Board specific code for bootstrap calls this 119 * function after setting up the stack and tp registers. 120 */ 121SYM_CODE_START(smpboot_entry) 122 li.d t0, CSR_DMW0_INIT # UC, PLV0 123 csrwr t0, LOONGARCH_CSR_DMWIN0 124 li.d t0, CSR_DMW1_INIT # CA, PLV0 125 csrwr t0, LOONGARCH_CSR_DMWIN1 126 127 JUMP_VIRT_ADDR t0, t1 128 129 /* Enable PG */ 130 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 131 csrwr t0, LOONGARCH_CSR_CRMD 132 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 133 csrwr t0, LOONGARCH_CSR_PRMD 134 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 135 csrwr t0, LOONGARCH_CSR_EUEN 136 137 la.pcrel t0, cpuboot_data 138 ld.d sp, t0, CPU_BOOT_STACK 139 ld.d tp, t0, CPU_BOOT_TINFO 140 141 bl start_secondary 142 ASM_BUG() 143 144SYM_CODE_END(smpboot_entry) 145 146#endif /* CONFIG_SMP */ 147 148SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) 149