1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5#include <linux/init.h> 6#include <linux/threads.h> 7 8#include <asm/addrspace.h> 9#include <asm/asm.h> 10#include <asm/asmmacro.h> 11#include <asm/regdef.h> 12#include <asm/loongarch.h> 13#include <asm/stackframe.h> 14 15 __REF 16 17SYM_CODE_START(kernel_entry) # kernel entry point 18 19 /* Config direct window and set PG */ 20 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx 21 csrwr t0, LOONGARCH_CSR_DMWIN0 22 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx 23 csrwr t0, LOONGARCH_CSR_DMWIN1 24 25 /* We might not get launched at the address the kernel is linked to, 26 so we jump there. */ 27 la.abs t0, 0f 28 jr t0 290: 30 /* Enable PG */ 31 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 32 csrwr t0, LOONGARCH_CSR_CRMD 33 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 34 csrwr t0, LOONGARCH_CSR_PRMD 35 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 36 csrwr t0, LOONGARCH_CSR_EUEN 37 38 la t0, __bss_start # clear .bss 39 st.d zero, t0, 0 40 la t1, __bss_stop - LONGSIZE 411: 42 addi.d t0, t0, LONGSIZE 43 st.d zero, t0, 0 44 bne t0, t1, 1b 45 46 la t0, fw_arg0 47 st.d a0, t0, 0 # firmware arguments 48 la t0, fw_arg1 49 st.d a1, t0, 0 50 51 /* KSave3 used for percpu base, initialized as 0 */ 52 csrwr zero, PERCPU_BASE_KS 53 /* GPR21 used for percpu base (runtime), initialized as 0 */ 54 move u0, zero 55 56 la tp, init_thread_union 57 /* Set the SP after an empty pt_regs. */ 58 PTR_LI sp, (_THREAD_SIZE - 32 - PT_SIZE) 59 PTR_ADD sp, sp, tp 60 set_saved_sp sp, t0, t1 61 PTR_ADDI sp, sp, -4 * SZREG # init stack pointer 62 63 bl start_kernel 64 65SYM_CODE_END(kernel_entry) 66 67#ifdef CONFIG_SMP 68 69/* 70 * SMP slave cpus entry point. Board specific code for bootstrap calls this 71 * function after setting up the stack and tp registers. 72 */ 73SYM_CODE_START(smpboot_entry) 74 li.d t0, CSR_DMW0_INIT # UC, PLV0 75 csrwr t0, LOONGARCH_CSR_DMWIN0 76 li.d t0, CSR_DMW1_INIT # CA, PLV0 77 csrwr t0, LOONGARCH_CSR_DMWIN1 78 79 la.abs t0, 0f 80 jr t0 810: 82 /* Enable PG */ 83 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 84 csrwr t0, LOONGARCH_CSR_CRMD 85 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 86 csrwr t0, LOONGARCH_CSR_PRMD 87 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 88 csrwr t0, LOONGARCH_CSR_EUEN 89 90 la.abs t0, cpuboot_data 91 ld.d sp, t0, CPU_BOOT_STACK 92 ld.d tp, t0, CPU_BOOT_TINFO 93 94 bl start_secondary 95SYM_CODE_END(smpboot_entry) 96 97#endif /* CONFIG_SMP */ 98 99SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) 100