1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Processor capabilities determination functions. 4 * 5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 6 */ 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <linux/ptrace.h> 10 #include <linux/smp.h> 11 #include <linux/stddef.h> 12 #include <linux/export.h> 13 #include <linux/printk.h> 14 #include <linux/uaccess.h> 15 16 #include <asm/cpu-features.h> 17 #include <asm/elf.h> 18 #include <asm/fpu.h> 19 #include <asm/loongarch.h> 20 #include <asm/pgtable-bits.h> 21 #include <asm/setup.h> 22 23 /* Hardware capabilities */ 24 unsigned int elf_hwcap __read_mostly; 25 EXPORT_SYMBOL_GPL(elf_hwcap); 26 27 /* 28 * Determine the FCSR mask for FPU hardware. 29 */ 30 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c) 31 { 32 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 33 34 fcsr = c->fpu_csr0; 35 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 36 37 sr = read_csr_euen(); 38 enable_fpu(); 39 40 fcsr0 = fcsr & mask; 41 write_fcsr(LOONGARCH_FCSR0, fcsr0); 42 fcsr0 = read_fcsr(LOONGARCH_FCSR0); 43 44 fcsr1 = fcsr | ~mask; 45 write_fcsr(LOONGARCH_FCSR0, fcsr1); 46 fcsr1 = read_fcsr(LOONGARCH_FCSR0); 47 48 write_fcsr(LOONGARCH_FCSR0, fcsr); 49 50 write_csr_euen(sr); 51 52 c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask; 53 } 54 55 static inline void set_elf_platform(int cpu, const char *plat) 56 { 57 if (cpu == 0) 58 __elf_platform = plat; 59 } 60 61 /* MAP BASE */ 62 unsigned long vm_map_base; 63 EXPORT_SYMBOL(vm_map_base); 64 65 static void cpu_probe_addrbits(struct cpuinfo_loongarch *c) 66 { 67 #ifdef __NEED_ADDRBITS_PROBE 68 c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4; 69 c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12; 70 vm_map_base = 0UL - (1UL << c->vabits); 71 #endif 72 } 73 74 static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa) 75 { 76 switch (isa) { 77 case LOONGARCH_CPU_ISA_LA64: 78 c->isa_level |= LOONGARCH_CPU_ISA_LA64; 79 fallthrough; 80 case LOONGARCH_CPU_ISA_LA32S: 81 c->isa_level |= LOONGARCH_CPU_ISA_LA32S; 82 fallthrough; 83 case LOONGARCH_CPU_ISA_LA32R: 84 c->isa_level |= LOONGARCH_CPU_ISA_LA32R; 85 break; 86 } 87 } 88 89 static void cpu_probe_common(struct cpuinfo_loongarch *c) 90 { 91 unsigned int config; 92 unsigned long asid_mask; 93 94 c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | 95 LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; 96 97 elf_hwcap = HWCAP_LOONGARCH_CPUCFG; 98 99 config = read_cpucfg(LOONGARCH_CPUCFG1); 100 if (config & CPUCFG1_UAL) { 101 c->options |= LOONGARCH_CPU_UAL; 102 elf_hwcap |= HWCAP_LOONGARCH_UAL; 103 } 104 if (config & CPUCFG1_CRC32) { 105 c->options |= LOONGARCH_CPU_CRC32; 106 elf_hwcap |= HWCAP_LOONGARCH_CRC32; 107 } 108 109 110 config = read_cpucfg(LOONGARCH_CPUCFG2); 111 if (config & CPUCFG2_LAM) { 112 c->options |= LOONGARCH_CPU_LAM; 113 elf_hwcap |= HWCAP_LOONGARCH_LAM; 114 } 115 if (config & CPUCFG2_FP) { 116 c->options |= LOONGARCH_CPU_FPU; 117 elf_hwcap |= HWCAP_LOONGARCH_FPU; 118 } 119 #ifdef CONFIG_CPU_HAS_LSX 120 if (config & CPUCFG2_LSX) { 121 c->options |= LOONGARCH_CPU_LSX; 122 elf_hwcap |= HWCAP_LOONGARCH_LSX; 123 } 124 #endif 125 #ifdef CONFIG_CPU_HAS_LASX 126 if (config & CPUCFG2_LASX) { 127 c->options |= LOONGARCH_CPU_LASX; 128 elf_hwcap |= HWCAP_LOONGARCH_LASX; 129 } 130 #endif 131 if (config & CPUCFG2_COMPLEX) { 132 c->options |= LOONGARCH_CPU_COMPLEX; 133 elf_hwcap |= HWCAP_LOONGARCH_COMPLEX; 134 } 135 if (config & CPUCFG2_CRYPTO) { 136 c->options |= LOONGARCH_CPU_CRYPTO; 137 elf_hwcap |= HWCAP_LOONGARCH_CRYPTO; 138 } 139 if (config & CPUCFG2_PTW) { 140 c->options |= LOONGARCH_CPU_PTW; 141 elf_hwcap |= HWCAP_LOONGARCH_PTW; 142 } 143 if (config & CPUCFG2_LVZP) { 144 c->options |= LOONGARCH_CPU_LVZ; 145 elf_hwcap |= HWCAP_LOONGARCH_LVZ; 146 } 147 148 config = read_cpucfg(LOONGARCH_CPUCFG6); 149 if (config & CPUCFG6_PMP) 150 c->options |= LOONGARCH_CPU_PMP; 151 152 config = iocsr_read32(LOONGARCH_IOCSR_FEATURES); 153 if (config & IOCSRF_CSRIPI) 154 c->options |= LOONGARCH_CPU_CSRIPI; 155 if (config & IOCSRF_EXTIOI) 156 c->options |= LOONGARCH_CPU_EXTIOI; 157 if (config & IOCSRF_FREQSCALE) 158 c->options |= LOONGARCH_CPU_SCALEFREQ; 159 if (config & IOCSRF_FLATMODE) 160 c->options |= LOONGARCH_CPU_FLATMODE; 161 if (config & IOCSRF_EIODECODE) 162 c->options |= LOONGARCH_CPU_EIODECODE; 163 if (config & IOCSRF_VM) 164 c->options |= LOONGARCH_CPU_HYPERVISOR; 165 166 config = csr_read32(LOONGARCH_CSR_ASID); 167 config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT; 168 asid_mask = GENMASK(config - 1, 0); 169 set_cpu_asid_mask(c, asid_mask); 170 171 config = read_csr_prcfg1(); 172 c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0); 173 c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK); 174 175 config = read_csr_prcfg3(); 176 switch (config & CSR_CONF3_TLBTYPE) { 177 case 0: 178 c->tlbsizemtlb = 0; 179 c->tlbsizestlbsets = 0; 180 c->tlbsizestlbways = 0; 181 c->tlbsize = 0; 182 break; 183 case 1: 184 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1; 185 c->tlbsizestlbsets = 0; 186 c->tlbsizestlbways = 0; 187 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; 188 break; 189 case 2: 190 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1; 191 c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT); 192 c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1; 193 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; 194 break; 195 default: 196 pr_warn("Warning: unknown TLB type\n"); 197 } 198 } 199 200 #define MAX_NAME_LEN 32 201 #define VENDOR_OFFSET 0 202 #define CPUNAME_OFFSET 9 203 204 static char cpu_full_name[MAX_NAME_LEN] = " - "; 205 206 static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu) 207 { 208 uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]); 209 uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]); 210 211 if (!__cpu_full_name[cpu]) 212 __cpu_full_name[cpu] = cpu_full_name; 213 214 *vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR); 215 *cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME); 216 217 switch (c->processor_id & PRID_SERIES_MASK) { 218 case PRID_SERIES_LA132: 219 c->cputype = CPU_LOONGSON32; 220 set_isa(c, LOONGARCH_CPU_ISA_LA32S); 221 __cpu_family[cpu] = "Loongson-32bit"; 222 pr_info("32-bit Loongson Processor probed (LA132 Core)\n"); 223 break; 224 case PRID_SERIES_LA264: 225 c->cputype = CPU_LOONGSON64; 226 set_isa(c, LOONGARCH_CPU_ISA_LA64); 227 __cpu_family[cpu] = "Loongson-64bit"; 228 pr_info("64-bit Loongson Processor probed (LA264 Core)\n"); 229 break; 230 case PRID_SERIES_LA364: 231 c->cputype = CPU_LOONGSON64; 232 set_isa(c, LOONGARCH_CPU_ISA_LA64); 233 __cpu_family[cpu] = "Loongson-64bit"; 234 pr_info("64-bit Loongson Processor probed (LA364 Core)\n"); 235 break; 236 case PRID_SERIES_LA464: 237 c->cputype = CPU_LOONGSON64; 238 set_isa(c, LOONGARCH_CPU_ISA_LA64); 239 __cpu_family[cpu] = "Loongson-64bit"; 240 pr_info("64-bit Loongson Processor probed (LA464 Core)\n"); 241 break; 242 case PRID_SERIES_LA664: 243 c->cputype = CPU_LOONGSON64; 244 set_isa(c, LOONGARCH_CPU_ISA_LA64); 245 __cpu_family[cpu] = "Loongson-64bit"; 246 pr_info("64-bit Loongson Processor probed (LA664 Core)\n"); 247 break; 248 default: /* Default to 64 bit */ 249 c->cputype = CPU_LOONGSON64; 250 set_isa(c, LOONGARCH_CPU_ISA_LA64); 251 __cpu_family[cpu] = "Loongson-64bit"; 252 pr_info("64-bit Loongson Processor probed (Unknown Core)\n"); 253 } 254 } 255 256 #ifdef CONFIG_64BIT 257 /* For use by uaccess.h */ 258 u64 __ua_limit; 259 EXPORT_SYMBOL(__ua_limit); 260 #endif 261 262 const char *__cpu_family[NR_CPUS]; 263 const char *__cpu_full_name[NR_CPUS]; 264 const char *__elf_platform; 265 266 static void cpu_report(void) 267 { 268 struct cpuinfo_loongarch *c = ¤t_cpu_data; 269 270 pr_info("CPU%d revision is: %08x (%s)\n", 271 smp_processor_id(), c->processor_id, cpu_family_string()); 272 if (c->options & LOONGARCH_CPU_FPU) 273 pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers); 274 } 275 276 void cpu_probe(void) 277 { 278 unsigned int cpu = smp_processor_id(); 279 struct cpuinfo_loongarch *c = ¤t_cpu_data; 280 281 /* 282 * Set a default ELF platform, cpu probe may later 283 * overwrite it with a more precise value 284 */ 285 set_elf_platform(cpu, "loongarch"); 286 287 c->cputype = CPU_UNKNOWN; 288 c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0); 289 c->fpu_vers = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3; 290 291 c->fpu_csr0 = FPU_CSR_RN; 292 c->fpu_mask = FPU_CSR_RSVD; 293 294 cpu_probe_common(c); 295 296 per_cpu_trap_init(cpu); 297 298 switch (c->processor_id & PRID_COMP_MASK) { 299 case PRID_COMP_LOONGSON: 300 cpu_probe_loongson(c, cpu); 301 break; 302 } 303 304 BUG_ON(!__cpu_family[cpu]); 305 BUG_ON(c->cputype == CPU_UNKNOWN); 306 307 cpu_probe_addrbits(c); 308 309 #ifdef CONFIG_64BIT 310 if (cpu == 0) 311 __ua_limit = ~((1ull << cpu_vabits) - 1); 312 #endif 313 314 cpu_report(); 315 } 316