1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_PROCESSOR_H 6 #define _ASM_PROCESSOR_H 7 8 #include <linux/atomic.h> 9 #include <linux/cpumask.h> 10 #include <linux/sizes.h> 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/hw_breakpoint.h> 15 #include <asm/loongarch.h> 16 #include <asm/vdso/processor.h> 17 #include <uapi/asm/ptrace.h> 18 #include <uapi/asm/sigcontext.h> 19 20 #ifdef CONFIG_32BIT 21 22 #define TASK_SIZE 0x80000000UL 23 #define TASK_SIZE_MIN TASK_SIZE 24 #define STACK_TOP_MAX TASK_SIZE 25 26 #define TASK_IS_32BIT_ADDR 1 27 28 #endif 29 30 #ifdef CONFIG_64BIT 31 32 #define TASK_SIZE32 0x100000000UL 33 #define TASK_SIZE64 (0x1UL << ((cpu_vabits > VA_BITS) ? VA_BITS : cpu_vabits)) 34 35 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 36 #define TASK_SIZE_MIN TASK_SIZE32 37 #define STACK_TOP_MAX TASK_SIZE64 38 39 #define TASK_SIZE_OF(tsk) \ 40 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 41 42 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR) 43 44 #endif 45 46 #define VDSO_RANDOMIZE_SIZE (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M) 47 48 unsigned long stack_top(void); 49 #define STACK_TOP stack_top() 50 51 /* 52 * This decides where the kernel will search for a free chunk of vm 53 * space during mmap's. 54 */ 55 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) 56 57 #define FPU_REG_WIDTH 256 58 #define FPU_ALIGN __attribute__((aligned(32))) 59 60 union fpureg { 61 __u32 val32[FPU_REG_WIDTH / 32]; 62 __u64 val64[FPU_REG_WIDTH / 64]; 63 }; 64 65 #define FPR_IDX(width, idx) (idx) 66 67 #define BUILD_FPR_ACCESS(width) \ 68 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \ 69 { \ 70 return fpr->val##width[FPR_IDX(width, idx)]; \ 71 } \ 72 \ 73 static inline void set_fpr##width(union fpureg *fpr, unsigned int idx, \ 74 u##width val) \ 75 { \ 76 fpr->val##width[FPR_IDX(width, idx)] = val; \ 77 } 78 79 BUILD_FPR_ACCESS(32) 80 BUILD_FPR_ACCESS(64) 81 82 struct loongarch_fpu { 83 unsigned int fcsr; 84 uint64_t fcc; /* 8x8 */ 85 union fpureg fpr[NUM_FPU_REGS]; 86 }; 87 88 #define INIT_CPUMASK { \ 89 {0,} \ 90 } 91 92 #define ARCH_MIN_TASKALIGN 32 93 94 struct loongarch_vdso_info; 95 96 /* 97 * If you change thread_struct remember to change the #defines below too! 98 */ 99 struct thread_struct { 100 /* Main processor registers. */ 101 unsigned long reg01, reg03, reg22; /* ra sp fp */ 102 unsigned long reg23, reg24, reg25, reg26; /* s0-s3 */ 103 unsigned long reg27, reg28, reg29, reg30, reg31; /* s4-s8 */ 104 105 /* __schedule() return address / call frame address */ 106 unsigned long sched_ra; 107 unsigned long sched_cfa; 108 109 /* CSR registers */ 110 unsigned long csr_prmd; 111 unsigned long csr_crmd; 112 unsigned long csr_euen; 113 unsigned long csr_ecfg; 114 unsigned long csr_badvaddr; /* Last user fault */ 115 116 /* Scratch registers */ 117 unsigned long scr0; 118 unsigned long scr1; 119 unsigned long scr2; 120 unsigned long scr3; 121 122 /* Eflags register */ 123 unsigned long eflags; 124 125 /* Other stuff associated with the thread. */ 126 unsigned long trap_nr; 127 unsigned long error_code; 128 unsigned long single_step; /* Used by PTRACE_SINGLESTEP */ 129 struct loongarch_vdso_info *vdso; 130 131 /* 132 * FPU & vector registers, must be at the last of inherited 133 * context because they are conditionally copied at fork(). 134 */ 135 struct loongarch_fpu fpu FPU_ALIGN; 136 137 /* Hardware breakpoints pinned to this task. */ 138 struct perf_event *hbp_break[LOONGARCH_MAX_BRP]; 139 struct perf_event *hbp_watch[LOONGARCH_MAX_WRP]; 140 }; 141 142 #define thread_saved_ra(tsk) (tsk->thread.sched_ra) 143 #define thread_saved_fp(tsk) (tsk->thread.sched_cfa) 144 145 #define INIT_THREAD { \ 146 /* \ 147 * Main processor registers \ 148 */ \ 149 .reg01 = 0, \ 150 .reg03 = 0, \ 151 .reg22 = 0, \ 152 .reg23 = 0, \ 153 .reg24 = 0, \ 154 .reg25 = 0, \ 155 .reg26 = 0, \ 156 .reg27 = 0, \ 157 .reg28 = 0, \ 158 .reg29 = 0, \ 159 .reg30 = 0, \ 160 .reg31 = 0, \ 161 .sched_ra = 0, \ 162 .sched_cfa = 0, \ 163 .csr_crmd = 0, \ 164 .csr_prmd = 0, \ 165 .csr_euen = 0, \ 166 .csr_ecfg = 0, \ 167 .csr_badvaddr = 0, \ 168 /* \ 169 * Other stuff associated with the process \ 170 */ \ 171 .trap_nr = 0, \ 172 .error_code = 0, \ 173 /* \ 174 * FPU & vector registers \ 175 */ \ 176 .fpu = { \ 177 .fcsr = 0, \ 178 .fcc = 0, \ 179 .fpr = {{{0,},},}, \ 180 }, \ 181 .hbp_break = {0}, \ 182 .hbp_watch = {0}, \ 183 } 184 185 struct task_struct; 186 187 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_HALT, IDLE_NOMWAIT, IDLE_POLL}; 188 189 extern unsigned long boot_option_idle_override; 190 /* 191 * Do necessary setup to start up a newly executed thread. 192 */ 193 extern void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp); 194 195 unsigned long __get_wchan(struct task_struct *p); 196 197 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 198 THREAD_SIZE - sizeof(struct pt_regs)) 199 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 200 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->csr_era) 201 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[3]) 202 #define KSTK_EUEN(tsk) (task_pt_regs(tsk)->csr_euen) 203 #define KSTK_ECFG(tsk) (task_pt_regs(tsk)->csr_ecfg) 204 205 #define return_address() ({__asm__ __volatile__("":::"$1"); __builtin_return_address(0);}) 206 207 #ifdef CONFIG_CPU_HAS_PREFETCH 208 209 #define ARCH_HAS_PREFETCH 210 #define prefetch(x) __builtin_prefetch((x), 0, 1) 211 212 #define ARCH_HAS_PREFETCHW 213 #define prefetchw(x) __builtin_prefetch((x), 1, 1) 214 215 #endif 216 217 #endif /* _ASM_PROCESSOR_H */ 218