1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_LOONGARCH_H 6 #define _ASM_LOONGARCH_H 7 8 #include <linux/bits.h> 9 #include <linux/linkage.h> 10 #include <linux/types.h> 11 12 #ifndef __ASSEMBLY__ 13 #include <larchintrin.h> 14 15 /* 16 * parse_r var, r - Helper assembler macro for parsing register names. 17 * 18 * This converts the register name in $n form provided in \r to the 19 * corresponding register number, which is assigned to the variable \var. It is 20 * needed to allow explicit encoding of instructions in inline assembly where 21 * registers are chosen by the compiler in $n form, allowing us to avoid using 22 * fixed register numbers. 23 * 24 * It also allows newer instructions (not implemented by the assembler) to be 25 * transparently implemented using assembler macros, instead of needing separate 26 * cases depending on toolchain support. 27 * 28 * Simple usage example: 29 * __asm__ __volatile__("parse_r addr, %0\n\t" 30 * "#invtlb op, 0, %0\n\t" 31 * ".word ((0x6498000) | (addr << 10) | (0 << 5) | op)" 32 * : "=r" (status); 33 */ 34 35 /* Match an individual register number and assign to \var */ 36 #define _IFC_REG(n) \ 37 ".ifc \\r, $r" #n "\n\t" \ 38 "\\var = " #n "\n\t" \ 39 ".endif\n\t" 40 41 __asm__(".macro parse_r var r\n\t" 42 "\\var = -1\n\t" 43 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) 44 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) 45 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) 46 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) 47 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) 48 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) 49 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) 50 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) 51 ".iflt \\var\n\t" 52 ".error \"Unable to parse register name \\r\"\n\t" 53 ".endif\n\t" 54 ".endm"); 55 56 #undef _IFC_REG 57 58 /* CPUCFG */ 59 static inline u32 read_cpucfg(u32 reg) 60 { 61 return __cpucfg(reg); 62 } 63 64 #endif /* !__ASSEMBLY__ */ 65 66 #ifdef __ASSEMBLY__ 67 68 /* LoongArch Registers */ 69 #define REG_ZERO 0x0 70 #define REG_RA 0x1 71 #define REG_TP 0x2 72 #define REG_SP 0x3 73 #define REG_A0 0x4 /* Reused as V0 for return value */ 74 #define REG_A1 0x5 /* Reused as V1 for return value */ 75 #define REG_A2 0x6 76 #define REG_A3 0x7 77 #define REG_A4 0x8 78 #define REG_A5 0x9 79 #define REG_A6 0xa 80 #define REG_A7 0xb 81 #define REG_T0 0xc 82 #define REG_T1 0xd 83 #define REG_T2 0xe 84 #define REG_T3 0xf 85 #define REG_T4 0x10 86 #define REG_T5 0x11 87 #define REG_T6 0x12 88 #define REG_T7 0x13 89 #define REG_T8 0x14 90 #define REG_U0 0x15 /* Kernel uses it as percpu base */ 91 #define REG_FP 0x16 92 #define REG_S0 0x17 93 #define REG_S1 0x18 94 #define REG_S2 0x19 95 #define REG_S3 0x1a 96 #define REG_S4 0x1b 97 #define REG_S5 0x1c 98 #define REG_S6 0x1d 99 #define REG_S7 0x1e 100 #define REG_S8 0x1f 101 102 #endif /* __ASSEMBLY__ */ 103 104 /* Bit fields for CPUCFG registers */ 105 #define LOONGARCH_CPUCFG0 0x0 106 #define CPUCFG0_PRID GENMASK(31, 0) 107 108 #define LOONGARCH_CPUCFG1 0x1 109 #define CPUCFG1_ISGR32 BIT(0) 110 #define CPUCFG1_ISGR64 BIT(1) 111 #define CPUCFG1_PAGING BIT(2) 112 #define CPUCFG1_IOCSR BIT(3) 113 #define CPUCFG1_PABITS GENMASK(11, 4) 114 #define CPUCFG1_VABITS GENMASK(19, 12) 115 #define CPUCFG1_UAL BIT(20) 116 #define CPUCFG1_RI BIT(21) 117 #define CPUCFG1_EP BIT(22) 118 #define CPUCFG1_RPLV BIT(23) 119 #define CPUCFG1_HUGEPG BIT(24) 120 #define CPUCFG1_CRC32 BIT(25) 121 #define CPUCFG1_MSGINT BIT(26) 122 123 #define LOONGARCH_CPUCFG2 0x2 124 #define CPUCFG2_FP BIT(0) 125 #define CPUCFG2_FPSP BIT(1) 126 #define CPUCFG2_FPDP BIT(2) 127 #define CPUCFG2_FPVERS GENMASK(5, 3) 128 #define CPUCFG2_LSX BIT(6) 129 #define CPUCFG2_LASX BIT(7) 130 #define CPUCFG2_COMPLEX BIT(8) 131 #define CPUCFG2_CRYPTO BIT(9) 132 #define CPUCFG2_LVZP BIT(10) 133 #define CPUCFG2_LVZVER GENMASK(13, 11) 134 #define CPUCFG2_LLFTP BIT(14) 135 #define CPUCFG2_LLFTPREV GENMASK(17, 15) 136 #define CPUCFG2_X86BT BIT(18) 137 #define CPUCFG2_ARMBT BIT(19) 138 #define CPUCFG2_MIPSBT BIT(20) 139 #define CPUCFG2_LSPW BIT(21) 140 #define CPUCFG2_LAM BIT(22) 141 142 #define LOONGARCH_CPUCFG3 0x3 143 #define CPUCFG3_CCDMA BIT(0) 144 #define CPUCFG3_SFB BIT(1) 145 #define CPUCFG3_UCACC BIT(2) 146 #define CPUCFG3_LLEXC BIT(3) 147 #define CPUCFG3_SCDLY BIT(4) 148 #define CPUCFG3_LLDBAR BIT(5) 149 #define CPUCFG3_ITLBT BIT(6) 150 #define CPUCFG3_ICACHET BIT(7) 151 #define CPUCFG3_SPW_LVL GENMASK(10, 8) 152 #define CPUCFG3_SPW_HG_HF BIT(11) 153 #define CPUCFG3_RVA BIT(12) 154 #define CPUCFG3_RVAMAX GENMASK(16, 13) 155 156 #define LOONGARCH_CPUCFG4 0x4 157 #define CPUCFG4_CCFREQ GENMASK(31, 0) 158 159 #define LOONGARCH_CPUCFG5 0x5 160 #define CPUCFG5_CCMUL GENMASK(15, 0) 161 #define CPUCFG5_CCDIV GENMASK(31, 16) 162 163 #define LOONGARCH_CPUCFG6 0x6 164 #define CPUCFG6_PMP BIT(0) 165 #define CPUCFG6_PAMVER GENMASK(3, 1) 166 #define CPUCFG6_PMNUM GENMASK(7, 4) 167 #define CPUCFG6_PMBITS GENMASK(13, 8) 168 #define CPUCFG6_UPM BIT(14) 169 170 #define LOONGARCH_CPUCFG16 0x10 171 #define CPUCFG16_L1_IUPRE BIT(0) 172 #define CPUCFG16_L1_IUUNIFY BIT(1) 173 #define CPUCFG16_L1_DPRE BIT(2) 174 #define CPUCFG16_L2_IUPRE BIT(3) 175 #define CPUCFG16_L2_IUUNIFY BIT(4) 176 #define CPUCFG16_L2_IUPRIV BIT(5) 177 #define CPUCFG16_L2_IUINCL BIT(6) 178 #define CPUCFG16_L2_DPRE BIT(7) 179 #define CPUCFG16_L2_DPRIV BIT(8) 180 #define CPUCFG16_L2_DINCL BIT(9) 181 #define CPUCFG16_L3_IUPRE BIT(10) 182 #define CPUCFG16_L3_IUUNIFY BIT(11) 183 #define CPUCFG16_L3_IUPRIV BIT(12) 184 #define CPUCFG16_L3_IUINCL BIT(13) 185 #define CPUCFG16_L3_DPRE BIT(14) 186 #define CPUCFG16_L3_DPRIV BIT(15) 187 #define CPUCFG16_L3_DINCL BIT(16) 188 189 #define LOONGARCH_CPUCFG17 0x11 190 #define LOONGARCH_CPUCFG18 0x12 191 #define LOONGARCH_CPUCFG19 0x13 192 #define LOONGARCH_CPUCFG20 0x14 193 #define CPUCFG_CACHE_WAYS_M GENMASK(15, 0) 194 #define CPUCFG_CACHE_SETS_M GENMASK(23, 16) 195 #define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24) 196 #define CPUCFG_CACHE_WAYS 0 197 #define CPUCFG_CACHE_SETS 16 198 #define CPUCFG_CACHE_LSIZE 24 199 200 #define LOONGARCH_CPUCFG48 0x30 201 #define CPUCFG48_MCSR_LCK BIT(0) 202 #define CPUCFG48_NAP_EN BIT(1) 203 #define CPUCFG48_VFPU_CG BIT(2) 204 #define CPUCFG48_RAM_CG BIT(3) 205 206 #ifndef __ASSEMBLY__ 207 208 /* CSR */ 209 static __always_inline u32 csr_read32(u32 reg) 210 { 211 return __csrrd_w(reg); 212 } 213 214 static __always_inline u64 csr_read64(u32 reg) 215 { 216 return __csrrd_d(reg); 217 } 218 219 static __always_inline void csr_write32(u32 val, u32 reg) 220 { 221 __csrwr_w(val, reg); 222 } 223 224 static __always_inline void csr_write64(u64 val, u32 reg) 225 { 226 __csrwr_d(val, reg); 227 } 228 229 static __always_inline u32 csr_xchg32(u32 val, u32 mask, u32 reg) 230 { 231 return __csrxchg_w(val, mask, reg); 232 } 233 234 static __always_inline u64 csr_xchg64(u64 val, u64 mask, u32 reg) 235 { 236 return __csrxchg_d(val, mask, reg); 237 } 238 239 /* IOCSR */ 240 static __always_inline u32 iocsr_read32(u32 reg) 241 { 242 return __iocsrrd_w(reg); 243 } 244 245 static __always_inline u64 iocsr_read64(u32 reg) 246 { 247 return __iocsrrd_d(reg); 248 } 249 250 static __always_inline void iocsr_write32(u32 val, u32 reg) 251 { 252 __iocsrwr_w(val, reg); 253 } 254 255 static __always_inline void iocsr_write64(u64 val, u32 reg) 256 { 257 __iocsrwr_d(val, reg); 258 } 259 260 #endif /* !__ASSEMBLY__ */ 261 262 /* CSR register number */ 263 264 /* Basic CSR registers */ 265 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 266 #define CSR_CRMD_WE_SHIFT 9 267 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT) 268 #define CSR_CRMD_DACM_SHIFT 7 269 #define CSR_CRMD_DACM_WIDTH 2 270 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT) 271 #define CSR_CRMD_DACF_SHIFT 5 272 #define CSR_CRMD_DACF_WIDTH 2 273 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT) 274 #define CSR_CRMD_PG_SHIFT 4 275 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT) 276 #define CSR_CRMD_DA_SHIFT 3 277 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT) 278 #define CSR_CRMD_IE_SHIFT 2 279 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT) 280 #define CSR_CRMD_PLV_SHIFT 0 281 #define CSR_CRMD_PLV_WIDTH 2 282 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT) 283 284 #define PLV_KERN 0 285 #define PLV_USER 3 286 #define PLV_MASK 0x3 287 288 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 289 #define CSR_PRMD_PWE_SHIFT 3 290 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT) 291 #define CSR_PRMD_PIE_SHIFT 2 292 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT) 293 #define CSR_PRMD_PPLV_SHIFT 0 294 #define CSR_PRMD_PPLV_WIDTH 2 295 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT) 296 297 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */ 298 #define CSR_EUEN_LBTEN_SHIFT 3 299 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT) 300 #define CSR_EUEN_LASXEN_SHIFT 2 301 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT) 302 #define CSR_EUEN_LSXEN_SHIFT 1 303 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT) 304 #define CSR_EUEN_FPEN_SHIFT 0 305 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT) 306 307 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */ 308 309 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ 310 #define CSR_ECFG_VS_SHIFT 16 311 #define CSR_ECFG_VS_WIDTH 3 312 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT) 313 #define CSR_ECFG_IM_SHIFT 0 314 #define CSR_ECFG_IM_WIDTH 14 315 #define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT) 316 317 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 318 #define CSR_ESTAT_ESUBCODE_SHIFT 22 319 #define CSR_ESTAT_ESUBCODE_WIDTH 9 320 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT) 321 #define CSR_ESTAT_EXC_SHIFT 16 322 #define CSR_ESTAT_EXC_WIDTH 6 323 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT) 324 #define CSR_ESTAT_IS_SHIFT 0 325 #define CSR_ESTAT_IS_WIDTH 14 326 #define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT) 327 328 #define LOONGARCH_CSR_ERA 0x6 /* ERA */ 329 330 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 331 332 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */ 333 334 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */ 335 336 /* TLB related CSR registers */ 337 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */ 338 #define CSR_TLBIDX_EHINV_SHIFT 31 339 #define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT) 340 #define CSR_TLBIDX_PS_SHIFT 24 341 #define CSR_TLBIDX_PS_WIDTH 6 342 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT) 343 #define CSR_TLBIDX_IDX_SHIFT 0 344 #define CSR_TLBIDX_IDX_WIDTH 12 345 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT) 346 #define CSR_TLBIDX_SIZEM 0x3f000000 347 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT 348 #define CSR_TLBIDX_IDXM 0xfff 349 #define CSR_INVALID_ENTRY(e) (CSR_TLBIDX_EHINV | e) 350 351 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ 352 353 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ 354 #define CSR_TLBLO0_RPLV_SHIFT 63 355 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT) 356 #define CSR_TLBLO0_NX_SHIFT 62 357 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT) 358 #define CSR_TLBLO0_NR_SHIFT 61 359 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT) 360 #define CSR_TLBLO0_PFN_SHIFT 12 361 #define CSR_TLBLO0_PFN_WIDTH 36 362 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT) 363 #define CSR_TLBLO0_GLOBAL_SHIFT 6 364 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT) 365 #define CSR_TLBLO0_CCA_SHIFT 4 366 #define CSR_TLBLO0_CCA_WIDTH 2 367 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT) 368 #define CSR_TLBLO0_PLV_SHIFT 2 369 #define CSR_TLBLO0_PLV_WIDTH 2 370 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT) 371 #define CSR_TLBLO0_WE_SHIFT 1 372 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT) 373 #define CSR_TLBLO0_V_SHIFT 0 374 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT) 375 376 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ 377 #define CSR_TLBLO1_RPLV_SHIFT 63 378 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT) 379 #define CSR_TLBLO1_NX_SHIFT 62 380 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT) 381 #define CSR_TLBLO1_NR_SHIFT 61 382 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT) 383 #define CSR_TLBLO1_PFN_SHIFT 12 384 #define CSR_TLBLO1_PFN_WIDTH 36 385 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT) 386 #define CSR_TLBLO1_GLOBAL_SHIFT 6 387 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT) 388 #define CSR_TLBLO1_CCA_SHIFT 4 389 #define CSR_TLBLO1_CCA_WIDTH 2 390 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT) 391 #define CSR_TLBLO1_PLV_SHIFT 2 392 #define CSR_TLBLO1_PLV_WIDTH 2 393 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT) 394 #define CSR_TLBLO1_WE_SHIFT 1 395 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT) 396 #define CSR_TLBLO1_V_SHIFT 0 397 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT) 398 399 #define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */ 400 #define CSR_GTLBC_RID_SHIFT 16 401 #define CSR_GTLBC_RID_WIDTH 8 402 #define CSR_GTLBC_RID (_ULCAST_(0xff) << CSR_GTLBC_RID_SHIFT) 403 #define CSR_GTLBC_TOTI_SHIFT 13 404 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT) 405 #define CSR_GTLBC_USERID_SHIFT 12 406 #define CSR_GTLBC_USERID (_ULCAST_(0x1) << CSR_GTLBC_USERID_SHIFT) 407 #define CSR_GTLBC_GMTLBSZ_SHIFT 0 408 #define CSR_GTLBC_GMTLBSZ_WIDTH 6 409 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT) 410 411 #define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */ 412 #define CSR_TRGP_RID_SHIFT 16 413 #define CSR_TRGP_RID_WIDTH 8 414 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT) 415 #define CSR_TRGP_GTLB_SHIFT 0 416 #define CSR_TRGP_GTLB (1 << CSR_TRGP_GTLB_SHIFT) 417 418 #define LOONGARCH_CSR_ASID 0x18 /* ASID */ 419 #define CSR_ASID_BIT_SHIFT 16 /* ASIDBits */ 420 #define CSR_ASID_BIT_WIDTH 8 421 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT) 422 #define CSR_ASID_ASID_SHIFT 0 423 #define CSR_ASID_ASID_WIDTH 10 424 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT) 425 426 #define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */ 427 428 #define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */ 429 430 #define LOONGARCH_CSR_PGD 0x1b /* Page table base */ 431 432 #define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */ 433 #define CSR_PWCTL0_PTEW_SHIFT 30 434 #define CSR_PWCTL0_PTEW_WIDTH 2 435 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT) 436 #define CSR_PWCTL0_DIR1WIDTH_SHIFT 25 437 #define CSR_PWCTL0_DIR1WIDTH_WIDTH 5 438 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT) 439 #define CSR_PWCTL0_DIR1BASE_SHIFT 20 440 #define CSR_PWCTL0_DIR1BASE_WIDTH 5 441 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT) 442 #define CSR_PWCTL0_DIR0WIDTH_SHIFT 15 443 #define CSR_PWCTL0_DIR0WIDTH_WIDTH 5 444 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT) 445 #define CSR_PWCTL0_DIR0BASE_SHIFT 10 446 #define CSR_PWCTL0_DIR0BASE_WIDTH 5 447 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT) 448 #define CSR_PWCTL0_PTWIDTH_SHIFT 5 449 #define CSR_PWCTL0_PTWIDTH_WIDTH 5 450 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT) 451 #define CSR_PWCTL0_PTBASE_SHIFT 0 452 #define CSR_PWCTL0_PTBASE_WIDTH 5 453 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT) 454 455 #define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */ 456 #define CSR_PWCTL1_DIR3WIDTH_SHIFT 18 457 #define CSR_PWCTL1_DIR3WIDTH_WIDTH 5 458 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT) 459 #define CSR_PWCTL1_DIR3BASE_SHIFT 12 460 #define CSR_PWCTL1_DIR3BASE_WIDTH 5 461 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT) 462 #define CSR_PWCTL1_DIR2WIDTH_SHIFT 6 463 #define CSR_PWCTL1_DIR2WIDTH_WIDTH 5 464 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT) 465 #define CSR_PWCTL1_DIR2BASE_SHIFT 0 466 #define CSR_PWCTL1_DIR2BASE_WIDTH 5 467 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT) 468 469 #define LOONGARCH_CSR_STLBPGSIZE 0x1e 470 #define CSR_STLBPGSIZE_PS_WIDTH 6 471 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f)) 472 473 #define LOONGARCH_CSR_RVACFG 0x1f 474 #define CSR_RVACFG_RDVA_WIDTH 4 475 #define CSR_RVACFG_RDVA (_ULCAST_(0xf)) 476 477 /* Config CSR registers */ 478 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */ 479 #define CSR_CPUID_COREID_WIDTH 9 480 #define CSR_CPUID_COREID _ULCAST_(0x1ff) 481 482 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */ 483 #define CSR_CONF1_VSMAX_SHIFT 12 484 #define CSR_CONF1_VSMAX_WIDTH 3 485 #define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT) 486 #define CSR_CONF1_TMRBITS_SHIFT 4 487 #define CSR_CONF1_TMRBITS_WIDTH 8 488 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT) 489 #define CSR_CONF1_KSNUM_WIDTH 4 490 #define CSR_CONF1_KSNUM _ULCAST_(0xf) 491 492 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */ 493 #define CSR_CONF2_PGMASK_SUPP 0x3ffff000 494 495 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */ 496 #define CSR_CONF3_STLBIDX_SHIFT 20 497 #define CSR_CONF3_STLBIDX_WIDTH 6 498 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT) 499 #define CSR_CONF3_STLBWAYS_SHIFT 12 500 #define CSR_CONF3_STLBWAYS_WIDTH 8 501 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT) 502 #define CSR_CONF3_MTLBSIZE_SHIFT 4 503 #define CSR_CONF3_MTLBSIZE_WIDTH 8 504 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT) 505 #define CSR_CONF3_TLBTYPE_SHIFT 0 506 #define CSR_CONF3_TLBTYPE_WIDTH 4 507 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT) 508 509 /* KSave registers */ 510 #define LOONGARCH_CSR_KS0 0x30 511 #define LOONGARCH_CSR_KS1 0x31 512 #define LOONGARCH_CSR_KS2 0x32 513 #define LOONGARCH_CSR_KS3 0x33 514 #define LOONGARCH_CSR_KS4 0x34 515 #define LOONGARCH_CSR_KS5 0x35 516 #define LOONGARCH_CSR_KS6 0x36 517 #define LOONGARCH_CSR_KS7 0x37 518 #define LOONGARCH_CSR_KS8 0x38 519 520 /* Exception allocated KS0, KS1 and KS2 statically */ 521 #define EXCEPTION_KS0 LOONGARCH_CSR_KS0 522 #define EXCEPTION_KS1 LOONGARCH_CSR_KS1 523 #define EXCEPTION_KS2 LOONGARCH_CSR_KS2 524 #define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2) 525 526 /* Percpu-data base allocated KS3 statically */ 527 #define PERCPU_BASE_KS LOONGARCH_CSR_KS3 528 #define PERCPU_KSAVE_MASK (1 << 3) 529 530 /* KVM allocated KS4 and KS5 statically */ 531 #define KVM_VCPU_KS LOONGARCH_CSR_KS4 532 #define KVM_TEMP_KS LOONGARCH_CSR_KS5 533 #define KVM_KSAVE_MASK (1 << 4 | 1 << 5) 534 535 /* Timer registers */ 536 #define LOONGARCH_CSR_TMID 0x40 /* Timer ID */ 537 538 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ 539 #define CSR_TCFG_VAL_SHIFT 2 540 #define CSR_TCFG_VAL_WIDTH 48 541 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT) 542 #define CSR_TCFG_PERIOD_SHIFT 1 543 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT) 544 #define CSR_TCFG_EN (_ULCAST_(0x1)) 545 546 #define LOONGARCH_CSR_TVAL 0x42 /* Timer value */ 547 548 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */ 549 550 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */ 551 #define CSR_TINTCLR_TI_SHIFT 0 552 #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT) 553 554 /* Guest registers */ 555 #define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */ 556 #define CSR_GSTAT_GID_SHIFT 16 557 #define CSR_GSTAT_GID_WIDTH 8 558 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT) 559 #define CSR_GSTAT_GIDBIT_SHIFT 4 560 #define CSR_GSTAT_GIDBIT_WIDTH 6 561 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT) 562 #define CSR_GSTAT_PVM_SHIFT 1 563 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT) 564 #define CSR_GSTAT_VM_SHIFT 0 565 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT) 566 567 #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ 568 #define CSR_GCFG_GPERF_SHIFT 24 569 #define CSR_GCFG_GPERF_WIDTH 3 570 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) 571 #define CSR_GCFG_GCI_SHIFT 20 572 #define CSR_GCFG_GCI_WIDTH 2 573 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) 574 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) 575 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) 576 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) 577 #define CSR_GCFG_GCIP_SHIFT 16 578 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) 579 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) 580 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) 581 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) 582 #define CSR_GCFG_TORU_SHIFT 15 583 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) 584 #define CSR_GCFG_TORUP_SHIFT 14 585 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) 586 #define CSR_GCFG_TOP_SHIFT 13 587 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) 588 #define CSR_GCFG_TOPP_SHIFT 12 589 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) 590 #define CSR_GCFG_TOE_SHIFT 11 591 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) 592 #define CSR_GCFG_TOEP_SHIFT 10 593 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) 594 #define CSR_GCFG_TIT_SHIFT 9 595 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) 596 #define CSR_GCFG_TITP_SHIFT 8 597 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) 598 #define CSR_GCFG_SIT_SHIFT 7 599 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) 600 #define CSR_GCFG_SITP_SHIFT 6 601 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) 602 #define CSR_GCFG_MATC_SHITF 4 603 #define CSR_GCFG_MATC_WIDTH 2 604 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) 605 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) 606 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) 607 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) 608 609 #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ 610 #define CSR_GINTC_HC_SHIFT 16 611 #define CSR_GINTC_HC_WIDTH 8 612 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT) 613 #define CSR_GINTC_PIP_SHIFT 8 614 #define CSR_GINTC_PIP_WIDTH 8 615 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT) 616 #define CSR_GINTC_VIP_SHIFT 0 617 #define CSR_GINTC_VIP_WIDTH 8 618 #define CSR_GINTC_VIP (_ULCAST_(0xff)) 619 620 #define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */ 621 622 /* LLBCTL register */ 623 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */ 624 #define CSR_LLBCTL_ROLLB_SHIFT 0 625 #define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT) 626 #define CSR_LLBCTL_WCLLB_SHIFT 1 627 #define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT) 628 #define CSR_LLBCTL_KLO_SHIFT 2 629 #define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT) 630 631 /* Implement dependent */ 632 #define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */ 633 #define CSR_MISPEC_SHIFT 20 634 #define CSR_MISPEC_WIDTH 8 635 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT) 636 #define CSR_SSEN_SHIFT 18 637 #define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT) 638 #define CSR_SCRAND_SHIFT 17 639 #define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT) 640 #define CSR_LLEXCL_SHIFT 16 641 #define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT) 642 #define CSR_DISVC_SHIFT 15 643 #define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT) 644 #define CSR_VCLRU_SHIFT 14 645 #define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT) 646 #define CSR_DCLRU_SHIFT 13 647 #define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT) 648 #define CSR_FASTLDQ_SHIFT 12 649 #define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT) 650 #define CSR_USERCAC_SHIFT 11 651 #define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT) 652 #define CSR_ANTI_MISPEC_SHIFT 10 653 #define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT) 654 #define CSR_AUTO_FLUSHSFB_SHIFT 9 655 #define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT) 656 #define CSR_STFILL_SHIFT 8 657 #define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT) 658 #define CSR_LIFEP_SHIFT 7 659 #define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT) 660 #define CSR_LLSYNC_SHIFT 6 661 #define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT) 662 #define CSR_BRBTDIS_SHIFT 5 663 #define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT) 664 #define CSR_RASDIS_SHIFT 4 665 #define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT) 666 #define CSR_STPRE_SHIFT 2 667 #define CSR_STPRE_WIDTH 2 668 #define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT) 669 #define CSR_INSTPRE_SHIFT 1 670 #define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT) 671 #define CSR_DATAPRE_SHIFT 0 672 #define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT) 673 674 #define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */ 675 #define CSR_FLUSH_MTLB_SHIFT 0 676 #define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT) 677 #define CSR_FLUSH_STLB_SHIFT 1 678 #define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT) 679 #define CSR_FLUSH_DTLB_SHIFT 2 680 #define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT) 681 #define CSR_FLUSH_ITLB_SHIFT 3 682 #define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT) 683 #define CSR_FLUSH_BTAC_SHIFT 4 684 #define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT) 685 686 #define LOONGARCH_CSR_GNMI 0x82 687 688 /* TLB Refill registers */ 689 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */ 690 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */ 691 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */ 692 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */ 693 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */ 694 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ 695 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ 696 #define CSR_TLBREHI_PS_SHIFT 0 697 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT) 698 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ 699 700 /* Machine Error registers */ 701 #define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */ 702 #define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */ 703 #define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */ 704 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */ 705 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */ 706 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */ 707 708 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ 709 710 #define LOONGARCH_CSR_PRID 0xc0 711 712 /* Shadow MCSR : 0xc0 ~ 0xff */ 713 #define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */ 714 #define MCSR0_INT_IMPL_SHIFT 58 715 #define MCSR0_INT_IMPL 0 716 #define MCSR0_IOCSR_BRD_SHIFT 57 717 #define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT) 718 #define MCSR0_HUGEPG_SHIFT 56 719 #define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT) 720 #define MCSR0_RPLMTLB_SHIFT 55 721 #define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT) 722 #define MCSR0_EP_SHIFT 54 723 #define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT) 724 #define MCSR0_RI_SHIFT 53 725 #define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT) 726 #define MCSR0_UAL_SHIFT 52 727 #define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT) 728 #define MCSR0_VABIT_SHIFT 44 729 #define MCSR0_VABIT_WIDTH 8 730 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT) 731 #define VABIT_DEFAULT 0x2f 732 #define MCSR0_PABIT_SHIFT 36 733 #define MCSR0_PABIT_WIDTH 8 734 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT) 735 #define PABIT_DEFAULT 0x2f 736 #define MCSR0_IOCSR_SHIFT 35 737 #define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT) 738 #define MCSR0_PAGING_SHIFT 34 739 #define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT) 740 #define MCSR0_GR64_SHIFT 33 741 #define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT) 742 #define GR64_DEFAULT 1 743 #define MCSR0_GR32_SHIFT 32 744 #define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT) 745 #define GR32_DEFAULT 0 746 #define MCSR0_PRID_WIDTH 32 747 #define MCSR0_PRID 0x14C010 748 749 #define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */ 750 #define MCSR1_HPFOLD_SHIFT 43 751 #define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT) 752 #define MCSR1_SPW_LVL_SHIFT 40 753 #define MCSR1_SPW_LVL_WIDTH 3 754 #define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT) 755 #define MCSR1_ICACHET_SHIFT 39 756 #define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT) 757 #define MCSR1_ITLBT_SHIFT 38 758 #define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT) 759 #define MCSR1_LLDBAR_SHIFT 37 760 #define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT) 761 #define MCSR1_SCDLY_SHIFT 36 762 #define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT) 763 #define MCSR1_LLEXC_SHIFT 35 764 #define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT) 765 #define MCSR1_UCACC_SHIFT 34 766 #define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT) 767 #define MCSR1_SFB_SHIFT 33 768 #define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT) 769 #define MCSR1_CCDMA_SHIFT 32 770 #define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT) 771 #define MCSR1_LAMO_SHIFT 22 772 #define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT) 773 #define MCSR1_LSPW_SHIFT 21 774 #define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT) 775 #define MCSR1_MIPSBT_SHIFT 20 776 #define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT) 777 #define MCSR1_ARMBT_SHIFT 19 778 #define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT) 779 #define MCSR1_X86BT_SHIFT 18 780 #define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT) 781 #define MCSR1_LLFTPVERS_SHIFT 15 782 #define MCSR1_LLFTPVERS_WIDTH 3 783 #define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT) 784 #define MCSR1_LLFTP_SHIFT 14 785 #define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT) 786 #define MCSR1_VZVERS_SHIFT 11 787 #define MCSR1_VZVERS_WIDTH 3 788 #define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT) 789 #define MCSR1_VZ_SHIFT 10 790 #define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT) 791 #define MCSR1_CRYPTO_SHIFT 9 792 #define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT) 793 #define MCSR1_COMPLEX_SHIFT 8 794 #define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT) 795 #define MCSR1_LASX_SHIFT 7 796 #define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT) 797 #define MCSR1_LSX_SHIFT 6 798 #define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT) 799 #define MCSR1_FPVERS_SHIFT 3 800 #define MCSR1_FPVERS_WIDTH 3 801 #define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT) 802 #define MCSR1_FPDP_SHIFT 2 803 #define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT) 804 #define MCSR1_FPSP_SHIFT 1 805 #define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT) 806 #define MCSR1_FP_SHIFT 0 807 #define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT) 808 809 #define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */ 810 #define MCSR2_CCDIV_SHIFT 48 811 #define MCSR2_CCDIV_WIDTH 16 812 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT) 813 #define MCSR2_CCMUL_SHIFT 32 814 #define MCSR2_CCMUL_WIDTH 16 815 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT) 816 #define MCSR2_CCFREQ_WIDTH 32 817 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff)) 818 #define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */ 819 820 #define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */ 821 #define MCSR3_UPM_SHIFT 14 822 #define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT) 823 #define MCSR3_PMBITS_SHIFT 8 824 #define MCSR3_PMBITS_WIDTH 6 825 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT) 826 #define PMBITS_DEFAULT 0x40 827 #define MCSR3_PMNUM_SHIFT 4 828 #define MCSR3_PMNUM_WIDTH 4 829 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT) 830 #define MCSR3_PAMVER_SHIFT 1 831 #define MCSR3_PAMVER_WIDTH 3 832 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT) 833 #define MCSR3_PMP_SHIFT 0 834 #define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT) 835 836 #define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */ 837 #define MCSR8_L1I_SIZE_SHIFT 56 838 #define MCSR8_L1I_SIZE_WIDTH 7 839 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT) 840 #define MCSR8_L1I_IDX_SHIFT 48 841 #define MCSR8_L1I_IDX_WIDTH 8 842 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT) 843 #define MCSR8_L1I_WAY_SHIFT 32 844 #define MCSR8_L1I_WAY_WIDTH 16 845 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT) 846 #define MCSR8_L3DINCL_SHIFT 16 847 #define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT) 848 #define MCSR8_L3DPRIV_SHIFT 15 849 #define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT) 850 #define MCSR8_L3DPRE_SHIFT 14 851 #define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT) 852 #define MCSR8_L3IUINCL_SHIFT 13 853 #define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT) 854 #define MCSR8_L3IUPRIV_SHIFT 12 855 #define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT) 856 #define MCSR8_L3IUUNIFY_SHIFT 11 857 #define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT) 858 #define MCSR8_L3IUPRE_SHIFT 10 859 #define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT) 860 #define MCSR8_L2DINCL_SHIFT 9 861 #define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT) 862 #define MCSR8_L2DPRIV_SHIFT 8 863 #define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT) 864 #define MCSR8_L2DPRE_SHIFT 7 865 #define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT) 866 #define MCSR8_L2IUINCL_SHIFT 6 867 #define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT) 868 #define MCSR8_L2IUPRIV_SHIFT 5 869 #define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT) 870 #define MCSR8_L2IUUNIFY_SHIFT 4 871 #define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT) 872 #define MCSR8_L2IUPRE_SHIFT 3 873 #define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT) 874 #define MCSR8_L1DPRE_SHIFT 2 875 #define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT) 876 #define MCSR8_L1IUUNIFY_SHIFT 1 877 #define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT) 878 #define MCSR8_L1IUPRE_SHIFT 0 879 #define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT) 880 881 #define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */ 882 #define MCSR9_L2U_SIZE_SHIFT 56 883 #define MCSR9_L2U_SIZE_WIDTH 7 884 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT) 885 #define MCSR9_L2U_IDX_SHIFT 48 886 #define MCSR9_L2U_IDX_WIDTH 8 887 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT) 888 #define MCSR9_L2U_WAY_SHIFT 32 889 #define MCSR9_L2U_WAY_WIDTH 16 890 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT) 891 #define MCSR9_L1D_SIZE_SHIFT 24 892 #define MCSR9_L1D_SIZE_WIDTH 7 893 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT) 894 #define MCSR9_L1D_IDX_SHIFT 16 895 #define MCSR9_L1D_IDX_WIDTH 8 896 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT) 897 #define MCSR9_L1D_WAY_SHIFT 0 898 #define MCSR9_L1D_WAY_WIDTH 16 899 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT) 900 901 #define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */ 902 #define MCSR10_L3U_SIZE_SHIFT 24 903 #define MCSR10_L3U_SIZE_WIDTH 7 904 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT) 905 #define MCSR10_L3U_IDX_SHIFT 16 906 #define MCSR10_L3U_IDX_WIDTH 8 907 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT) 908 #define MCSR10_L3U_WAY_SHIFT 0 909 #define MCSR10_L3U_WAY_WIDTH 16 910 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT) 911 912 #define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */ 913 #define MCSR24_RAMCG_SHIFT 3 914 #define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT) 915 #define MCSR24_VFPUCG_SHIFT 2 916 #define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT) 917 #define MCSR24_NAPEN_SHIFT 1 918 #define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT) 919 #define MCSR24_MCSRLOCK_SHIFT 0 920 #define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT) 921 922 /* Uncached accelerate windows registers */ 923 #define LOONGARCH_CSR_UCAWIN 0x100 924 #define LOONGARCH_CSR_UCAWIN0_LO 0x102 925 #define LOONGARCH_CSR_UCAWIN0_HI 0x103 926 #define LOONGARCH_CSR_UCAWIN1_LO 0x104 927 #define LOONGARCH_CSR_UCAWIN1_HI 0x105 928 #define LOONGARCH_CSR_UCAWIN2_LO 0x106 929 #define LOONGARCH_CSR_UCAWIN2_HI 0x107 930 #define LOONGARCH_CSR_UCAWIN3_LO 0x108 931 #define LOONGARCH_CSR_UCAWIN3_HI 0x109 932 933 /* Direct Map windows registers */ 934 #define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */ 935 #define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */ 936 #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */ 937 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */ 938 939 /* Direct Map window 0/1 */ 940 #define CSR_DMW0_PLV0 _CONST64_(1 << 0) 941 #define CSR_DMW0_VSEG _CONST64_(0x8000) 942 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) 943 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0) 944 945 #define CSR_DMW1_PLV0 _CONST64_(1 << 0) 946 #define CSR_DMW1_MAT _CONST64_(1 << 4) 947 #define CSR_DMW1_VSEG _CONST64_(0x9000) 948 #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) 949 #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) 950 951 /* Performance Counter registers */ 952 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */ 953 #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */ 954 #define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */ 955 #define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */ 956 #define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */ 957 #define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */ 958 #define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */ 959 #define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */ 960 #define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16) 961 #define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17) 962 #define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18) 963 #define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19) 964 #define CSR_PERFCTRL_IE (_ULCAST_(1) << 20) 965 #define CSR_PERFCTRL_EVENT 0x3ff 966 967 /* Debug registers */ 968 #define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */ 969 #define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */ 970 971 #define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */ 972 #define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */ 973 #define LOONGARCH_CSR_DB0CTRL 0x312 /* data breakpoint 0 control */ 974 #define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */ 975 976 #define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */ 977 #define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */ 978 #define LOONGARCH_CSR_DB1CTRL 0x31a /* data breakpoint 1 control */ 979 #define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */ 980 981 #define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */ 982 #define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */ 983 #define LOONGARCH_CSR_DB2CTRL 0x322 /* data breakpoint 2 control */ 984 #define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */ 985 986 #define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */ 987 #define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */ 988 #define LOONGARCH_CSR_DB3CTRL 0x32a /* data breakpoint 3 control */ 989 #define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */ 990 991 #define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */ 992 #define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */ 993 #define LOONGARCH_CSR_DB4CTRL 0x332 /* data breakpoint 4 control */ 994 #define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */ 995 996 #define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */ 997 #define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */ 998 #define LOONGARCH_CSR_DB5CTRL 0x33a /* data breakpoint 5 control */ 999 #define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */ 1000 1001 #define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */ 1002 #define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */ 1003 #define LOONGARCH_CSR_DB6CTRL 0x342 /* data breakpoint 6 control */ 1004 #define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */ 1005 1006 #define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */ 1007 #define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */ 1008 #define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */ 1009 #define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */ 1010 1011 #define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */ 1012 #define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */ 1013 1014 #define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */ 1015 #define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */ 1016 #define LOONGARCH_CSR_IB0CTRL 0x392 /* inst breakpoint 0 control */ 1017 #define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */ 1018 1019 #define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */ 1020 #define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */ 1021 #define LOONGARCH_CSR_IB1CTRL 0x39a /* inst breakpoint 1 control */ 1022 #define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */ 1023 1024 #define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */ 1025 #define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */ 1026 #define LOONGARCH_CSR_IB2CTRL 0x3a2 /* inst breakpoint 2 control */ 1027 #define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */ 1028 1029 #define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */ 1030 #define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */ 1031 #define LOONGARCH_CSR_IB3CTRL 0x3aa /* inst breakpoint 3 control */ 1032 #define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */ 1033 1034 #define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */ 1035 #define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */ 1036 #define LOONGARCH_CSR_IB4CTRL 0x3b2 /* inst breakpoint 4 control */ 1037 #define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */ 1038 1039 #define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */ 1040 #define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */ 1041 #define LOONGARCH_CSR_IB5CTRL 0x3ba /* inst breakpoint 5 control */ 1042 #define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */ 1043 1044 #define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */ 1045 #define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */ 1046 #define LOONGARCH_CSR_IB6CTRL 0x3c2 /* inst breakpoint 6 control */ 1047 #define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */ 1048 1049 #define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */ 1050 #define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */ 1051 #define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */ 1052 #define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */ 1053 1054 #define LOONGARCH_CSR_DEBUG 0x500 /* debug config */ 1055 #define LOONGARCH_CSR_DERA 0x501 /* debug era */ 1056 #define LOONGARCH_CSR_DESAVE 0x502 /* debug save */ 1057 1058 #define CSR_FWPC_SKIP_SHIFT 16 1059 #define CSR_FWPC_SKIP (_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT) 1060 1061 /* 1062 * CSR_ECFG IM 1063 */ 1064 #define ECFG0_IM 0x00001fff 1065 #define ECFGB_SIP0 0 1066 #define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0) 1067 #define ECFGB_SIP1 1 1068 #define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1) 1069 #define ECFGB_IP0 2 1070 #define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0) 1071 #define ECFGB_IP1 3 1072 #define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1) 1073 #define ECFGB_IP2 4 1074 #define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2) 1075 #define ECFGB_IP3 5 1076 #define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3) 1077 #define ECFGB_IP4 6 1078 #define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4) 1079 #define ECFGB_IP5 7 1080 #define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5) 1081 #define ECFGB_IP6 8 1082 #define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6) 1083 #define ECFGB_IP7 9 1084 #define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7) 1085 #define ECFGB_PMC 10 1086 #define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC) 1087 #define ECFGB_TIMER 11 1088 #define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER) 1089 #define ECFGB_IPI 12 1090 #define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI) 1091 #define ECFGF(hwirq) (_ULCAST_(1) << hwirq) 1092 1093 #define ESTATF_IP 0x00003fff 1094 1095 #define LOONGARCH_IOCSR_FEATURES 0x8 1096 #define IOCSRF_TEMP BIT_ULL(0) 1097 #define IOCSRF_NODECNT BIT_ULL(1) 1098 #define IOCSRF_MSI BIT_ULL(2) 1099 #define IOCSRF_EXTIOI BIT_ULL(3) 1100 #define IOCSRF_CSRIPI BIT_ULL(4) 1101 #define IOCSRF_FREQCSR BIT_ULL(5) 1102 #define IOCSRF_FREQSCALE BIT_ULL(6) 1103 #define IOCSRF_DVFSV1 BIT_ULL(7) 1104 #define IOCSRF_EIODECODE BIT_ULL(9) 1105 #define IOCSRF_FLATMODE BIT_ULL(10) 1106 #define IOCSRF_VM BIT_ULL(11) 1107 1108 #define LOONGARCH_IOCSR_VENDOR 0x10 1109 1110 #define LOONGARCH_IOCSR_CPUNAME 0x20 1111 1112 #define LOONGARCH_IOCSR_NODECNT 0x408 1113 1114 #define LOONGARCH_IOCSR_MISC_FUNC 0x420 1115 #define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21) 1116 #define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48) 1117 1118 #define LOONGARCH_IOCSR_CPUTEMP 0x428 1119 1120 /* PerCore CSR, only accessible by local cores */ 1121 #define LOONGARCH_IOCSR_IPI_STATUS 0x1000 1122 #define LOONGARCH_IOCSR_IPI_EN 0x1004 1123 #define LOONGARCH_IOCSR_IPI_SET 0x1008 1124 #define LOONGARCH_IOCSR_IPI_CLEAR 0x100c 1125 #define LOONGARCH_IOCSR_MBUF0 0x1020 1126 #define LOONGARCH_IOCSR_MBUF1 0x1028 1127 #define LOONGARCH_IOCSR_MBUF2 0x1030 1128 #define LOONGARCH_IOCSR_MBUF3 0x1038 1129 1130 #define LOONGARCH_IOCSR_IPI_SEND 0x1040 1131 #define IOCSR_IPI_SEND_IP_SHIFT 0 1132 #define IOCSR_IPI_SEND_CPU_SHIFT 16 1133 #define IOCSR_IPI_SEND_BLOCKING BIT(31) 1134 1135 #define LOONGARCH_IOCSR_MBUF_SEND 0x1048 1136 #define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31) 1137 #define IOCSR_MBUF_SEND_BOX_SHIFT 2 1138 #define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1) 1139 #define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1) 1140 #define IOCSR_MBUF_SEND_CPU_SHIFT 16 1141 #define IOCSR_MBUF_SEND_BUF_SHIFT 32 1142 #define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1143 1144 #define LOONGARCH_IOCSR_ANY_SEND 0x1158 1145 #define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31) 1146 #define IOCSR_ANY_SEND_CPU_SHIFT 16 1147 #define IOCSR_ANY_SEND_MASK_SHIFT 27 1148 #define IOCSR_ANY_SEND_BUF_SHIFT 32 1149 #define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1150 1151 /* Register offset and bit definition for CSR access */ 1152 #define LOONGARCH_IOCSR_TIMER_CFG 0x1060 1153 #define LOONGARCH_IOCSR_TIMER_TICK 0x1070 1154 #define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63) 1155 #define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62) 1156 #define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61) 1157 #define IOCSR_TIMER_MASK 0x0ffffffffffffULL 1158 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48) 1159 1160 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0 1161 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0 1162 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600 1163 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680 1164 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800 1165 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00 1166 #define IOCSR_EXTIOI_VECTOR_NUM 256 1167 1168 #ifndef __ASSEMBLY__ 1169 1170 static inline u64 drdtime(void) 1171 { 1172 int rID = 0; 1173 u64 val = 0; 1174 1175 __asm__ __volatile__( 1176 "rdtime.d %0, %1 \n\t" 1177 : "=r"(val), "=r"(rID) 1178 : 1179 ); 1180 return val; 1181 } 1182 1183 static inline unsigned int get_csr_cpuid(void) 1184 { 1185 return csr_read32(LOONGARCH_CSR_CPUID); 1186 } 1187 1188 static inline void csr_any_send(unsigned int addr, unsigned int data, 1189 unsigned int data_mask, unsigned int cpu) 1190 { 1191 uint64_t val = 0; 1192 1193 val = IOCSR_ANY_SEND_BLOCKING | addr; 1194 val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT); 1195 val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT); 1196 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT); 1197 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND); 1198 } 1199 1200 static inline unsigned int read_csr_excode(void) 1201 { 1202 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 1203 } 1204 1205 static inline void write_csr_index(unsigned int idx) 1206 { 1207 csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX); 1208 } 1209 1210 static inline unsigned int read_csr_pagesize(void) 1211 { 1212 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE; 1213 } 1214 1215 static inline void write_csr_pagesize(unsigned int size) 1216 { 1217 csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX); 1218 } 1219 1220 static inline unsigned int read_csr_tlbrefill_pagesize(void) 1221 { 1222 return (csr_read64(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT; 1223 } 1224 1225 static inline void write_csr_tlbrefill_pagesize(unsigned int size) 1226 { 1227 csr_xchg64(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI); 1228 } 1229 1230 #define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID) 1231 #define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID) 1232 #define read_csr_entryhi() csr_read64(LOONGARCH_CSR_TLBEHI) 1233 #define write_csr_entryhi(val) csr_write64(val, LOONGARCH_CSR_TLBEHI) 1234 #define read_csr_entrylo0() csr_read64(LOONGARCH_CSR_TLBELO0) 1235 #define write_csr_entrylo0(val) csr_write64(val, LOONGARCH_CSR_TLBELO0) 1236 #define read_csr_entrylo1() csr_read64(LOONGARCH_CSR_TLBELO1) 1237 #define write_csr_entrylo1(val) csr_write64(val, LOONGARCH_CSR_TLBELO1) 1238 #define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG) 1239 #define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG) 1240 #define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT) 1241 #define write_csr_estat(val) csr_write32(val, LOONGARCH_CSR_ESTAT) 1242 #define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX) 1243 #define write_csr_tlbidx(val) csr_write32(val, LOONGARCH_CSR_TLBIDX) 1244 #define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN) 1245 #define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN) 1246 #define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID) 1247 #define read_csr_prcfg1() csr_read64(LOONGARCH_CSR_PRCFG1) 1248 #define write_csr_prcfg1(val) csr_write64(val, LOONGARCH_CSR_PRCFG1) 1249 #define read_csr_prcfg2() csr_read64(LOONGARCH_CSR_PRCFG2) 1250 #define write_csr_prcfg2(val) csr_write64(val, LOONGARCH_CSR_PRCFG2) 1251 #define read_csr_prcfg3() csr_read64(LOONGARCH_CSR_PRCFG3) 1252 #define write_csr_prcfg3(val) csr_write64(val, LOONGARCH_CSR_PRCFG3) 1253 #define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE) 1254 #define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE) 1255 #define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG) 1256 #define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG) 1257 #define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR) 1258 #define read_csr_impctl1() csr_read64(LOONGARCH_CSR_IMPCTL1) 1259 #define write_csr_impctl1(val) csr_write64(val, LOONGARCH_CSR_IMPCTL1) 1260 #define write_csr_impctl2(val) csr_write64(val, LOONGARCH_CSR_IMPCTL2) 1261 1262 #define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0) 1263 #define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0) 1264 #define read_csr_perfctrl1() csr_read64(LOONGARCH_CSR_PERFCTRL1) 1265 #define read_csr_perfcntr1() csr_read64(LOONGARCH_CSR_PERFCNTR1) 1266 #define read_csr_perfctrl2() csr_read64(LOONGARCH_CSR_PERFCTRL2) 1267 #define read_csr_perfcntr2() csr_read64(LOONGARCH_CSR_PERFCNTR2) 1268 #define read_csr_perfctrl3() csr_read64(LOONGARCH_CSR_PERFCTRL3) 1269 #define read_csr_perfcntr3() csr_read64(LOONGARCH_CSR_PERFCNTR3) 1270 #define write_csr_perfctrl0(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL0) 1271 #define write_csr_perfcntr0(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR0) 1272 #define write_csr_perfctrl1(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL1) 1273 #define write_csr_perfcntr1(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR1) 1274 #define write_csr_perfctrl2(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL2) 1275 #define write_csr_perfcntr2(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR2) 1276 #define write_csr_perfctrl3(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL3) 1277 #define write_csr_perfcntr3(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR3) 1278 1279 /* 1280 * Manipulate bits in a register. 1281 */ 1282 #define __BUILD_CSR_COMMON(name) \ 1283 static inline unsigned long \ 1284 set_##name(unsigned long set) \ 1285 { \ 1286 unsigned long res, new; \ 1287 \ 1288 res = read_##name(); \ 1289 new = res | set; \ 1290 write_##name(new); \ 1291 \ 1292 return res; \ 1293 } \ 1294 \ 1295 static inline unsigned long \ 1296 clear_##name(unsigned long clear) \ 1297 { \ 1298 unsigned long res, new; \ 1299 \ 1300 res = read_##name(); \ 1301 new = res & ~clear; \ 1302 write_##name(new); \ 1303 \ 1304 return res; \ 1305 } \ 1306 \ 1307 static inline unsigned long \ 1308 change_##name(unsigned long change, unsigned long val) \ 1309 { \ 1310 unsigned long res, new; \ 1311 \ 1312 res = read_##name(); \ 1313 new = res & ~change; \ 1314 new |= (val & change); \ 1315 write_##name(new); \ 1316 \ 1317 return res; \ 1318 } 1319 1320 #define __BUILD_CSR_OP(name) __BUILD_CSR_COMMON(csr_##name) 1321 1322 __BUILD_CSR_OP(euen) 1323 __BUILD_CSR_OP(ecfg) 1324 __BUILD_CSR_OP(tlbidx) 1325 1326 #define set_csr_estat(val) \ 1327 csr_xchg32(val, val, LOONGARCH_CSR_ESTAT) 1328 #define clear_csr_estat(val) \ 1329 csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT) 1330 1331 #endif /* __ASSEMBLY__ */ 1332 1333 /* Generic EntryLo bit definitions */ 1334 #define ENTRYLO_V (_ULCAST_(1) << 0) 1335 #define ENTRYLO_D (_ULCAST_(1) << 1) 1336 #define ENTRYLO_PLV_SHIFT 2 1337 #define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT) 1338 #define ENTRYLO_C_SHIFT 4 1339 #define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT) 1340 #define ENTRYLO_G (_ULCAST_(1) << 6) 1341 #define ENTRYLO_NR (_ULCAST_(1) << 61) 1342 #define ENTRYLO_NX (_ULCAST_(1) << 62) 1343 1344 /* Values for PageSize register */ 1345 #define PS_4K 0x0000000c 1346 #define PS_8K 0x0000000d 1347 #define PS_16K 0x0000000e 1348 #define PS_32K 0x0000000f 1349 #define PS_64K 0x00000010 1350 #define PS_128K 0x00000011 1351 #define PS_256K 0x00000012 1352 #define PS_512K 0x00000013 1353 #define PS_1M 0x00000014 1354 #define PS_2M 0x00000015 1355 #define PS_4M 0x00000016 1356 #define PS_8M 0x00000017 1357 #define PS_16M 0x00000018 1358 #define PS_32M 0x00000019 1359 #define PS_64M 0x0000001a 1360 #define PS_128M 0x0000001b 1361 #define PS_256M 0x0000001c 1362 #define PS_512M 0x0000001d 1363 #define PS_1G 0x0000001e 1364 1365 /* Default page size for a given kernel configuration */ 1366 #ifdef CONFIG_PAGE_SIZE_4KB 1367 #define PS_DEFAULT_SIZE PS_4K 1368 #elif defined(CONFIG_PAGE_SIZE_16KB) 1369 #define PS_DEFAULT_SIZE PS_16K 1370 #elif defined(CONFIG_PAGE_SIZE_64KB) 1371 #define PS_DEFAULT_SIZE PS_64K 1372 #else 1373 #error Bad page size configuration! 1374 #endif 1375 1376 /* Default huge tlb size for a given kernel configuration */ 1377 #ifdef CONFIG_PAGE_SIZE_4KB 1378 #define PS_HUGE_SIZE PS_1M 1379 #elif defined(CONFIG_PAGE_SIZE_16KB) 1380 #define PS_HUGE_SIZE PS_16M 1381 #elif defined(CONFIG_PAGE_SIZE_64KB) 1382 #define PS_HUGE_SIZE PS_256M 1383 #else 1384 #error Bad page size configuration for hugetlbfs! 1385 #endif 1386 1387 /* ExStatus.ExcCode */ 1388 #define EXCCODE_RSV 0 /* Reserved */ 1389 #define EXCCODE_TLBL 1 /* TLB miss on a load */ 1390 #define EXCCODE_TLBS 2 /* TLB miss on a store */ 1391 #define EXCCODE_TLBI 3 /* TLB miss on a ifetch */ 1392 #define EXCCODE_TLBM 4 /* TLB modified fault */ 1393 #define EXCCODE_TLBNR 5 /* TLB Read-Inhibit exception */ 1394 #define EXCCODE_TLBNX 6 /* TLB Execution-Inhibit exception */ 1395 #define EXCCODE_TLBPE 7 /* TLB Privilege Error */ 1396 #define EXCCODE_ADE 8 /* Address Error */ 1397 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */ 1398 #define EXSUBCODE_ADEM 1 /* Access Memory*/ 1399 #define EXCCODE_ALE 9 /* Unalign Access */ 1400 #define EXCCODE_BCE 10 /* Bounds Check Error */ 1401 #define EXCCODE_SYS 11 /* System call */ 1402 #define EXCCODE_BP 12 /* Breakpoint */ 1403 #define EXCCODE_INE 13 /* Inst. Not Exist */ 1404 #define EXCCODE_IPE 14 /* Inst. Privileged Error */ 1405 #define EXCCODE_FPDIS 15 /* FPU Disabled */ 1406 #define EXCCODE_LSXDIS 16 /* LSX Disabled */ 1407 #define EXCCODE_LASXDIS 17 /* LASX Disabled */ 1408 #define EXCCODE_FPE 18 /* Floating Point Exception */ 1409 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */ 1410 #define EXCSUBCODE_VFPE 1 /* Vector Exception */ 1411 #define EXCCODE_WATCH 19 /* WatchPoint Exception */ 1412 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */ 1413 #define EXCSUBCODE_WPEM 1 /* ... on Memory Accesses */ 1414 #define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */ 1415 #define EXCCODE_BTE 21 /* Binary Trans. Exception */ 1416 #define EXCCODE_GSPR 22 /* Guest Privileged Error */ 1417 #define EXCCODE_HVC 23 /* Hypercall */ 1418 #define EXCCODE_GCM 24 /* Guest CSR modified */ 1419 #define EXCSUBCODE_GCSC 0 /* Software caused */ 1420 #define EXCSUBCODE_GCHC 1 /* Hardware caused */ 1421 #define EXCCODE_SE 25 /* Security */ 1422 1423 /* Interrupt numbers */ 1424 #define INT_SWI0 0 /* Software Interrupts */ 1425 #define INT_SWI1 1 1426 #define INT_HWI0 2 /* Hardware Interrupts */ 1427 #define INT_HWI1 3 1428 #define INT_HWI2 4 1429 #define INT_HWI3 5 1430 #define INT_HWI4 6 1431 #define INT_HWI5 7 1432 #define INT_HWI6 8 1433 #define INT_HWI7 9 1434 #define INT_PCOV 10 /* Performance Counter Overflow */ 1435 #define INT_TI 11 /* Timer */ 1436 #define INT_IPI 12 1437 #define INT_NMI 13 1438 1439 /* ExcCodes corresponding to interrupts */ 1440 #define EXCCODE_INT_NUM (INT_NMI + 1) 1441 #define EXCCODE_INT_START 64 1442 #define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1) 1443 1444 /* FPU register names */ 1445 #define LOONGARCH_FCSR0 $r0 1446 #define LOONGARCH_FCSR1 $r1 1447 #define LOONGARCH_FCSR2 $r2 1448 #define LOONGARCH_FCSR3 $r3 1449 1450 /* FPU Status Register Values */ 1451 #define FPU_CSR_RSVD 0xe0e0fce0 1452 1453 /* 1454 * X the exception cause indicator 1455 * E the exception enable 1456 * S the sticky/flag bit 1457 */ 1458 #define FPU_CSR_ALL_X 0x1f000000 1459 #define FPU_CSR_INV_X 0x10000000 1460 #define FPU_CSR_DIV_X 0x08000000 1461 #define FPU_CSR_OVF_X 0x04000000 1462 #define FPU_CSR_UDF_X 0x02000000 1463 #define FPU_CSR_INE_X 0x01000000 1464 1465 #define FPU_CSR_ALL_S 0x001f0000 1466 #define FPU_CSR_INV_S 0x00100000 1467 #define FPU_CSR_DIV_S 0x00080000 1468 #define FPU_CSR_OVF_S 0x00040000 1469 #define FPU_CSR_UDF_S 0x00020000 1470 #define FPU_CSR_INE_S 0x00010000 1471 1472 #define FPU_CSR_ALL_E 0x0000001f 1473 #define FPU_CSR_INV_E 0x00000010 1474 #define FPU_CSR_DIV_E 0x00000008 1475 #define FPU_CSR_OVF_E 0x00000004 1476 #define FPU_CSR_UDF_E 0x00000002 1477 #define FPU_CSR_INE_E 0x00000001 1478 1479 /* Bits 8 and 9 of FPU Status Register specify the rounding mode */ 1480 #define FPU_CSR_RM 0x300 1481 #define FPU_CSR_RN 0x000 /* nearest */ 1482 #define FPU_CSR_RZ 0x100 /* towards zero */ 1483 #define FPU_CSR_RU 0x200 /* towards +Infinity */ 1484 #define FPU_CSR_RD 0x300 /* towards -Infinity */ 1485 1486 #define read_fcsr(source) \ 1487 ({ \ 1488 unsigned int __res; \ 1489 \ 1490 __asm__ __volatile__( \ 1491 " movfcsr2gr %0, "__stringify(source)" \n" \ 1492 : "=r" (__res)); \ 1493 __res; \ 1494 }) 1495 1496 #define write_fcsr(dest, val) \ 1497 do { \ 1498 __asm__ __volatile__( \ 1499 " movgr2fcsr %0, "__stringify(dest)" \n" \ 1500 : : "r" (val)); \ 1501 } while (0) 1502 1503 #endif /* _ASM_LOONGARCH_H */ 1504