1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_LOONGARCH_H 6 #define _ASM_LOONGARCH_H 7 8 #include <linux/bits.h> 9 #include <linux/linkage.h> 10 #include <linux/types.h> 11 12 #ifndef __ASSEMBLY__ 13 #include <larchintrin.h> 14 15 /* 16 * parse_r var, r - Helper assembler macro for parsing register names. 17 * 18 * This converts the register name in $n form provided in \r to the 19 * corresponding register number, which is assigned to the variable \var. It is 20 * needed to allow explicit encoding of instructions in inline assembly where 21 * registers are chosen by the compiler in $n form, allowing us to avoid using 22 * fixed register numbers. 23 * 24 * It also allows newer instructions (not implemented by the assembler) to be 25 * transparently implemented using assembler macros, instead of needing separate 26 * cases depending on toolchain support. 27 * 28 * Simple usage example: 29 * __asm__ __volatile__("parse_r addr, %0\n\t" 30 * "#invtlb op, 0, %0\n\t" 31 * ".word ((0x6498000) | (addr << 10) | (0 << 5) | op)" 32 * : "=r" (status); 33 */ 34 35 /* Match an individual register number and assign to \var */ 36 #define _IFC_REG(n) \ 37 ".ifc \\r, $r" #n "\n\t" \ 38 "\\var = " #n "\n\t" \ 39 ".endif\n\t" 40 41 __asm__(".macro parse_r var r\n\t" 42 "\\var = -1\n\t" 43 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) 44 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) 45 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) 46 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) 47 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) 48 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) 49 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) 50 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) 51 ".iflt \\var\n\t" 52 ".error \"Unable to parse register name \\r\"\n\t" 53 ".endif\n\t" 54 ".endm"); 55 56 #undef _IFC_REG 57 58 /* CPUCFG */ 59 #define read_cpucfg(reg) __cpucfg(reg) 60 61 #endif /* !__ASSEMBLY__ */ 62 63 #ifdef __ASSEMBLY__ 64 65 /* LoongArch Registers */ 66 #define REG_ZERO 0x0 67 #define REG_RA 0x1 68 #define REG_TP 0x2 69 #define REG_SP 0x3 70 #define REG_A0 0x4 /* Reused as V0 for return value */ 71 #define REG_A1 0x5 /* Reused as V1 for return value */ 72 #define REG_A2 0x6 73 #define REG_A3 0x7 74 #define REG_A4 0x8 75 #define REG_A5 0x9 76 #define REG_A6 0xa 77 #define REG_A7 0xb 78 #define REG_T0 0xc 79 #define REG_T1 0xd 80 #define REG_T2 0xe 81 #define REG_T3 0xf 82 #define REG_T4 0x10 83 #define REG_T5 0x11 84 #define REG_T6 0x12 85 #define REG_T7 0x13 86 #define REG_T8 0x14 87 #define REG_U0 0x15 /* Kernel uses it as percpu base */ 88 #define REG_FP 0x16 89 #define REG_S0 0x17 90 #define REG_S1 0x18 91 #define REG_S2 0x19 92 #define REG_S3 0x1a 93 #define REG_S4 0x1b 94 #define REG_S5 0x1c 95 #define REG_S6 0x1d 96 #define REG_S7 0x1e 97 #define REG_S8 0x1f 98 99 #endif /* __ASSEMBLY__ */ 100 101 /* Bit fields for CPUCFG registers */ 102 #define LOONGARCH_CPUCFG0 0x0 103 #define CPUCFG0_PRID GENMASK(31, 0) 104 105 #define LOONGARCH_CPUCFG1 0x1 106 #define CPUCFG1_ISGR32 BIT(0) 107 #define CPUCFG1_ISGR64 BIT(1) 108 #define CPUCFG1_PAGING BIT(2) 109 #define CPUCFG1_IOCSR BIT(3) 110 #define CPUCFG1_PABITS GENMASK(11, 4) 111 #define CPUCFG1_VABITS GENMASK(19, 12) 112 #define CPUCFG1_UAL BIT(20) 113 #define CPUCFG1_RI BIT(21) 114 #define CPUCFG1_EP BIT(22) 115 #define CPUCFG1_RPLV BIT(23) 116 #define CPUCFG1_HUGEPG BIT(24) 117 #define CPUCFG1_CRC32 BIT(25) 118 #define CPUCFG1_MSGINT BIT(26) 119 120 #define LOONGARCH_CPUCFG2 0x2 121 #define CPUCFG2_FP BIT(0) 122 #define CPUCFG2_FPSP BIT(1) 123 #define CPUCFG2_FPDP BIT(2) 124 #define CPUCFG2_FPVERS GENMASK(5, 3) 125 #define CPUCFG2_LSX BIT(6) 126 #define CPUCFG2_LASX BIT(7) 127 #define CPUCFG2_COMPLEX BIT(8) 128 #define CPUCFG2_CRYPTO BIT(9) 129 #define CPUCFG2_LVZP BIT(10) 130 #define CPUCFG2_LVZVER GENMASK(13, 11) 131 #define CPUCFG2_LLFTP BIT(14) 132 #define CPUCFG2_LLFTPREV GENMASK(17, 15) 133 #define CPUCFG2_X86BT BIT(18) 134 #define CPUCFG2_ARMBT BIT(19) 135 #define CPUCFG2_MIPSBT BIT(20) 136 #define CPUCFG2_LSPW BIT(21) 137 #define CPUCFG2_LAM BIT(22) 138 #define CPUCFG2_PTW BIT(24) 139 140 #define LOONGARCH_CPUCFG3 0x3 141 #define CPUCFG3_CCDMA BIT(0) 142 #define CPUCFG3_SFB BIT(1) 143 #define CPUCFG3_UCACC BIT(2) 144 #define CPUCFG3_LLEXC BIT(3) 145 #define CPUCFG3_SCDLY BIT(4) 146 #define CPUCFG3_LLDBAR BIT(5) 147 #define CPUCFG3_ITLBT BIT(6) 148 #define CPUCFG3_ICACHET BIT(7) 149 #define CPUCFG3_SPW_LVL GENMASK(10, 8) 150 #define CPUCFG3_SPW_HG_HF BIT(11) 151 #define CPUCFG3_RVA BIT(12) 152 #define CPUCFG3_RVAMAX GENMASK(16, 13) 153 154 #define LOONGARCH_CPUCFG4 0x4 155 #define CPUCFG4_CCFREQ GENMASK(31, 0) 156 157 #define LOONGARCH_CPUCFG5 0x5 158 #define CPUCFG5_CCMUL GENMASK(15, 0) 159 #define CPUCFG5_CCDIV GENMASK(31, 16) 160 161 #define LOONGARCH_CPUCFG6 0x6 162 #define CPUCFG6_PMP BIT(0) 163 #define CPUCFG6_PAMVER GENMASK(3, 1) 164 #define CPUCFG6_PMNUM GENMASK(7, 4) 165 #define CPUCFG6_PMBITS GENMASK(13, 8) 166 #define CPUCFG6_UPM BIT(14) 167 168 #define LOONGARCH_CPUCFG16 0x10 169 #define CPUCFG16_L1_IUPRE BIT(0) 170 #define CPUCFG16_L1_IUUNIFY BIT(1) 171 #define CPUCFG16_L1_DPRE BIT(2) 172 #define CPUCFG16_L2_IUPRE BIT(3) 173 #define CPUCFG16_L2_IUUNIFY BIT(4) 174 #define CPUCFG16_L2_IUPRIV BIT(5) 175 #define CPUCFG16_L2_IUINCL BIT(6) 176 #define CPUCFG16_L2_DPRE BIT(7) 177 #define CPUCFG16_L2_DPRIV BIT(8) 178 #define CPUCFG16_L2_DINCL BIT(9) 179 #define CPUCFG16_L3_IUPRE BIT(10) 180 #define CPUCFG16_L3_IUUNIFY BIT(11) 181 #define CPUCFG16_L3_IUPRIV BIT(12) 182 #define CPUCFG16_L3_IUINCL BIT(13) 183 #define CPUCFG16_L3_DPRE BIT(14) 184 #define CPUCFG16_L3_DPRIV BIT(15) 185 #define CPUCFG16_L3_DINCL BIT(16) 186 187 #define LOONGARCH_CPUCFG17 0x11 188 #define LOONGARCH_CPUCFG18 0x12 189 #define LOONGARCH_CPUCFG19 0x13 190 #define LOONGARCH_CPUCFG20 0x14 191 #define CPUCFG_CACHE_WAYS_M GENMASK(15, 0) 192 #define CPUCFG_CACHE_SETS_M GENMASK(23, 16) 193 #define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24) 194 #define CPUCFG_CACHE_WAYS 0 195 #define CPUCFG_CACHE_SETS 16 196 #define CPUCFG_CACHE_LSIZE 24 197 198 #define LOONGARCH_CPUCFG48 0x30 199 #define CPUCFG48_MCSR_LCK BIT(0) 200 #define CPUCFG48_NAP_EN BIT(1) 201 #define CPUCFG48_VFPU_CG BIT(2) 202 #define CPUCFG48_RAM_CG BIT(3) 203 204 #ifndef __ASSEMBLY__ 205 206 /* CSR */ 207 #define csr_read32(reg) __csrrd_w(reg) 208 #define csr_read64(reg) __csrrd_d(reg) 209 #define csr_write32(val, reg) __csrwr_w(val, reg) 210 #define csr_write64(val, reg) __csrwr_d(val, reg) 211 #define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg) 212 #define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg) 213 214 /* IOCSR */ 215 #define iocsr_read32(reg) __iocsrrd_w(reg) 216 #define iocsr_read64(reg) __iocsrrd_d(reg) 217 #define iocsr_write32(val, reg) __iocsrwr_w(val, reg) 218 #define iocsr_write64(val, reg) __iocsrwr_d(val, reg) 219 220 #endif /* !__ASSEMBLY__ */ 221 222 /* CSR register number */ 223 224 /* Basic CSR registers */ 225 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 226 #define CSR_CRMD_WE_SHIFT 9 227 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT) 228 #define CSR_CRMD_DACM_SHIFT 7 229 #define CSR_CRMD_DACM_WIDTH 2 230 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT) 231 #define CSR_CRMD_DACF_SHIFT 5 232 #define CSR_CRMD_DACF_WIDTH 2 233 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT) 234 #define CSR_CRMD_PG_SHIFT 4 235 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT) 236 #define CSR_CRMD_DA_SHIFT 3 237 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT) 238 #define CSR_CRMD_IE_SHIFT 2 239 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT) 240 #define CSR_CRMD_PLV_SHIFT 0 241 #define CSR_CRMD_PLV_WIDTH 2 242 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT) 243 244 #define PLV_KERN 0 245 #define PLV_USER 3 246 #define PLV_MASK 0x3 247 248 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 249 #define CSR_PRMD_PWE_SHIFT 3 250 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT) 251 #define CSR_PRMD_PIE_SHIFT 2 252 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT) 253 #define CSR_PRMD_PPLV_SHIFT 0 254 #define CSR_PRMD_PPLV_WIDTH 2 255 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT) 256 257 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */ 258 #define CSR_EUEN_LBTEN_SHIFT 3 259 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT) 260 #define CSR_EUEN_LASXEN_SHIFT 2 261 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT) 262 #define CSR_EUEN_LSXEN_SHIFT 1 263 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT) 264 #define CSR_EUEN_FPEN_SHIFT 0 265 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT) 266 267 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */ 268 269 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ 270 #define CSR_ECFG_VS_SHIFT 16 271 #define CSR_ECFG_VS_WIDTH 3 272 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT) 273 #define CSR_ECFG_IM_SHIFT 0 274 #define CSR_ECFG_IM_WIDTH 14 275 #define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT) 276 277 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 278 #define CSR_ESTAT_ESUBCODE_SHIFT 22 279 #define CSR_ESTAT_ESUBCODE_WIDTH 9 280 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT) 281 #define CSR_ESTAT_EXC_SHIFT 16 282 #define CSR_ESTAT_EXC_WIDTH 6 283 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT) 284 #define CSR_ESTAT_IS_SHIFT 0 285 #define CSR_ESTAT_IS_WIDTH 14 286 #define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT) 287 288 #define LOONGARCH_CSR_ERA 0x6 /* ERA */ 289 290 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 291 292 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */ 293 294 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */ 295 296 /* TLB related CSR registers */ 297 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */ 298 #define CSR_TLBIDX_EHINV_SHIFT 31 299 #define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT) 300 #define CSR_TLBIDX_PS_SHIFT 24 301 #define CSR_TLBIDX_PS_WIDTH 6 302 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT) 303 #define CSR_TLBIDX_IDX_SHIFT 0 304 #define CSR_TLBIDX_IDX_WIDTH 12 305 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT) 306 #define CSR_TLBIDX_SIZEM 0x3f000000 307 #define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT 308 #define CSR_TLBIDX_IDXM 0xfff 309 #define CSR_INVALID_ENTRY(e) (CSR_TLBIDX_EHINV | e) 310 311 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ 312 313 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ 314 #define CSR_TLBLO0_RPLV_SHIFT 63 315 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT) 316 #define CSR_TLBLO0_NX_SHIFT 62 317 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT) 318 #define CSR_TLBLO0_NR_SHIFT 61 319 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT) 320 #define CSR_TLBLO0_PFN_SHIFT 12 321 #define CSR_TLBLO0_PFN_WIDTH 36 322 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT) 323 #define CSR_TLBLO0_GLOBAL_SHIFT 6 324 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT) 325 #define CSR_TLBLO0_CCA_SHIFT 4 326 #define CSR_TLBLO0_CCA_WIDTH 2 327 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT) 328 #define CSR_TLBLO0_PLV_SHIFT 2 329 #define CSR_TLBLO0_PLV_WIDTH 2 330 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT) 331 #define CSR_TLBLO0_WE_SHIFT 1 332 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT) 333 #define CSR_TLBLO0_V_SHIFT 0 334 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT) 335 336 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ 337 #define CSR_TLBLO1_RPLV_SHIFT 63 338 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT) 339 #define CSR_TLBLO1_NX_SHIFT 62 340 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT) 341 #define CSR_TLBLO1_NR_SHIFT 61 342 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT) 343 #define CSR_TLBLO1_PFN_SHIFT 12 344 #define CSR_TLBLO1_PFN_WIDTH 36 345 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT) 346 #define CSR_TLBLO1_GLOBAL_SHIFT 6 347 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT) 348 #define CSR_TLBLO1_CCA_SHIFT 4 349 #define CSR_TLBLO1_CCA_WIDTH 2 350 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT) 351 #define CSR_TLBLO1_PLV_SHIFT 2 352 #define CSR_TLBLO1_PLV_WIDTH 2 353 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT) 354 #define CSR_TLBLO1_WE_SHIFT 1 355 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT) 356 #define CSR_TLBLO1_V_SHIFT 0 357 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT) 358 359 #define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */ 360 #define CSR_GTLBC_RID_SHIFT 16 361 #define CSR_GTLBC_RID_WIDTH 8 362 #define CSR_GTLBC_RID (_ULCAST_(0xff) << CSR_GTLBC_RID_SHIFT) 363 #define CSR_GTLBC_TOTI_SHIFT 13 364 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT) 365 #define CSR_GTLBC_USERID_SHIFT 12 366 #define CSR_GTLBC_USERID (_ULCAST_(0x1) << CSR_GTLBC_USERID_SHIFT) 367 #define CSR_GTLBC_GMTLBSZ_SHIFT 0 368 #define CSR_GTLBC_GMTLBSZ_WIDTH 6 369 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT) 370 371 #define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */ 372 #define CSR_TRGP_RID_SHIFT 16 373 #define CSR_TRGP_RID_WIDTH 8 374 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT) 375 #define CSR_TRGP_GTLB_SHIFT 0 376 #define CSR_TRGP_GTLB (1 << CSR_TRGP_GTLB_SHIFT) 377 378 #define LOONGARCH_CSR_ASID 0x18 /* ASID */ 379 #define CSR_ASID_BIT_SHIFT 16 /* ASIDBits */ 380 #define CSR_ASID_BIT_WIDTH 8 381 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT) 382 #define CSR_ASID_ASID_SHIFT 0 383 #define CSR_ASID_ASID_WIDTH 10 384 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT) 385 386 #define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */ 387 388 #define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */ 389 390 #define LOONGARCH_CSR_PGD 0x1b /* Page table base */ 391 392 #define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */ 393 #define CSR_PWCTL0_PTEW_SHIFT 30 394 #define CSR_PWCTL0_PTEW_WIDTH 2 395 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT) 396 #define CSR_PWCTL0_DIR1WIDTH_SHIFT 25 397 #define CSR_PWCTL0_DIR1WIDTH_WIDTH 5 398 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT) 399 #define CSR_PWCTL0_DIR1BASE_SHIFT 20 400 #define CSR_PWCTL0_DIR1BASE_WIDTH 5 401 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT) 402 #define CSR_PWCTL0_DIR0WIDTH_SHIFT 15 403 #define CSR_PWCTL0_DIR0WIDTH_WIDTH 5 404 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT) 405 #define CSR_PWCTL0_DIR0BASE_SHIFT 10 406 #define CSR_PWCTL0_DIR0BASE_WIDTH 5 407 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT) 408 #define CSR_PWCTL0_PTWIDTH_SHIFT 5 409 #define CSR_PWCTL0_PTWIDTH_WIDTH 5 410 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT) 411 #define CSR_PWCTL0_PTBASE_SHIFT 0 412 #define CSR_PWCTL0_PTBASE_WIDTH 5 413 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT) 414 415 #define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */ 416 #define CSR_PWCTL1_PTW_SHIFT 24 417 #define CSR_PWCTL1_PTW_WIDTH 1 418 #define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT) 419 #define CSR_PWCTL1_DIR3WIDTH_SHIFT 18 420 #define CSR_PWCTL1_DIR3WIDTH_WIDTH 5 421 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT) 422 #define CSR_PWCTL1_DIR3BASE_SHIFT 12 423 #define CSR_PWCTL1_DIR3BASE_WIDTH 5 424 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT) 425 #define CSR_PWCTL1_DIR2WIDTH_SHIFT 6 426 #define CSR_PWCTL1_DIR2WIDTH_WIDTH 5 427 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT) 428 #define CSR_PWCTL1_DIR2BASE_SHIFT 0 429 #define CSR_PWCTL1_DIR2BASE_WIDTH 5 430 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT) 431 432 #define LOONGARCH_CSR_STLBPGSIZE 0x1e 433 #define CSR_STLBPGSIZE_PS_WIDTH 6 434 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f)) 435 436 #define LOONGARCH_CSR_RVACFG 0x1f 437 #define CSR_RVACFG_RDVA_WIDTH 4 438 #define CSR_RVACFG_RDVA (_ULCAST_(0xf)) 439 440 /* Config CSR registers */ 441 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */ 442 #define CSR_CPUID_COREID_WIDTH 9 443 #define CSR_CPUID_COREID _ULCAST_(0x1ff) 444 445 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */ 446 #define CSR_CONF1_VSMAX_SHIFT 12 447 #define CSR_CONF1_VSMAX_WIDTH 3 448 #define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT) 449 #define CSR_CONF1_TMRBITS_SHIFT 4 450 #define CSR_CONF1_TMRBITS_WIDTH 8 451 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT) 452 #define CSR_CONF1_KSNUM_WIDTH 4 453 #define CSR_CONF1_KSNUM _ULCAST_(0xf) 454 455 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */ 456 #define CSR_CONF2_PGMASK_SUPP 0x3ffff000 457 458 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */ 459 #define CSR_CONF3_STLBIDX_SHIFT 20 460 #define CSR_CONF3_STLBIDX_WIDTH 6 461 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT) 462 #define CSR_CONF3_STLBWAYS_SHIFT 12 463 #define CSR_CONF3_STLBWAYS_WIDTH 8 464 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT) 465 #define CSR_CONF3_MTLBSIZE_SHIFT 4 466 #define CSR_CONF3_MTLBSIZE_WIDTH 8 467 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT) 468 #define CSR_CONF3_TLBTYPE_SHIFT 0 469 #define CSR_CONF3_TLBTYPE_WIDTH 4 470 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT) 471 472 /* KSave registers */ 473 #define LOONGARCH_CSR_KS0 0x30 474 #define LOONGARCH_CSR_KS1 0x31 475 #define LOONGARCH_CSR_KS2 0x32 476 #define LOONGARCH_CSR_KS3 0x33 477 #define LOONGARCH_CSR_KS4 0x34 478 #define LOONGARCH_CSR_KS5 0x35 479 #define LOONGARCH_CSR_KS6 0x36 480 #define LOONGARCH_CSR_KS7 0x37 481 #define LOONGARCH_CSR_KS8 0x38 482 483 /* Exception allocated KS0, KS1 and KS2 statically */ 484 #define EXCEPTION_KS0 LOONGARCH_CSR_KS0 485 #define EXCEPTION_KS1 LOONGARCH_CSR_KS1 486 #define EXCEPTION_KS2 LOONGARCH_CSR_KS2 487 #define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2) 488 489 /* Percpu-data base allocated KS3 statically */ 490 #define PERCPU_BASE_KS LOONGARCH_CSR_KS3 491 #define PERCPU_KSAVE_MASK (1 << 3) 492 493 /* KVM allocated KS4 and KS5 statically */ 494 #define KVM_VCPU_KS LOONGARCH_CSR_KS4 495 #define KVM_TEMP_KS LOONGARCH_CSR_KS5 496 #define KVM_KSAVE_MASK (1 << 4 | 1 << 5) 497 498 /* Timer registers */ 499 #define LOONGARCH_CSR_TMID 0x40 /* Timer ID */ 500 501 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ 502 #define CSR_TCFG_VAL_SHIFT 2 503 #define CSR_TCFG_VAL_WIDTH 48 504 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT) 505 #define CSR_TCFG_PERIOD_SHIFT 1 506 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT) 507 #define CSR_TCFG_EN (_ULCAST_(0x1)) 508 509 #define LOONGARCH_CSR_TVAL 0x42 /* Timer value */ 510 511 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */ 512 513 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */ 514 #define CSR_TINTCLR_TI_SHIFT 0 515 #define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT) 516 517 /* Guest registers */ 518 #define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */ 519 #define CSR_GSTAT_GID_SHIFT 16 520 #define CSR_GSTAT_GID_WIDTH 8 521 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT) 522 #define CSR_GSTAT_GIDBIT_SHIFT 4 523 #define CSR_GSTAT_GIDBIT_WIDTH 6 524 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT) 525 #define CSR_GSTAT_PVM_SHIFT 1 526 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT) 527 #define CSR_GSTAT_VM_SHIFT 0 528 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT) 529 530 #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ 531 #define CSR_GCFG_GPERF_SHIFT 24 532 #define CSR_GCFG_GPERF_WIDTH 3 533 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) 534 #define CSR_GCFG_GCI_SHIFT 20 535 #define CSR_GCFG_GCI_WIDTH 2 536 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) 537 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) 538 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) 539 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) 540 #define CSR_GCFG_GCIP_SHIFT 16 541 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) 542 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) 543 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) 544 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) 545 #define CSR_GCFG_TORU_SHIFT 15 546 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) 547 #define CSR_GCFG_TORUP_SHIFT 14 548 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) 549 #define CSR_GCFG_TOP_SHIFT 13 550 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) 551 #define CSR_GCFG_TOPP_SHIFT 12 552 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) 553 #define CSR_GCFG_TOE_SHIFT 11 554 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) 555 #define CSR_GCFG_TOEP_SHIFT 10 556 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) 557 #define CSR_GCFG_TIT_SHIFT 9 558 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) 559 #define CSR_GCFG_TITP_SHIFT 8 560 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) 561 #define CSR_GCFG_SIT_SHIFT 7 562 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) 563 #define CSR_GCFG_SITP_SHIFT 6 564 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) 565 #define CSR_GCFG_MATC_SHITF 4 566 #define CSR_GCFG_MATC_WIDTH 2 567 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) 568 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) 569 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) 570 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) 571 572 #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ 573 #define CSR_GINTC_HC_SHIFT 16 574 #define CSR_GINTC_HC_WIDTH 8 575 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT) 576 #define CSR_GINTC_PIP_SHIFT 8 577 #define CSR_GINTC_PIP_WIDTH 8 578 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT) 579 #define CSR_GINTC_VIP_SHIFT 0 580 #define CSR_GINTC_VIP_WIDTH 8 581 #define CSR_GINTC_VIP (_ULCAST_(0xff)) 582 583 #define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */ 584 585 /* LLBCTL register */ 586 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */ 587 #define CSR_LLBCTL_ROLLB_SHIFT 0 588 #define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT) 589 #define CSR_LLBCTL_WCLLB_SHIFT 1 590 #define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT) 591 #define CSR_LLBCTL_KLO_SHIFT 2 592 #define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT) 593 594 /* Implement dependent */ 595 #define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */ 596 #define CSR_MISPEC_SHIFT 20 597 #define CSR_MISPEC_WIDTH 8 598 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT) 599 #define CSR_SSEN_SHIFT 18 600 #define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT) 601 #define CSR_SCRAND_SHIFT 17 602 #define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT) 603 #define CSR_LLEXCL_SHIFT 16 604 #define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT) 605 #define CSR_DISVC_SHIFT 15 606 #define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT) 607 #define CSR_VCLRU_SHIFT 14 608 #define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT) 609 #define CSR_DCLRU_SHIFT 13 610 #define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT) 611 #define CSR_FASTLDQ_SHIFT 12 612 #define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT) 613 #define CSR_USERCAC_SHIFT 11 614 #define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT) 615 #define CSR_ANTI_MISPEC_SHIFT 10 616 #define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT) 617 #define CSR_AUTO_FLUSHSFB_SHIFT 9 618 #define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT) 619 #define CSR_STFILL_SHIFT 8 620 #define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT) 621 #define CSR_LIFEP_SHIFT 7 622 #define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT) 623 #define CSR_LLSYNC_SHIFT 6 624 #define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT) 625 #define CSR_BRBTDIS_SHIFT 5 626 #define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT) 627 #define CSR_RASDIS_SHIFT 4 628 #define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT) 629 #define CSR_STPRE_SHIFT 2 630 #define CSR_STPRE_WIDTH 2 631 #define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT) 632 #define CSR_INSTPRE_SHIFT 1 633 #define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT) 634 #define CSR_DATAPRE_SHIFT 0 635 #define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT) 636 637 #define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */ 638 #define CSR_FLUSH_MTLB_SHIFT 0 639 #define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT) 640 #define CSR_FLUSH_STLB_SHIFT 1 641 #define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT) 642 #define CSR_FLUSH_DTLB_SHIFT 2 643 #define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT) 644 #define CSR_FLUSH_ITLB_SHIFT 3 645 #define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT) 646 #define CSR_FLUSH_BTAC_SHIFT 4 647 #define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT) 648 649 #define LOONGARCH_CSR_GNMI 0x82 650 651 /* TLB Refill registers */ 652 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */ 653 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */ 654 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */ 655 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */ 656 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */ 657 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ 658 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ 659 #define CSR_TLBREHI_PS_SHIFT 0 660 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT) 661 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ 662 663 /* Machine Error registers */ 664 #define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */ 665 #define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */ 666 #define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */ 667 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */ 668 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */ 669 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */ 670 671 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ 672 673 #define LOONGARCH_CSR_PRID 0xc0 674 675 /* Shadow MCSR : 0xc0 ~ 0xff */ 676 #define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */ 677 #define MCSR0_INT_IMPL_SHIFT 58 678 #define MCSR0_INT_IMPL 0 679 #define MCSR0_IOCSR_BRD_SHIFT 57 680 #define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT) 681 #define MCSR0_HUGEPG_SHIFT 56 682 #define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT) 683 #define MCSR0_RPLMTLB_SHIFT 55 684 #define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT) 685 #define MCSR0_EP_SHIFT 54 686 #define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT) 687 #define MCSR0_RI_SHIFT 53 688 #define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT) 689 #define MCSR0_UAL_SHIFT 52 690 #define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT) 691 #define MCSR0_VABIT_SHIFT 44 692 #define MCSR0_VABIT_WIDTH 8 693 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT) 694 #define VABIT_DEFAULT 0x2f 695 #define MCSR0_PABIT_SHIFT 36 696 #define MCSR0_PABIT_WIDTH 8 697 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT) 698 #define PABIT_DEFAULT 0x2f 699 #define MCSR0_IOCSR_SHIFT 35 700 #define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT) 701 #define MCSR0_PAGING_SHIFT 34 702 #define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT) 703 #define MCSR0_GR64_SHIFT 33 704 #define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT) 705 #define GR64_DEFAULT 1 706 #define MCSR0_GR32_SHIFT 32 707 #define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT) 708 #define GR32_DEFAULT 0 709 #define MCSR0_PRID_WIDTH 32 710 #define MCSR0_PRID 0x14C010 711 712 #define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */ 713 #define MCSR1_HPFOLD_SHIFT 43 714 #define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT) 715 #define MCSR1_SPW_LVL_SHIFT 40 716 #define MCSR1_SPW_LVL_WIDTH 3 717 #define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT) 718 #define MCSR1_ICACHET_SHIFT 39 719 #define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT) 720 #define MCSR1_ITLBT_SHIFT 38 721 #define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT) 722 #define MCSR1_LLDBAR_SHIFT 37 723 #define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT) 724 #define MCSR1_SCDLY_SHIFT 36 725 #define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT) 726 #define MCSR1_LLEXC_SHIFT 35 727 #define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT) 728 #define MCSR1_UCACC_SHIFT 34 729 #define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT) 730 #define MCSR1_SFB_SHIFT 33 731 #define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT) 732 #define MCSR1_CCDMA_SHIFT 32 733 #define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT) 734 #define MCSR1_LAMO_SHIFT 22 735 #define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT) 736 #define MCSR1_LSPW_SHIFT 21 737 #define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT) 738 #define MCSR1_MIPSBT_SHIFT 20 739 #define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT) 740 #define MCSR1_ARMBT_SHIFT 19 741 #define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT) 742 #define MCSR1_X86BT_SHIFT 18 743 #define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT) 744 #define MCSR1_LLFTPVERS_SHIFT 15 745 #define MCSR1_LLFTPVERS_WIDTH 3 746 #define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT) 747 #define MCSR1_LLFTP_SHIFT 14 748 #define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT) 749 #define MCSR1_VZVERS_SHIFT 11 750 #define MCSR1_VZVERS_WIDTH 3 751 #define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT) 752 #define MCSR1_VZ_SHIFT 10 753 #define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT) 754 #define MCSR1_CRYPTO_SHIFT 9 755 #define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT) 756 #define MCSR1_COMPLEX_SHIFT 8 757 #define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT) 758 #define MCSR1_LASX_SHIFT 7 759 #define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT) 760 #define MCSR1_LSX_SHIFT 6 761 #define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT) 762 #define MCSR1_FPVERS_SHIFT 3 763 #define MCSR1_FPVERS_WIDTH 3 764 #define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT) 765 #define MCSR1_FPDP_SHIFT 2 766 #define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT) 767 #define MCSR1_FPSP_SHIFT 1 768 #define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT) 769 #define MCSR1_FP_SHIFT 0 770 #define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT) 771 772 #define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */ 773 #define MCSR2_CCDIV_SHIFT 48 774 #define MCSR2_CCDIV_WIDTH 16 775 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT) 776 #define MCSR2_CCMUL_SHIFT 32 777 #define MCSR2_CCMUL_WIDTH 16 778 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT) 779 #define MCSR2_CCFREQ_WIDTH 32 780 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff)) 781 #define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */ 782 783 #define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */ 784 #define MCSR3_UPM_SHIFT 14 785 #define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT) 786 #define MCSR3_PMBITS_SHIFT 8 787 #define MCSR3_PMBITS_WIDTH 6 788 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT) 789 #define PMBITS_DEFAULT 0x40 790 #define MCSR3_PMNUM_SHIFT 4 791 #define MCSR3_PMNUM_WIDTH 4 792 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT) 793 #define MCSR3_PAMVER_SHIFT 1 794 #define MCSR3_PAMVER_WIDTH 3 795 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT) 796 #define MCSR3_PMP_SHIFT 0 797 #define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT) 798 799 #define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */ 800 #define MCSR8_L1I_SIZE_SHIFT 56 801 #define MCSR8_L1I_SIZE_WIDTH 7 802 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT) 803 #define MCSR8_L1I_IDX_SHIFT 48 804 #define MCSR8_L1I_IDX_WIDTH 8 805 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT) 806 #define MCSR8_L1I_WAY_SHIFT 32 807 #define MCSR8_L1I_WAY_WIDTH 16 808 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT) 809 #define MCSR8_L3DINCL_SHIFT 16 810 #define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT) 811 #define MCSR8_L3DPRIV_SHIFT 15 812 #define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT) 813 #define MCSR8_L3DPRE_SHIFT 14 814 #define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT) 815 #define MCSR8_L3IUINCL_SHIFT 13 816 #define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT) 817 #define MCSR8_L3IUPRIV_SHIFT 12 818 #define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT) 819 #define MCSR8_L3IUUNIFY_SHIFT 11 820 #define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT) 821 #define MCSR8_L3IUPRE_SHIFT 10 822 #define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT) 823 #define MCSR8_L2DINCL_SHIFT 9 824 #define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT) 825 #define MCSR8_L2DPRIV_SHIFT 8 826 #define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT) 827 #define MCSR8_L2DPRE_SHIFT 7 828 #define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT) 829 #define MCSR8_L2IUINCL_SHIFT 6 830 #define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT) 831 #define MCSR8_L2IUPRIV_SHIFT 5 832 #define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT) 833 #define MCSR8_L2IUUNIFY_SHIFT 4 834 #define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT) 835 #define MCSR8_L2IUPRE_SHIFT 3 836 #define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT) 837 #define MCSR8_L1DPRE_SHIFT 2 838 #define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT) 839 #define MCSR8_L1IUUNIFY_SHIFT 1 840 #define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT) 841 #define MCSR8_L1IUPRE_SHIFT 0 842 #define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT) 843 844 #define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */ 845 #define MCSR9_L2U_SIZE_SHIFT 56 846 #define MCSR9_L2U_SIZE_WIDTH 7 847 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT) 848 #define MCSR9_L2U_IDX_SHIFT 48 849 #define MCSR9_L2U_IDX_WIDTH 8 850 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT) 851 #define MCSR9_L2U_WAY_SHIFT 32 852 #define MCSR9_L2U_WAY_WIDTH 16 853 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT) 854 #define MCSR9_L1D_SIZE_SHIFT 24 855 #define MCSR9_L1D_SIZE_WIDTH 7 856 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT) 857 #define MCSR9_L1D_IDX_SHIFT 16 858 #define MCSR9_L1D_IDX_WIDTH 8 859 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT) 860 #define MCSR9_L1D_WAY_SHIFT 0 861 #define MCSR9_L1D_WAY_WIDTH 16 862 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT) 863 864 #define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */ 865 #define MCSR10_L3U_SIZE_SHIFT 24 866 #define MCSR10_L3U_SIZE_WIDTH 7 867 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT) 868 #define MCSR10_L3U_IDX_SHIFT 16 869 #define MCSR10_L3U_IDX_WIDTH 8 870 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT) 871 #define MCSR10_L3U_WAY_SHIFT 0 872 #define MCSR10_L3U_WAY_WIDTH 16 873 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT) 874 875 #define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */ 876 #define MCSR24_RAMCG_SHIFT 3 877 #define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT) 878 #define MCSR24_VFPUCG_SHIFT 2 879 #define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT) 880 #define MCSR24_NAPEN_SHIFT 1 881 #define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT) 882 #define MCSR24_MCSRLOCK_SHIFT 0 883 #define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT) 884 885 /* Uncached accelerate windows registers */ 886 #define LOONGARCH_CSR_UCAWIN 0x100 887 #define LOONGARCH_CSR_UCAWIN0_LO 0x102 888 #define LOONGARCH_CSR_UCAWIN0_HI 0x103 889 #define LOONGARCH_CSR_UCAWIN1_LO 0x104 890 #define LOONGARCH_CSR_UCAWIN1_HI 0x105 891 #define LOONGARCH_CSR_UCAWIN2_LO 0x106 892 #define LOONGARCH_CSR_UCAWIN2_HI 0x107 893 #define LOONGARCH_CSR_UCAWIN3_LO 0x108 894 #define LOONGARCH_CSR_UCAWIN3_HI 0x109 895 896 /* Direct Map windows registers */ 897 #define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */ 898 #define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */ 899 #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */ 900 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */ 901 902 /* Direct Map window 0/1 */ 903 #define CSR_DMW0_PLV0 _CONST64_(1 << 0) 904 #define CSR_DMW0_VSEG _CONST64_(0x8000) 905 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) 906 #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0) 907 908 #define CSR_DMW1_PLV0 _CONST64_(1 << 0) 909 #define CSR_DMW1_MAT _CONST64_(1 << 4) 910 #define CSR_DMW1_VSEG _CONST64_(0x9000) 911 #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) 912 #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) 913 914 /* Performance Counter registers */ 915 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */ 916 #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */ 917 #define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */ 918 #define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */ 919 #define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */ 920 #define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */ 921 #define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */ 922 #define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */ 923 #define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16) 924 #define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17) 925 #define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18) 926 #define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19) 927 #define CSR_PERFCTRL_IE (_ULCAST_(1) << 20) 928 #define CSR_PERFCTRL_EVENT 0x3ff 929 930 /* Debug registers */ 931 #define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */ 932 #define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */ 933 934 #define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */ 935 #define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */ 936 #define LOONGARCH_CSR_DB0CTRL 0x312 /* data breakpoint 0 control */ 937 #define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */ 938 939 #define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */ 940 #define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */ 941 #define LOONGARCH_CSR_DB1CTRL 0x31a /* data breakpoint 1 control */ 942 #define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */ 943 944 #define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */ 945 #define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */ 946 #define LOONGARCH_CSR_DB2CTRL 0x322 /* data breakpoint 2 control */ 947 #define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */ 948 949 #define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */ 950 #define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */ 951 #define LOONGARCH_CSR_DB3CTRL 0x32a /* data breakpoint 3 control */ 952 #define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */ 953 954 #define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */ 955 #define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */ 956 #define LOONGARCH_CSR_DB4CTRL 0x332 /* data breakpoint 4 control */ 957 #define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */ 958 959 #define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */ 960 #define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */ 961 #define LOONGARCH_CSR_DB5CTRL 0x33a /* data breakpoint 5 control */ 962 #define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */ 963 964 #define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */ 965 #define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */ 966 #define LOONGARCH_CSR_DB6CTRL 0x342 /* data breakpoint 6 control */ 967 #define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */ 968 969 #define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */ 970 #define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */ 971 #define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */ 972 #define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */ 973 974 #define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */ 975 #define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */ 976 977 #define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */ 978 #define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */ 979 #define LOONGARCH_CSR_IB0CTRL 0x392 /* inst breakpoint 0 control */ 980 #define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */ 981 982 #define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */ 983 #define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */ 984 #define LOONGARCH_CSR_IB1CTRL 0x39a /* inst breakpoint 1 control */ 985 #define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */ 986 987 #define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */ 988 #define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */ 989 #define LOONGARCH_CSR_IB2CTRL 0x3a2 /* inst breakpoint 2 control */ 990 #define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */ 991 992 #define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */ 993 #define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */ 994 #define LOONGARCH_CSR_IB3CTRL 0x3aa /* inst breakpoint 3 control */ 995 #define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */ 996 997 #define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */ 998 #define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */ 999 #define LOONGARCH_CSR_IB4CTRL 0x3b2 /* inst breakpoint 4 control */ 1000 #define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */ 1001 1002 #define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */ 1003 #define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */ 1004 #define LOONGARCH_CSR_IB5CTRL 0x3ba /* inst breakpoint 5 control */ 1005 #define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */ 1006 1007 #define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */ 1008 #define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */ 1009 #define LOONGARCH_CSR_IB6CTRL 0x3c2 /* inst breakpoint 6 control */ 1010 #define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */ 1011 1012 #define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */ 1013 #define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */ 1014 #define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */ 1015 #define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */ 1016 1017 #define LOONGARCH_CSR_DEBUG 0x500 /* debug config */ 1018 #define LOONGARCH_CSR_DERA 0x501 /* debug era */ 1019 #define LOONGARCH_CSR_DESAVE 0x502 /* debug save */ 1020 1021 #define CSR_FWPC_SKIP_SHIFT 16 1022 #define CSR_FWPC_SKIP (_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT) 1023 1024 /* 1025 * CSR_ECFG IM 1026 */ 1027 #define ECFG0_IM 0x00001fff 1028 #define ECFGB_SIP0 0 1029 #define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0) 1030 #define ECFGB_SIP1 1 1031 #define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1) 1032 #define ECFGB_IP0 2 1033 #define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0) 1034 #define ECFGB_IP1 3 1035 #define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1) 1036 #define ECFGB_IP2 4 1037 #define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2) 1038 #define ECFGB_IP3 5 1039 #define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3) 1040 #define ECFGB_IP4 6 1041 #define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4) 1042 #define ECFGB_IP5 7 1043 #define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5) 1044 #define ECFGB_IP6 8 1045 #define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6) 1046 #define ECFGB_IP7 9 1047 #define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7) 1048 #define ECFGB_PMC 10 1049 #define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC) 1050 #define ECFGB_TIMER 11 1051 #define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER) 1052 #define ECFGB_IPI 12 1053 #define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI) 1054 #define ECFGF(hwirq) (_ULCAST_(1) << hwirq) 1055 1056 #define ESTATF_IP 0x00003fff 1057 1058 #define LOONGARCH_IOCSR_FEATURES 0x8 1059 #define IOCSRF_TEMP BIT_ULL(0) 1060 #define IOCSRF_NODECNT BIT_ULL(1) 1061 #define IOCSRF_MSI BIT_ULL(2) 1062 #define IOCSRF_EXTIOI BIT_ULL(3) 1063 #define IOCSRF_CSRIPI BIT_ULL(4) 1064 #define IOCSRF_FREQCSR BIT_ULL(5) 1065 #define IOCSRF_FREQSCALE BIT_ULL(6) 1066 #define IOCSRF_DVFSV1 BIT_ULL(7) 1067 #define IOCSRF_EIODECODE BIT_ULL(9) 1068 #define IOCSRF_FLATMODE BIT_ULL(10) 1069 #define IOCSRF_VM BIT_ULL(11) 1070 1071 #define LOONGARCH_IOCSR_VENDOR 0x10 1072 1073 #define LOONGARCH_IOCSR_CPUNAME 0x20 1074 1075 #define LOONGARCH_IOCSR_NODECNT 0x408 1076 1077 #define LOONGARCH_IOCSR_MISC_FUNC 0x420 1078 #define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21) 1079 #define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48) 1080 1081 #define LOONGARCH_IOCSR_CPUTEMP 0x428 1082 1083 /* PerCore CSR, only accessible by local cores */ 1084 #define LOONGARCH_IOCSR_IPI_STATUS 0x1000 1085 #define LOONGARCH_IOCSR_IPI_EN 0x1004 1086 #define LOONGARCH_IOCSR_IPI_SET 0x1008 1087 #define LOONGARCH_IOCSR_IPI_CLEAR 0x100c 1088 #define LOONGARCH_IOCSR_MBUF0 0x1020 1089 #define LOONGARCH_IOCSR_MBUF1 0x1028 1090 #define LOONGARCH_IOCSR_MBUF2 0x1030 1091 #define LOONGARCH_IOCSR_MBUF3 0x1038 1092 1093 #define LOONGARCH_IOCSR_IPI_SEND 0x1040 1094 #define IOCSR_IPI_SEND_IP_SHIFT 0 1095 #define IOCSR_IPI_SEND_CPU_SHIFT 16 1096 #define IOCSR_IPI_SEND_BLOCKING BIT(31) 1097 1098 #define LOONGARCH_IOCSR_MBUF_SEND 0x1048 1099 #define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31) 1100 #define IOCSR_MBUF_SEND_BOX_SHIFT 2 1101 #define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1) 1102 #define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1) 1103 #define IOCSR_MBUF_SEND_CPU_SHIFT 16 1104 #define IOCSR_MBUF_SEND_BUF_SHIFT 32 1105 #define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1106 1107 #define LOONGARCH_IOCSR_ANY_SEND 0x1158 1108 #define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31) 1109 #define IOCSR_ANY_SEND_CPU_SHIFT 16 1110 #define IOCSR_ANY_SEND_MASK_SHIFT 27 1111 #define IOCSR_ANY_SEND_BUF_SHIFT 32 1112 #define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1113 1114 /* Register offset and bit definition for CSR access */ 1115 #define LOONGARCH_IOCSR_TIMER_CFG 0x1060 1116 #define LOONGARCH_IOCSR_TIMER_TICK 0x1070 1117 #define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63) 1118 #define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62) 1119 #define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61) 1120 #define IOCSR_TIMER_MASK 0x0ffffffffffffULL 1121 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48) 1122 1123 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0 1124 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0 1125 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600 1126 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680 1127 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800 1128 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00 1129 #define IOCSR_EXTIOI_VECTOR_NUM 256 1130 1131 #ifndef __ASSEMBLY__ 1132 1133 static __always_inline u64 drdtime(void) 1134 { 1135 int rID = 0; 1136 u64 val = 0; 1137 1138 __asm__ __volatile__( 1139 "rdtime.d %0, %1 \n\t" 1140 : "=r"(val), "=r"(rID) 1141 : 1142 ); 1143 return val; 1144 } 1145 1146 static inline unsigned int get_csr_cpuid(void) 1147 { 1148 return csr_read32(LOONGARCH_CSR_CPUID); 1149 } 1150 1151 static inline void csr_any_send(unsigned int addr, unsigned int data, 1152 unsigned int data_mask, unsigned int cpu) 1153 { 1154 uint64_t val = 0; 1155 1156 val = IOCSR_ANY_SEND_BLOCKING | addr; 1157 val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT); 1158 val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT); 1159 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT); 1160 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND); 1161 } 1162 1163 static inline unsigned int read_csr_excode(void) 1164 { 1165 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 1166 } 1167 1168 static inline void write_csr_index(unsigned int idx) 1169 { 1170 csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX); 1171 } 1172 1173 static inline unsigned int read_csr_pagesize(void) 1174 { 1175 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE; 1176 } 1177 1178 static inline void write_csr_pagesize(unsigned int size) 1179 { 1180 csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX); 1181 } 1182 1183 static inline unsigned int read_csr_tlbrefill_pagesize(void) 1184 { 1185 return (csr_read64(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT; 1186 } 1187 1188 static inline void write_csr_tlbrefill_pagesize(unsigned int size) 1189 { 1190 csr_xchg64(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI); 1191 } 1192 1193 #define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID) 1194 #define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID) 1195 #define read_csr_entryhi() csr_read64(LOONGARCH_CSR_TLBEHI) 1196 #define write_csr_entryhi(val) csr_write64(val, LOONGARCH_CSR_TLBEHI) 1197 #define read_csr_entrylo0() csr_read64(LOONGARCH_CSR_TLBELO0) 1198 #define write_csr_entrylo0(val) csr_write64(val, LOONGARCH_CSR_TLBELO0) 1199 #define read_csr_entrylo1() csr_read64(LOONGARCH_CSR_TLBELO1) 1200 #define write_csr_entrylo1(val) csr_write64(val, LOONGARCH_CSR_TLBELO1) 1201 #define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG) 1202 #define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG) 1203 #define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT) 1204 #define write_csr_estat(val) csr_write32(val, LOONGARCH_CSR_ESTAT) 1205 #define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX) 1206 #define write_csr_tlbidx(val) csr_write32(val, LOONGARCH_CSR_TLBIDX) 1207 #define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN) 1208 #define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN) 1209 #define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID) 1210 #define read_csr_prcfg1() csr_read64(LOONGARCH_CSR_PRCFG1) 1211 #define write_csr_prcfg1(val) csr_write64(val, LOONGARCH_CSR_PRCFG1) 1212 #define read_csr_prcfg2() csr_read64(LOONGARCH_CSR_PRCFG2) 1213 #define write_csr_prcfg2(val) csr_write64(val, LOONGARCH_CSR_PRCFG2) 1214 #define read_csr_prcfg3() csr_read64(LOONGARCH_CSR_PRCFG3) 1215 #define write_csr_prcfg3(val) csr_write64(val, LOONGARCH_CSR_PRCFG3) 1216 #define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE) 1217 #define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE) 1218 #define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG) 1219 #define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG) 1220 #define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR) 1221 #define read_csr_impctl1() csr_read64(LOONGARCH_CSR_IMPCTL1) 1222 #define write_csr_impctl1(val) csr_write64(val, LOONGARCH_CSR_IMPCTL1) 1223 #define write_csr_impctl2(val) csr_write64(val, LOONGARCH_CSR_IMPCTL2) 1224 1225 #define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0) 1226 #define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0) 1227 #define read_csr_perfctrl1() csr_read64(LOONGARCH_CSR_PERFCTRL1) 1228 #define read_csr_perfcntr1() csr_read64(LOONGARCH_CSR_PERFCNTR1) 1229 #define read_csr_perfctrl2() csr_read64(LOONGARCH_CSR_PERFCTRL2) 1230 #define read_csr_perfcntr2() csr_read64(LOONGARCH_CSR_PERFCNTR2) 1231 #define read_csr_perfctrl3() csr_read64(LOONGARCH_CSR_PERFCTRL3) 1232 #define read_csr_perfcntr3() csr_read64(LOONGARCH_CSR_PERFCNTR3) 1233 #define write_csr_perfctrl0(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL0) 1234 #define write_csr_perfcntr0(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR0) 1235 #define write_csr_perfctrl1(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL1) 1236 #define write_csr_perfcntr1(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR1) 1237 #define write_csr_perfctrl2(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL2) 1238 #define write_csr_perfcntr2(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR2) 1239 #define write_csr_perfctrl3(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL3) 1240 #define write_csr_perfcntr3(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR3) 1241 1242 /* 1243 * Manipulate bits in a register. 1244 */ 1245 #define __BUILD_CSR_COMMON(name) \ 1246 static inline unsigned long \ 1247 set_##name(unsigned long set) \ 1248 { \ 1249 unsigned long res, new; \ 1250 \ 1251 res = read_##name(); \ 1252 new = res | set; \ 1253 write_##name(new); \ 1254 \ 1255 return res; \ 1256 } \ 1257 \ 1258 static inline unsigned long \ 1259 clear_##name(unsigned long clear) \ 1260 { \ 1261 unsigned long res, new; \ 1262 \ 1263 res = read_##name(); \ 1264 new = res & ~clear; \ 1265 write_##name(new); \ 1266 \ 1267 return res; \ 1268 } \ 1269 \ 1270 static inline unsigned long \ 1271 change_##name(unsigned long change, unsigned long val) \ 1272 { \ 1273 unsigned long res, new; \ 1274 \ 1275 res = read_##name(); \ 1276 new = res & ~change; \ 1277 new |= (val & change); \ 1278 write_##name(new); \ 1279 \ 1280 return res; \ 1281 } 1282 1283 #define __BUILD_CSR_OP(name) __BUILD_CSR_COMMON(csr_##name) 1284 1285 __BUILD_CSR_OP(euen) 1286 __BUILD_CSR_OP(ecfg) 1287 __BUILD_CSR_OP(tlbidx) 1288 1289 #define set_csr_estat(val) \ 1290 csr_xchg32(val, val, LOONGARCH_CSR_ESTAT) 1291 #define clear_csr_estat(val) \ 1292 csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT) 1293 1294 #endif /* __ASSEMBLY__ */ 1295 1296 /* Generic EntryLo bit definitions */ 1297 #define ENTRYLO_V (_ULCAST_(1) << 0) 1298 #define ENTRYLO_D (_ULCAST_(1) << 1) 1299 #define ENTRYLO_PLV_SHIFT 2 1300 #define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT) 1301 #define ENTRYLO_C_SHIFT 4 1302 #define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT) 1303 #define ENTRYLO_G (_ULCAST_(1) << 6) 1304 #define ENTRYLO_NR (_ULCAST_(1) << 61) 1305 #define ENTRYLO_NX (_ULCAST_(1) << 62) 1306 1307 /* Values for PageSize register */ 1308 #define PS_4K 0x0000000c 1309 #define PS_8K 0x0000000d 1310 #define PS_16K 0x0000000e 1311 #define PS_32K 0x0000000f 1312 #define PS_64K 0x00000010 1313 #define PS_128K 0x00000011 1314 #define PS_256K 0x00000012 1315 #define PS_512K 0x00000013 1316 #define PS_1M 0x00000014 1317 #define PS_2M 0x00000015 1318 #define PS_4M 0x00000016 1319 #define PS_8M 0x00000017 1320 #define PS_16M 0x00000018 1321 #define PS_32M 0x00000019 1322 #define PS_64M 0x0000001a 1323 #define PS_128M 0x0000001b 1324 #define PS_256M 0x0000001c 1325 #define PS_512M 0x0000001d 1326 #define PS_1G 0x0000001e 1327 1328 /* Default page size for a given kernel configuration */ 1329 #ifdef CONFIG_PAGE_SIZE_4KB 1330 #define PS_DEFAULT_SIZE PS_4K 1331 #elif defined(CONFIG_PAGE_SIZE_16KB) 1332 #define PS_DEFAULT_SIZE PS_16K 1333 #elif defined(CONFIG_PAGE_SIZE_64KB) 1334 #define PS_DEFAULT_SIZE PS_64K 1335 #else 1336 #error Bad page size configuration! 1337 #endif 1338 1339 /* Default huge tlb size for a given kernel configuration */ 1340 #ifdef CONFIG_PAGE_SIZE_4KB 1341 #define PS_HUGE_SIZE PS_1M 1342 #elif defined(CONFIG_PAGE_SIZE_16KB) 1343 #define PS_HUGE_SIZE PS_16M 1344 #elif defined(CONFIG_PAGE_SIZE_64KB) 1345 #define PS_HUGE_SIZE PS_256M 1346 #else 1347 #error Bad page size configuration for hugetlbfs! 1348 #endif 1349 1350 /* ExStatus.ExcCode */ 1351 #define EXCCODE_RSV 0 /* Reserved */ 1352 #define EXCCODE_TLBL 1 /* TLB miss on a load */ 1353 #define EXCCODE_TLBS 2 /* TLB miss on a store */ 1354 #define EXCCODE_TLBI 3 /* TLB miss on a ifetch */ 1355 #define EXCCODE_TLBM 4 /* TLB modified fault */ 1356 #define EXCCODE_TLBNR 5 /* TLB Read-Inhibit exception */ 1357 #define EXCCODE_TLBNX 6 /* TLB Execution-Inhibit exception */ 1358 #define EXCCODE_TLBPE 7 /* TLB Privilege Error */ 1359 #define EXCCODE_ADE 8 /* Address Error */ 1360 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */ 1361 #define EXSUBCODE_ADEM 1 /* Access Memory*/ 1362 #define EXCCODE_ALE 9 /* Unalign Access */ 1363 #define EXCCODE_BCE 10 /* Bounds Check Error */ 1364 #define EXCCODE_SYS 11 /* System call */ 1365 #define EXCCODE_BP 12 /* Breakpoint */ 1366 #define EXCCODE_INE 13 /* Inst. Not Exist */ 1367 #define EXCCODE_IPE 14 /* Inst. Privileged Error */ 1368 #define EXCCODE_FPDIS 15 /* FPU Disabled */ 1369 #define EXCCODE_LSXDIS 16 /* LSX Disabled */ 1370 #define EXCCODE_LASXDIS 17 /* LASX Disabled */ 1371 #define EXCCODE_FPE 18 /* Floating Point Exception */ 1372 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */ 1373 #define EXCSUBCODE_VFPE 1 /* Vector Exception */ 1374 #define EXCCODE_WATCH 19 /* WatchPoint Exception */ 1375 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */ 1376 #define EXCSUBCODE_WPEM 1 /* ... on Memory Accesses */ 1377 #define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */ 1378 #define EXCCODE_BTE 21 /* Binary Trans. Exception */ 1379 #define EXCCODE_GSPR 22 /* Guest Privileged Error */ 1380 #define EXCCODE_HVC 23 /* Hypercall */ 1381 #define EXCCODE_GCM 24 /* Guest CSR modified */ 1382 #define EXCSUBCODE_GCSC 0 /* Software caused */ 1383 #define EXCSUBCODE_GCHC 1 /* Hardware caused */ 1384 #define EXCCODE_SE 25 /* Security */ 1385 1386 /* Interrupt numbers */ 1387 #define INT_SWI0 0 /* Software Interrupts */ 1388 #define INT_SWI1 1 1389 #define INT_HWI0 2 /* Hardware Interrupts */ 1390 #define INT_HWI1 3 1391 #define INT_HWI2 4 1392 #define INT_HWI3 5 1393 #define INT_HWI4 6 1394 #define INT_HWI5 7 1395 #define INT_HWI6 8 1396 #define INT_HWI7 9 1397 #define INT_PCOV 10 /* Performance Counter Overflow */ 1398 #define INT_TI 11 /* Timer */ 1399 #define INT_IPI 12 1400 #define INT_NMI 13 1401 1402 /* ExcCodes corresponding to interrupts */ 1403 #define EXCCODE_INT_NUM (INT_NMI + 1) 1404 #define EXCCODE_INT_START 64 1405 #define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1) 1406 1407 /* FPU Status Register Names */ 1408 #ifndef CONFIG_AS_HAS_FCSR_CLASS 1409 #define LOONGARCH_FCSR0 $r0 1410 #define LOONGARCH_FCSR1 $r1 1411 #define LOONGARCH_FCSR2 $r2 1412 #define LOONGARCH_FCSR3 $r3 1413 #else 1414 #define LOONGARCH_FCSR0 $fcsr0 1415 #define LOONGARCH_FCSR1 $fcsr1 1416 #define LOONGARCH_FCSR2 $fcsr2 1417 #define LOONGARCH_FCSR3 $fcsr3 1418 #endif 1419 1420 /* FPU Status Register Values */ 1421 #define FPU_CSR_RSVD 0xe0e0fce0 1422 1423 /* 1424 * X the exception cause indicator 1425 * E the exception enable 1426 * S the sticky/flag bit 1427 */ 1428 #define FPU_CSR_ALL_X 0x1f000000 1429 #define FPU_CSR_INV_X 0x10000000 1430 #define FPU_CSR_DIV_X 0x08000000 1431 #define FPU_CSR_OVF_X 0x04000000 1432 #define FPU_CSR_UDF_X 0x02000000 1433 #define FPU_CSR_INE_X 0x01000000 1434 1435 #define FPU_CSR_ALL_S 0x001f0000 1436 #define FPU_CSR_INV_S 0x00100000 1437 #define FPU_CSR_DIV_S 0x00080000 1438 #define FPU_CSR_OVF_S 0x00040000 1439 #define FPU_CSR_UDF_S 0x00020000 1440 #define FPU_CSR_INE_S 0x00010000 1441 1442 #define FPU_CSR_ALL_E 0x0000001f 1443 #define FPU_CSR_INV_E 0x00000010 1444 #define FPU_CSR_DIV_E 0x00000008 1445 #define FPU_CSR_OVF_E 0x00000004 1446 #define FPU_CSR_UDF_E 0x00000002 1447 #define FPU_CSR_INE_E 0x00000001 1448 1449 /* Bits 8 and 9 of FPU Status Register specify the rounding mode */ 1450 #define FPU_CSR_RM 0x300 1451 #define FPU_CSR_RN 0x000 /* nearest */ 1452 #define FPU_CSR_RZ 0x100 /* towards zero */ 1453 #define FPU_CSR_RU 0x200 /* towards +Infinity */ 1454 #define FPU_CSR_RD 0x300 /* towards -Infinity */ 1455 1456 #define read_fcsr(source) \ 1457 ({ \ 1458 unsigned int __res; \ 1459 \ 1460 __asm__ __volatile__( \ 1461 " movfcsr2gr %0, "__stringify(source)" \n" \ 1462 : "=r" (__res)); \ 1463 __res; \ 1464 }) 1465 1466 #define write_fcsr(dest, val) \ 1467 do { \ 1468 __asm__ __volatile__( \ 1469 " movgr2fcsr "__stringify(dest)", %0 \n" \ 1470 : : "r" (val)); \ 1471 } while (0) 1472 1473 #endif /* _ASM_LOONGARCH_H */ 1474