1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_INST_H 6 #define _ASM_INST_H 7 8 #include <linux/types.h> 9 #include <asm/asm.h> 10 #include <asm/ptrace.h> 11 12 #define INSN_NOP 0x03400000 13 #define INSN_BREAK 0x002a0000 14 15 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000 16 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000 17 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000 18 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000 19 20 #define ADDR_IMMSHIFT_LU52ID 52 21 #define ADDR_IMMSHIFT_LU32ID 32 22 #define ADDR_IMMSHIFT_LU12IW 12 23 #define ADDR_IMMSHIFT_ADDU16ID 16 24 25 #define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN) 26 27 enum reg0i15_op { 28 break_op = 0x54, 29 }; 30 31 enum reg0i26_op { 32 b_op = 0x14, 33 bl_op = 0x15, 34 }; 35 36 enum reg1i20_op { 37 lu12iw_op = 0x0a, 38 lu32id_op = 0x0b, 39 pcaddi_op = 0x0c, 40 pcalau12i_op = 0x0d, 41 pcaddu12i_op = 0x0e, 42 pcaddu18i_op = 0x0f, 43 }; 44 45 enum reg1i21_op { 46 beqz_op = 0x10, 47 bnez_op = 0x11, 48 bceqz_op = 0x12, /* bits[9:8] = 0x00 */ 49 bcnez_op = 0x12, /* bits[9:8] = 0x01 */ 50 }; 51 52 enum reg2_op { 53 revb2h_op = 0x0c, 54 revb4h_op = 0x0d, 55 revb2w_op = 0x0e, 56 revbd_op = 0x0f, 57 revh2w_op = 0x10, 58 revhd_op = 0x11, 59 }; 60 61 enum reg2i5_op { 62 slliw_op = 0x81, 63 srliw_op = 0x89, 64 sraiw_op = 0x91, 65 }; 66 67 enum reg2i6_op { 68 sllid_op = 0x41, 69 srlid_op = 0x45, 70 sraid_op = 0x49, 71 }; 72 73 enum reg2i12_op { 74 addiw_op = 0x0a, 75 addid_op = 0x0b, 76 lu52id_op = 0x0c, 77 andi_op = 0x0d, 78 ori_op = 0x0e, 79 xori_op = 0x0f, 80 ldb_op = 0xa0, 81 ldh_op = 0xa1, 82 ldw_op = 0xa2, 83 ldd_op = 0xa3, 84 stb_op = 0xa4, 85 sth_op = 0xa5, 86 stw_op = 0xa6, 87 std_op = 0xa7, 88 ldbu_op = 0xa8, 89 ldhu_op = 0xa9, 90 ldwu_op = 0xaa, 91 flds_op = 0xac, 92 fsts_op = 0xad, 93 fldd_op = 0xae, 94 fstd_op = 0xaf, 95 }; 96 97 enum reg2i14_op { 98 llw_op = 0x20, 99 scw_op = 0x21, 100 lld_op = 0x22, 101 scd_op = 0x23, 102 ldptrw_op = 0x24, 103 stptrw_op = 0x25, 104 ldptrd_op = 0x26, 105 stptrd_op = 0x27, 106 }; 107 108 enum reg2i16_op { 109 jirl_op = 0x13, 110 beq_op = 0x16, 111 bne_op = 0x17, 112 blt_op = 0x18, 113 bge_op = 0x19, 114 bltu_op = 0x1a, 115 bgeu_op = 0x1b, 116 }; 117 118 enum reg2bstrd_op { 119 bstrinsd_op = 0x2, 120 bstrpickd_op = 0x3, 121 }; 122 123 enum reg3_op { 124 asrtle_op = 0x02, 125 asrtgt_op = 0x03, 126 addw_op = 0x20, 127 addd_op = 0x21, 128 subw_op = 0x22, 129 subd_op = 0x23, 130 nor_op = 0x28, 131 and_op = 0x29, 132 or_op = 0x2a, 133 xor_op = 0x2b, 134 orn_op = 0x2c, 135 andn_op = 0x2d, 136 sllw_op = 0x2e, 137 srlw_op = 0x2f, 138 sraw_op = 0x30, 139 slld_op = 0x31, 140 srld_op = 0x32, 141 srad_op = 0x33, 142 mulw_op = 0x38, 143 mulhw_op = 0x39, 144 mulhwu_op = 0x3a, 145 muld_op = 0x3b, 146 mulhd_op = 0x3c, 147 mulhdu_op = 0x3d, 148 divw_op = 0x40, 149 modw_op = 0x41, 150 divwu_op = 0x42, 151 modwu_op = 0x43, 152 divd_op = 0x44, 153 modd_op = 0x45, 154 divdu_op = 0x46, 155 moddu_op = 0x47, 156 ldxb_op = 0x7000, 157 ldxh_op = 0x7008, 158 ldxw_op = 0x7010, 159 ldxd_op = 0x7018, 160 stxb_op = 0x7020, 161 stxh_op = 0x7028, 162 stxw_op = 0x7030, 163 stxd_op = 0x7038, 164 ldxbu_op = 0x7040, 165 ldxhu_op = 0x7048, 166 ldxwu_op = 0x7050, 167 fldxs_op = 0x7060, 168 fldxd_op = 0x7068, 169 fstxs_op = 0x7070, 170 fstxd_op = 0x7078, 171 amswapw_op = 0x70c0, 172 amswapd_op = 0x70c1, 173 amaddw_op = 0x70c2, 174 amaddd_op = 0x70c3, 175 amandw_op = 0x70c4, 176 amandd_op = 0x70c5, 177 amorw_op = 0x70c6, 178 amord_op = 0x70c7, 179 amxorw_op = 0x70c8, 180 amxord_op = 0x70c9, 181 fldgts_op = 0x70e8, 182 fldgtd_op = 0x70e9, 183 fldles_op = 0x70ea, 184 fldled_op = 0x70eb, 185 fstgts_op = 0x70ec, 186 fstgtd_op = 0x70ed, 187 fstles_op = 0x70ee, 188 fstled_op = 0x70ef, 189 ldgtb_op = 0x70f0, 190 ldgth_op = 0x70f1, 191 ldgtw_op = 0x70f2, 192 ldgtd_op = 0x70f3, 193 ldleb_op = 0x70f4, 194 ldleh_op = 0x70f5, 195 ldlew_op = 0x70f6, 196 ldled_op = 0x70f7, 197 stgtb_op = 0x70f8, 198 stgth_op = 0x70f9, 199 stgtw_op = 0x70fa, 200 stgtd_op = 0x70fb, 201 stleb_op = 0x70fc, 202 stleh_op = 0x70fd, 203 stlew_op = 0x70fe, 204 stled_op = 0x70ff, 205 }; 206 207 enum reg3sa2_op { 208 alslw_op = 0x02, 209 alslwu_op = 0x03, 210 alsld_op = 0x16, 211 }; 212 213 struct reg0i15_format { 214 unsigned int immediate : 15; 215 unsigned int opcode : 17; 216 }; 217 218 struct reg0i26_format { 219 unsigned int immediate_h : 10; 220 unsigned int immediate_l : 16; 221 unsigned int opcode : 6; 222 }; 223 224 struct reg1i20_format { 225 unsigned int rd : 5; 226 unsigned int immediate : 20; 227 unsigned int opcode : 7; 228 }; 229 230 struct reg1i21_format { 231 unsigned int immediate_h : 5; 232 unsigned int rj : 5; 233 unsigned int immediate_l : 16; 234 unsigned int opcode : 6; 235 }; 236 237 struct reg2_format { 238 unsigned int rd : 5; 239 unsigned int rj : 5; 240 unsigned int opcode : 22; 241 }; 242 243 struct reg2i5_format { 244 unsigned int rd : 5; 245 unsigned int rj : 5; 246 unsigned int immediate : 5; 247 unsigned int opcode : 17; 248 }; 249 250 struct reg2i6_format { 251 unsigned int rd : 5; 252 unsigned int rj : 5; 253 unsigned int immediate : 6; 254 unsigned int opcode : 16; 255 }; 256 257 struct reg2i12_format { 258 unsigned int rd : 5; 259 unsigned int rj : 5; 260 unsigned int immediate : 12; 261 unsigned int opcode : 10; 262 }; 263 264 struct reg2i14_format { 265 unsigned int rd : 5; 266 unsigned int rj : 5; 267 unsigned int immediate : 14; 268 unsigned int opcode : 8; 269 }; 270 271 struct reg2i16_format { 272 unsigned int rd : 5; 273 unsigned int rj : 5; 274 unsigned int immediate : 16; 275 unsigned int opcode : 6; 276 }; 277 278 struct reg2bstrd_format { 279 unsigned int rd : 5; 280 unsigned int rj : 5; 281 unsigned int lsbd : 6; 282 unsigned int msbd : 6; 283 unsigned int opcode : 10; 284 }; 285 286 struct reg3_format { 287 unsigned int rd : 5; 288 unsigned int rj : 5; 289 unsigned int rk : 5; 290 unsigned int opcode : 17; 291 }; 292 293 struct reg3sa2_format { 294 unsigned int rd : 5; 295 unsigned int rj : 5; 296 unsigned int rk : 5; 297 unsigned int immediate : 2; 298 unsigned int opcode : 15; 299 }; 300 301 union loongarch_instruction { 302 unsigned int word; 303 struct reg0i15_format reg0i15_format; 304 struct reg0i26_format reg0i26_format; 305 struct reg1i20_format reg1i20_format; 306 struct reg1i21_format reg1i21_format; 307 struct reg2_format reg2_format; 308 struct reg2i5_format reg2i5_format; 309 struct reg2i6_format reg2i6_format; 310 struct reg2i12_format reg2i12_format; 311 struct reg2i14_format reg2i14_format; 312 struct reg2i16_format reg2i16_format; 313 struct reg2bstrd_format reg2bstrd_format; 314 struct reg3_format reg3_format; 315 struct reg3sa2_format reg3sa2_format; 316 }; 317 318 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction) 319 320 enum loongarch_gpr { 321 LOONGARCH_GPR_ZERO = 0, 322 LOONGARCH_GPR_RA = 1, 323 LOONGARCH_GPR_TP = 2, 324 LOONGARCH_GPR_SP = 3, 325 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */ 326 LOONGARCH_GPR_A1, /* Reused as V1 for return value */ 327 LOONGARCH_GPR_A2, 328 LOONGARCH_GPR_A3, 329 LOONGARCH_GPR_A4, 330 LOONGARCH_GPR_A5, 331 LOONGARCH_GPR_A6, 332 LOONGARCH_GPR_A7, 333 LOONGARCH_GPR_T0 = 12, 334 LOONGARCH_GPR_T1, 335 LOONGARCH_GPR_T2, 336 LOONGARCH_GPR_T3, 337 LOONGARCH_GPR_T4, 338 LOONGARCH_GPR_T5, 339 LOONGARCH_GPR_T6, 340 LOONGARCH_GPR_T7, 341 LOONGARCH_GPR_T8, 342 LOONGARCH_GPR_FP = 22, 343 LOONGARCH_GPR_S0 = 23, 344 LOONGARCH_GPR_S1, 345 LOONGARCH_GPR_S2, 346 LOONGARCH_GPR_S3, 347 LOONGARCH_GPR_S4, 348 LOONGARCH_GPR_S5, 349 LOONGARCH_GPR_S6, 350 LOONGARCH_GPR_S7, 351 LOONGARCH_GPR_S8, 352 LOONGARCH_GPR_MAX 353 }; 354 355 #define is_imm12_negative(val) is_imm_negative(val, 12) 356 357 static inline bool is_imm_negative(unsigned long val, unsigned int bit) 358 { 359 return val & (1UL << (bit - 1)); 360 } 361 362 static inline bool is_break_ins(union loongarch_instruction *ip) 363 { 364 return ip->reg0i15_format.opcode == break_op; 365 } 366 367 static inline bool is_pc_ins(union loongarch_instruction *ip) 368 { 369 return ip->reg1i20_format.opcode >= pcaddi_op && 370 ip->reg1i20_format.opcode <= pcaddu18i_op; 371 } 372 373 static inline bool is_branch_ins(union loongarch_instruction *ip) 374 { 375 return ip->reg1i21_format.opcode >= beqz_op && 376 ip->reg1i21_format.opcode <= bgeu_op; 377 } 378 379 static inline bool is_ra_save_ins(union loongarch_instruction *ip) 380 { 381 /* st.d $ra, $sp, offset */ 382 return ip->reg2i12_format.opcode == std_op && 383 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 384 ip->reg2i12_format.rd == LOONGARCH_GPR_RA && 385 !is_imm12_negative(ip->reg2i12_format.immediate); 386 } 387 388 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip) 389 { 390 /* addi.d $sp, $sp, -imm */ 391 return ip->reg2i12_format.opcode == addid_op && 392 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 393 ip->reg2i12_format.rd == LOONGARCH_GPR_SP && 394 is_imm12_negative(ip->reg2i12_format.immediate); 395 } 396 397 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs) 398 { 399 switch (ip->reg0i26_format.opcode) { 400 case b_op: 401 case bl_op: 402 if (ip->reg0i26_format.immediate_l == 0 403 && ip->reg0i26_format.immediate_h == 0) 404 return true; 405 } 406 407 switch (ip->reg1i21_format.opcode) { 408 case beqz_op: 409 case bnez_op: 410 case bceqz_op: 411 if (ip->reg1i21_format.immediate_l == 0 412 && ip->reg1i21_format.immediate_h == 0) 413 return true; 414 } 415 416 switch (ip->reg2i16_format.opcode) { 417 case beq_op: 418 case bne_op: 419 case blt_op: 420 case bge_op: 421 case bltu_op: 422 case bgeu_op: 423 if (ip->reg2i16_format.immediate == 0) 424 return true; 425 break; 426 case jirl_op: 427 if (regs->regs[ip->reg2i16_format.rj] + 428 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip) 429 return true; 430 } 431 432 return false; 433 } 434 435 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn); 436 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn); 437 438 int larch_insn_read(void *addr, u32 *insnp); 439 int larch_insn_write(void *addr, u32 insn); 440 int larch_insn_patch_text(void *addr, u32 insn); 441 442 u32 larch_insn_gen_nop(void); 443 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest); 444 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest); 445 446 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk); 447 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj); 448 449 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm); 450 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm); 451 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 452 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest); 453 454 static inline bool signed_imm_check(long val, unsigned int bit) 455 { 456 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1)); 457 } 458 459 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit) 460 { 461 return val < (1UL << bit); 462 } 463 464 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \ 465 static inline void emit_##NAME(union loongarch_instruction *insn, \ 466 int offset) \ 467 { \ 468 unsigned int immediate_l, immediate_h; \ 469 \ 470 immediate_l = offset & 0xffff; \ 471 offset >>= 16; \ 472 immediate_h = offset & 0x3ff; \ 473 \ 474 insn->reg0i26_format.opcode = OP; \ 475 insn->reg0i26_format.immediate_l = immediate_l; \ 476 insn->reg0i26_format.immediate_h = immediate_h; \ 477 } 478 479 DEF_EMIT_REG0I26_FORMAT(b, b_op) 480 DEF_EMIT_REG0I26_FORMAT(bl, bl_op) 481 482 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \ 483 static inline void emit_##NAME(union loongarch_instruction *insn, \ 484 enum loongarch_gpr rd, int imm) \ 485 { \ 486 insn->reg1i20_format.opcode = OP; \ 487 insn->reg1i20_format.immediate = imm; \ 488 insn->reg1i20_format.rd = rd; \ 489 } 490 491 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op) 492 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op) 493 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op) 494 495 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \ 496 static inline void emit_##NAME(union loongarch_instruction *insn, \ 497 enum loongarch_gpr rd, \ 498 enum loongarch_gpr rj) \ 499 { \ 500 insn->reg2_format.opcode = OP; \ 501 insn->reg2_format.rd = rd; \ 502 insn->reg2_format.rj = rj; \ 503 } 504 505 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op) 506 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op) 507 DEF_EMIT_REG2_FORMAT(revbd, revbd_op) 508 509 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \ 510 static inline void emit_##NAME(union loongarch_instruction *insn, \ 511 enum loongarch_gpr rd, \ 512 enum loongarch_gpr rj, \ 513 int imm) \ 514 { \ 515 insn->reg2i5_format.opcode = OP; \ 516 insn->reg2i5_format.immediate = imm; \ 517 insn->reg2i5_format.rd = rd; \ 518 insn->reg2i5_format.rj = rj; \ 519 } 520 521 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op) 522 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op) 523 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op) 524 525 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \ 526 static inline void emit_##NAME(union loongarch_instruction *insn, \ 527 enum loongarch_gpr rd, \ 528 enum loongarch_gpr rj, \ 529 int imm) \ 530 { \ 531 insn->reg2i6_format.opcode = OP; \ 532 insn->reg2i6_format.immediate = imm; \ 533 insn->reg2i6_format.rd = rd; \ 534 insn->reg2i6_format.rj = rj; \ 535 } 536 537 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op) 538 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op) 539 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op) 540 541 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \ 542 static inline void emit_##NAME(union loongarch_instruction *insn, \ 543 enum loongarch_gpr rd, \ 544 enum loongarch_gpr rj, \ 545 int imm) \ 546 { \ 547 insn->reg2i12_format.opcode = OP; \ 548 insn->reg2i12_format.immediate = imm; \ 549 insn->reg2i12_format.rd = rd; \ 550 insn->reg2i12_format.rj = rj; \ 551 } 552 553 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op) 554 DEF_EMIT_REG2I12_FORMAT(addid, addid_op) 555 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op) 556 DEF_EMIT_REG2I12_FORMAT(andi, andi_op) 557 DEF_EMIT_REG2I12_FORMAT(ori, ori_op) 558 DEF_EMIT_REG2I12_FORMAT(xori, xori_op) 559 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op) 560 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op) 561 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op) 562 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op) 563 DEF_EMIT_REG2I12_FORMAT(stb, stb_op) 564 DEF_EMIT_REG2I12_FORMAT(sth, sth_op) 565 DEF_EMIT_REG2I12_FORMAT(stw, stw_op) 566 DEF_EMIT_REG2I12_FORMAT(std, std_op) 567 568 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \ 569 static inline void emit_##NAME(union loongarch_instruction *insn, \ 570 enum loongarch_gpr rd, \ 571 enum loongarch_gpr rj, \ 572 int imm) \ 573 { \ 574 insn->reg2i14_format.opcode = OP; \ 575 insn->reg2i14_format.immediate = imm; \ 576 insn->reg2i14_format.rd = rd; \ 577 insn->reg2i14_format.rj = rj; \ 578 } 579 580 DEF_EMIT_REG2I14_FORMAT(llw, llw_op) 581 DEF_EMIT_REG2I14_FORMAT(scw, scw_op) 582 DEF_EMIT_REG2I14_FORMAT(lld, lld_op) 583 DEF_EMIT_REG2I14_FORMAT(scd, scd_op) 584 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op) 585 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op) 586 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op) 587 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op) 588 589 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \ 590 static inline void emit_##NAME(union loongarch_instruction *insn, \ 591 enum loongarch_gpr rj, \ 592 enum loongarch_gpr rd, \ 593 int offset) \ 594 { \ 595 insn->reg2i16_format.opcode = OP; \ 596 insn->reg2i16_format.immediate = offset; \ 597 insn->reg2i16_format.rj = rj; \ 598 insn->reg2i16_format.rd = rd; \ 599 } 600 601 DEF_EMIT_REG2I16_FORMAT(beq, beq_op) 602 DEF_EMIT_REG2I16_FORMAT(bne, bne_op) 603 DEF_EMIT_REG2I16_FORMAT(blt, blt_op) 604 DEF_EMIT_REG2I16_FORMAT(bge, bge_op) 605 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op) 606 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op) 607 DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op) 608 609 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \ 610 static inline void emit_##NAME(union loongarch_instruction *insn, \ 611 enum loongarch_gpr rd, \ 612 enum loongarch_gpr rj, \ 613 int msbd, \ 614 int lsbd) \ 615 { \ 616 insn->reg2bstrd_format.opcode = OP; \ 617 insn->reg2bstrd_format.msbd = msbd; \ 618 insn->reg2bstrd_format.lsbd = lsbd; \ 619 insn->reg2bstrd_format.rj = rj; \ 620 insn->reg2bstrd_format.rd = rd; \ 621 } 622 623 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op) 624 625 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \ 626 static inline void emit_##NAME(union loongarch_instruction *insn, \ 627 enum loongarch_gpr rd, \ 628 enum loongarch_gpr rj, \ 629 enum loongarch_gpr rk) \ 630 { \ 631 insn->reg3_format.opcode = OP; \ 632 insn->reg3_format.rd = rd; \ 633 insn->reg3_format.rj = rj; \ 634 insn->reg3_format.rk = rk; \ 635 } 636 637 DEF_EMIT_REG3_FORMAT(addd, addd_op) 638 DEF_EMIT_REG3_FORMAT(subd, subd_op) 639 DEF_EMIT_REG3_FORMAT(muld, muld_op) 640 DEF_EMIT_REG3_FORMAT(divdu, divdu_op) 641 DEF_EMIT_REG3_FORMAT(moddu, moddu_op) 642 DEF_EMIT_REG3_FORMAT(and, and_op) 643 DEF_EMIT_REG3_FORMAT(or, or_op) 644 DEF_EMIT_REG3_FORMAT(xor, xor_op) 645 DEF_EMIT_REG3_FORMAT(sllw, sllw_op) 646 DEF_EMIT_REG3_FORMAT(slld, slld_op) 647 DEF_EMIT_REG3_FORMAT(srlw, srlw_op) 648 DEF_EMIT_REG3_FORMAT(srld, srld_op) 649 DEF_EMIT_REG3_FORMAT(sraw, sraw_op) 650 DEF_EMIT_REG3_FORMAT(srad, srad_op) 651 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op) 652 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op) 653 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op) 654 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op) 655 DEF_EMIT_REG3_FORMAT(stxb, stxb_op) 656 DEF_EMIT_REG3_FORMAT(stxh, stxh_op) 657 DEF_EMIT_REG3_FORMAT(stxw, stxw_op) 658 DEF_EMIT_REG3_FORMAT(stxd, stxd_op) 659 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op) 660 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op) 661 DEF_EMIT_REG3_FORMAT(amandw, amandw_op) 662 DEF_EMIT_REG3_FORMAT(amandd, amandd_op) 663 DEF_EMIT_REG3_FORMAT(amorw, amorw_op) 664 DEF_EMIT_REG3_FORMAT(amord, amord_op) 665 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op) 666 DEF_EMIT_REG3_FORMAT(amxord, amxord_op) 667 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op) 668 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op) 669 670 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \ 671 static inline void emit_##NAME(union loongarch_instruction *insn, \ 672 enum loongarch_gpr rd, \ 673 enum loongarch_gpr rj, \ 674 enum loongarch_gpr rk, \ 675 int imm) \ 676 { \ 677 insn->reg3sa2_format.opcode = OP; \ 678 insn->reg3sa2_format.immediate = imm; \ 679 insn->reg3sa2_format.rd = rd; \ 680 insn->reg3sa2_format.rj = rj; \ 681 insn->reg3sa2_format.rk = rk; \ 682 } 683 684 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op) 685 686 struct pt_regs; 687 688 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc); 689 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign); 690 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n); 691 692 #endif /* _ASM_INST_H */ 693