1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4  */
5 #ifndef __ASM_CPU_INFO_H
6 #define __ASM_CPU_INFO_H
7 
8 #include <linux/cache.h>
9 #include <linux/types.h>
10 
11 #include <asm/loongarch.h>
12 
13 /* cache_desc->flags */
14 enum {
15 	CACHE_PRESENT	= (1 << 0),
16 	CACHE_PRIVATE	= (1 << 1),	/* core private cache */
17 	CACHE_INCLUSIVE	= (1 << 2),	/* include the inner level caches */
18 };
19 
20 /*
21  * Descriptor for a cache
22  */
23 struct cache_desc {
24 	unsigned char type;
25 	unsigned char level;
26 	unsigned short sets;	/* Number of lines per set */
27 	unsigned char ways;	/* Number of ways */
28 	unsigned char linesz;	/* Size of line in bytes */
29 	unsigned char flags;	/* Flags describing cache properties */
30 };
31 
32 #define CACHE_LEVEL_MAX		3
33 #define CACHE_LEAVES_MAX	6
34 
35 struct cpuinfo_loongarch {
36 	u64			asid_cache;
37 	unsigned long		asid_mask;
38 
39 	/*
40 	 * Capability and feature descriptor structure for LoongArch CPU
41 	 */
42 	unsigned long long	options;
43 	unsigned int		processor_id;
44 	unsigned int		fpu_vers;
45 	unsigned int		fpu_csr0;
46 	unsigned int		fpu_mask;
47 	unsigned int		cputype;
48 	int			isa_level;
49 	int			tlbsize;
50 	int			tlbsizemtlb;
51 	int			tlbsizestlbsets;
52 	int			tlbsizestlbways;
53 	int			cache_leaves_present; /* number of cache_leaves[] elements */
54 	struct cache_desc	cache_leaves[CACHE_LEAVES_MAX];
55 	int			core;   /* physical core number in package */
56 	int			package;/* physical package number */
57 	int			vabits; /* Virtual Address size in bits */
58 	int			pabits; /* Physical Address size in bits */
59 	unsigned int		ksave_mask; /* Usable KSave mask. */
60 	unsigned int		watch_dreg_count;   /* Number data breakpoints */
61 	unsigned int		watch_ireg_count;   /* Number instruction breakpoints */
62 	unsigned int		watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
63 } __aligned(SMP_CACHE_BYTES);
64 
65 extern struct cpuinfo_loongarch cpu_data[];
66 #define boot_cpu_data cpu_data[0]
67 #define current_cpu_data cpu_data[smp_processor_id()]
68 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
69 
70 extern void cpu_probe(void);
71 
72 extern const char *__cpu_family[];
73 extern const char *__cpu_full_name[];
74 #define cpu_family_string()	__cpu_family[raw_smp_processor_id()]
75 #define cpu_full_name_string()	__cpu_full_name[raw_smp_processor_id()]
76 
77 struct seq_file;
78 struct notifier_block;
79 
80 extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
81 extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
82 
83 #define proc_cpuinfo_notifier(fn, pri)					\
84 ({									\
85 	static struct notifier_block fn##_nb = {			\
86 		.notifier_call = fn,					\
87 		.priority = pri						\
88 	};								\
89 									\
90 	register_proc_cpuinfo_notifier(&fn##_nb);			\
91 })
92 
93 struct proc_cpuinfo_notifier_args {
94 	struct seq_file *m;
95 	unsigned long n;
96 };
97 
98 static inline bool cpus_are_siblings(int cpua, int cpub)
99 {
100 	struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
101 	struct cpuinfo_loongarch *infob = &cpu_data[cpub];
102 
103 	if (infoa->package != infob->package)
104 		return false;
105 
106 	if (infoa->core != infob->core)
107 		return false;
108 
109 	return true;
110 }
111 
112 static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
113 {
114 	return cpuinfo->asid_mask;
115 }
116 
117 static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
118 				     unsigned long asid_mask)
119 {
120 	cpuinfo->asid_mask = asid_mask;
121 }
122 
123 #endif /* __ASM_CPU_INFO_H */
124