1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Cache operations for the cache instruction. 4 * 5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 6 */ 7 #ifndef __ASM_CACHEOPS_H 8 #define __ASM_CACHEOPS_H 9 10 /* 11 * Most cache ops are split into a 2 bit field identifying the cache, and a 3 12 * bit field identifying the cache operation. 13 */ 14 #define CacheOp_Cache 0x03 15 #define CacheOp_Op 0x1c 16 17 #define Cache_I 0x00 18 #define Cache_D 0x01 19 #define Cache_V 0x02 20 #define Cache_S 0x03 21 22 #define Index_Invalidate 0x08 23 #define Index_Writeback_Inv 0x08 24 #define Hit_Invalidate 0x10 25 #define Hit_Writeback_Inv 0x10 26 #define CacheOp_User_Defined 0x18 27 28 #define Index_Invalidate_I (Cache_I | Index_Invalidate) 29 #define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv) 30 #define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv) 31 #define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv) 32 #define Hit_Invalidate_I (Cache_I | Hit_Invalidate) 33 #define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv) 34 #define Hit_Writeback_Inv_V (Cache_V | Hit_Writeback_Inv) 35 #define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv) 36 37 #endif /* __ASM_CACHEOPS_H */ 38