xref: /openbmc/linux/arch/ia64/pci/pci.c (revision b6dcefde)
1 /*
2  * pci.c - Low-Level PCI Access in IA-64
3  *
4  * Derived from bios32.c of i386 tree.
5  *
6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7  *	David Mosberger-Tang <davidm@hpl.hp.com>
8  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
9  * Copyright (C) 2004 Silicon Graphics, Inc.
10  *
11  * Note: Above list of copyright holders is incomplete...
12  */
13 
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/bootmem.h>
23 
24 #include <asm/machvec.h>
25 #include <asm/page.h>
26 #include <asm/system.h>
27 #include <asm/io.h>
28 #include <asm/sal.h>
29 #include <asm/smp.h>
30 #include <asm/irq.h>
31 #include <asm/hw_irq.h>
32 
33 /*
34  * Low-level SAL-based PCI configuration access functions. Note that SAL
35  * calls are already serialized (via sal_lock), so we don't need another
36  * synchronization mechanism here.
37  */
38 
39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)		\
40 	(((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
41 
42 /* SAL 3.2 adds support for extended config space. */
43 
44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)	\
45 	(((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
46 
47 int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
48 	      int reg, int len, u32 *value)
49 {
50 	u64 addr, data = 0;
51 	int mode, result;
52 
53 	if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
54 		return -EINVAL;
55 
56 	if ((seg | reg) <= 255) {
57 		addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
58 		mode = 0;
59 	} else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
60 		addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
61 		mode = 1;
62 	} else {
63 		return -EINVAL;
64 	}
65 
66 	result = ia64_sal_pci_config_read(addr, mode, len, &data);
67 	if (result != 0)
68 		return -EINVAL;
69 
70 	*value = (u32) data;
71 	return 0;
72 }
73 
74 int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
75 	       int reg, int len, u32 value)
76 {
77 	u64 addr;
78 	int mode, result;
79 
80 	if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
81 		return -EINVAL;
82 
83 	if ((seg | reg) <= 255) {
84 		addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
85 		mode = 0;
86 	} else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
87 		addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
88 		mode = 1;
89 	} else {
90 		return -EINVAL;
91 	}
92 	result = ia64_sal_pci_config_write(addr, mode, len, value);
93 	if (result != 0)
94 		return -EINVAL;
95 	return 0;
96 }
97 
98 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
99 							int size, u32 *value)
100 {
101 	return raw_pci_read(pci_domain_nr(bus), bus->number,
102 				 devfn, where, size, value);
103 }
104 
105 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
106 							int size, u32 value)
107 {
108 	return raw_pci_write(pci_domain_nr(bus), bus->number,
109 				  devfn, where, size, value);
110 }
111 
112 struct pci_ops pci_root_ops = {
113 	.read = pci_read,
114 	.write = pci_write,
115 };
116 
117 /* Called by ACPI when it finds a new root bus.  */
118 
119 static struct pci_controller * __devinit
120 alloc_pci_controller (int seg)
121 {
122 	struct pci_controller *controller;
123 
124 	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
125 	if (!controller)
126 		return NULL;
127 
128 	controller->segment = seg;
129 	controller->node = -1;
130 	return controller;
131 }
132 
133 struct pci_root_info {
134 	struct acpi_device *bridge;
135 	struct pci_controller *controller;
136 	char *name;
137 };
138 
139 static unsigned int
140 new_space (u64 phys_base, int sparse)
141 {
142 	u64 mmio_base;
143 	int i;
144 
145 	if (phys_base == 0)
146 		return 0;	/* legacy I/O port space */
147 
148 	mmio_base = (u64) ioremap(phys_base, 0);
149 	for (i = 0; i < num_io_spaces; i++)
150 		if (io_space[i].mmio_base == mmio_base &&
151 		    io_space[i].sparse == sparse)
152 			return i;
153 
154 	if (num_io_spaces == MAX_IO_SPACES) {
155 		printk(KERN_ERR "PCI: Too many IO port spaces "
156 			"(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
157 		return ~0;
158 	}
159 
160 	i = num_io_spaces++;
161 	io_space[i].mmio_base = mmio_base;
162 	io_space[i].sparse = sparse;
163 
164 	return i;
165 }
166 
167 static u64 __devinit
168 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
169 {
170 	struct resource *resource;
171 	char *name;
172 	unsigned long base, min, max, base_port;
173 	unsigned int sparse = 0, space_nr, len;
174 
175 	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
176 	if (!resource) {
177 		printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
178 			info->name);
179 		goto out;
180 	}
181 
182 	len = strlen(info->name) + 32;
183 	name = kzalloc(len, GFP_KERNEL);
184 	if (!name) {
185 		printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
186 			info->name);
187 		goto free_resource;
188 	}
189 
190 	min = addr->minimum;
191 	max = min + addr->address_length - 1;
192 	if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
193 		sparse = 1;
194 
195 	space_nr = new_space(addr->translation_offset, sparse);
196 	if (space_nr == ~0)
197 		goto free_name;
198 
199 	base = __pa(io_space[space_nr].mmio_base);
200 	base_port = IO_SPACE_BASE(space_nr);
201 	snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
202 		base_port + min, base_port + max);
203 
204 	/*
205 	 * The SDM guarantees the legacy 0-64K space is sparse, but if the
206 	 * mapping is done by the processor (not the bridge), ACPI may not
207 	 * mark it as sparse.
208 	 */
209 	if (space_nr == 0)
210 		sparse = 1;
211 
212 	resource->name  = name;
213 	resource->flags = IORESOURCE_MEM;
214 	resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
215 	resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
216 	insert_resource(&iomem_resource, resource);
217 
218 	return base_port;
219 
220 free_name:
221 	kfree(name);
222 free_resource:
223 	kfree(resource);
224 out:
225 	return ~0;
226 }
227 
228 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
229 	struct acpi_resource_address64 *addr)
230 {
231 	acpi_status status;
232 
233 	/*
234 	 * We're only interested in _CRS descriptors that are
235 	 *	- address space descriptors for memory or I/O space
236 	 *	- non-zero size
237 	 *	- producers, i.e., the address space is routed downstream,
238 	 *	  not consumed by the bridge itself
239 	 */
240 	status = acpi_resource_to_address64(resource, addr);
241 	if (ACPI_SUCCESS(status) &&
242 	    (addr->resource_type == ACPI_MEMORY_RANGE ||
243 	     addr->resource_type == ACPI_IO_RANGE) &&
244 	    addr->address_length &&
245 	    addr->producer_consumer == ACPI_PRODUCER)
246 		return AE_OK;
247 
248 	return AE_ERROR;
249 }
250 
251 static acpi_status __devinit
252 count_window (struct acpi_resource *resource, void *data)
253 {
254 	unsigned int *windows = (unsigned int *) data;
255 	struct acpi_resource_address64 addr;
256 	acpi_status status;
257 
258 	status = resource_to_window(resource, &addr);
259 	if (ACPI_SUCCESS(status))
260 		(*windows)++;
261 
262 	return AE_OK;
263 }
264 
265 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
266 {
267 	struct pci_root_info *info = data;
268 	struct pci_window *window;
269 	struct acpi_resource_address64 addr;
270 	acpi_status status;
271 	unsigned long flags, offset = 0;
272 	struct resource *root;
273 
274 	/* Return AE_OK for non-window resources to keep scanning for more */
275 	status = resource_to_window(res, &addr);
276 	if (!ACPI_SUCCESS(status))
277 		return AE_OK;
278 
279 	if (addr.resource_type == ACPI_MEMORY_RANGE) {
280 		flags = IORESOURCE_MEM;
281 		root = &iomem_resource;
282 		offset = addr.translation_offset;
283 	} else if (addr.resource_type == ACPI_IO_RANGE) {
284 		flags = IORESOURCE_IO;
285 		root = &ioport_resource;
286 		offset = add_io_space(info, &addr);
287 		if (offset == ~0)
288 			return AE_OK;
289 	} else
290 		return AE_OK;
291 
292 	window = &info->controller->window[info->controller->windows++];
293 	window->resource.name = info->name;
294 	window->resource.flags = flags;
295 	window->resource.start = addr.minimum + offset;
296 	window->resource.end = window->resource.start + addr.address_length - 1;
297 	window->resource.child = NULL;
298 	window->offset = offset;
299 
300 	if (insert_resource(root, &window->resource)) {
301 		dev_err(&info->bridge->dev,
302 			"can't allocate host bridge window %pR\n",
303 			&window->resource);
304 	} else {
305 		if (offset)
306 			dev_info(&info->bridge->dev, "host bridge window %pR "
307 				 "(PCI address [%#llx-%#llx])\n",
308 				 &window->resource,
309 				 window->resource.start - offset,
310 				 window->resource.end - offset);
311 		else
312 			dev_info(&info->bridge->dev,
313 				 "host bridge window %pR\n",
314 				 &window->resource);
315 	}
316 
317 	return AE_OK;
318 }
319 
320 static void __devinit
321 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
322 {
323 	int i, j;
324 
325 	j = 0;
326 	for (i = 0; i < ctrl->windows; i++) {
327 		struct resource *res = &ctrl->window[i].resource;
328 		/* HP's firmware has a hack to work around a Windows bug.
329 		 * Ignore these tiny memory ranges */
330 		if ((res->flags & IORESOURCE_MEM) &&
331 		    (res->end - res->start < 16))
332 			continue;
333 		if (j >= PCI_BUS_NUM_RESOURCES) {
334 			dev_warn(&bus->dev,
335 				 "ignoring host bridge window %pR (no space)\n",
336 				 res);
337 			continue;
338 		}
339 		bus->resource[j++] = res;
340 	}
341 }
342 
343 struct pci_bus * __devinit
344 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
345 {
346 	struct pci_controller *controller;
347 	unsigned int windows = 0;
348 	struct pci_bus *pbus;
349 	char *name;
350 	int pxm;
351 
352 	controller = alloc_pci_controller(domain);
353 	if (!controller)
354 		goto out1;
355 
356 	controller->acpi_handle = device->handle;
357 
358 	pxm = acpi_get_pxm(controller->acpi_handle);
359 #ifdef CONFIG_NUMA
360 	if (pxm >= 0)
361 		controller->node = pxm_to_node(pxm);
362 #endif
363 
364 	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
365 			&windows);
366 	if (windows) {
367 		struct pci_root_info info;
368 
369 		controller->window =
370 			kmalloc_node(sizeof(*controller->window) * windows,
371 				     GFP_KERNEL, controller->node);
372 		if (!controller->window)
373 			goto out2;
374 
375 		name = kmalloc(16, GFP_KERNEL);
376 		if (!name)
377 			goto out3;
378 
379 		sprintf(name, "PCI Bus %04x:%02x", domain, bus);
380 		info.bridge = device;
381 		info.controller = controller;
382 		info.name = name;
383 		acpi_walk_resources(device->handle, METHOD_NAME__CRS,
384 			add_window, &info);
385 	}
386 	/*
387 	 * See arch/x86/pci/acpi.c.
388 	 * The desired pci bus might already be scanned in a quirk. We
389 	 * should handle the case here, but it appears that IA64 hasn't
390 	 * such quirk. So we just ignore the case now.
391 	 */
392 	pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
393 
394 	return pbus;
395 
396 out3:
397 	kfree(controller->window);
398 out2:
399 	kfree(controller);
400 out1:
401 	return NULL;
402 }
403 
404 void pcibios_resource_to_bus(struct pci_dev *dev,
405 		struct pci_bus_region *region, struct resource *res)
406 {
407 	struct pci_controller *controller = PCI_CONTROLLER(dev);
408 	unsigned long offset = 0;
409 	int i;
410 
411 	for (i = 0; i < controller->windows; i++) {
412 		struct pci_window *window = &controller->window[i];
413 		if (!(window->resource.flags & res->flags))
414 			continue;
415 		if (window->resource.start > res->start)
416 			continue;
417 		if (window->resource.end < res->end)
418 			continue;
419 		offset = window->offset;
420 		break;
421 	}
422 
423 	region->start = res->start - offset;
424 	region->end = res->end - offset;
425 }
426 EXPORT_SYMBOL(pcibios_resource_to_bus);
427 
428 void pcibios_bus_to_resource(struct pci_dev *dev,
429 		struct resource *res, struct pci_bus_region *region)
430 {
431 	struct pci_controller *controller = PCI_CONTROLLER(dev);
432 	unsigned long offset = 0;
433 	int i;
434 
435 	for (i = 0; i < controller->windows; i++) {
436 		struct pci_window *window = &controller->window[i];
437 		if (!(window->resource.flags & res->flags))
438 			continue;
439 		if (window->resource.start - window->offset > region->start)
440 			continue;
441 		if (window->resource.end - window->offset < region->end)
442 			continue;
443 		offset = window->offset;
444 		break;
445 	}
446 
447 	res->start = region->start + offset;
448 	res->end = region->end + offset;
449 }
450 EXPORT_SYMBOL(pcibios_bus_to_resource);
451 
452 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
453 {
454 	unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
455 	struct resource *devr = &dev->resource[idx];
456 
457 	if (!dev->bus)
458 		return 0;
459 	for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
460 		struct resource *busr = dev->bus->resource[i];
461 
462 		if (!busr || ((busr->flags ^ devr->flags) & type_mask))
463 			continue;
464 		if ((devr->start) && (devr->start >= busr->start) &&
465 				(devr->end <= busr->end))
466 			return 1;
467 	}
468 	return 0;
469 }
470 
471 static void __devinit
472 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
473 {
474 	struct pci_bus_region region;
475 	int i;
476 
477 	for (i = start; i < limit; i++) {
478 		if (!dev->resource[i].flags)
479 			continue;
480 		region.start = dev->resource[i].start;
481 		region.end = dev->resource[i].end;
482 		pcibios_bus_to_resource(dev, &dev->resource[i], &region);
483 		if ((is_valid_resource(dev, i)))
484 			pci_claim_resource(dev, i);
485 	}
486 }
487 
488 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
489 {
490 	pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
491 }
492 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
493 
494 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
495 {
496 	pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
497 }
498 
499 /*
500  *  Called after each bus is probed, but before its children are examined.
501  */
502 void __devinit
503 pcibios_fixup_bus (struct pci_bus *b)
504 {
505 	struct pci_dev *dev;
506 
507 	if (b->self) {
508 		pci_read_bridge_bases(b);
509 		pcibios_fixup_bridge_resources(b->self);
510 	} else {
511 		pcibios_setup_root_windows(b, b->sysdata);
512 	}
513 	list_for_each_entry(dev, &b->devices, bus_list)
514 		pcibios_fixup_device_resources(dev);
515 	platform_pci_fixup_bus(b);
516 
517 	return;
518 }
519 
520 void __devinit
521 pcibios_update_irq (struct pci_dev *dev, int irq)
522 {
523 	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
524 
525 	/* ??? FIXME -- record old value for shutdown.  */
526 }
527 
528 int
529 pcibios_enable_device (struct pci_dev *dev, int mask)
530 {
531 	int ret;
532 
533 	ret = pci_enable_resources(dev, mask);
534 	if (ret < 0)
535 		return ret;
536 
537 	if (!dev->msi_enabled)
538 		return acpi_pci_irq_enable(dev);
539 	return 0;
540 }
541 
542 void
543 pcibios_disable_device (struct pci_dev *dev)
544 {
545 	BUG_ON(atomic_read(&dev->enable_cnt));
546 	if (!dev->msi_enabled)
547 		acpi_pci_irq_disable(dev);
548 }
549 
550 void
551 pcibios_align_resource (void *data, struct resource *res,
552 		        resource_size_t size, resource_size_t align)
553 {
554 }
555 
556 /*
557  * PCI BIOS setup, always defaults to SAL interface
558  */
559 char * __init
560 pcibios_setup (char *str)
561 {
562 	return str;
563 }
564 
565 int
566 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
567 		     enum pci_mmap_state mmap_state, int write_combine)
568 {
569 	unsigned long size = vma->vm_end - vma->vm_start;
570 	pgprot_t prot;
571 
572 	/*
573 	 * I/O space cannot be accessed via normal processor loads and
574 	 * stores on this platform.
575 	 */
576 	if (mmap_state == pci_mmap_io)
577 		/*
578 		 * XXX we could relax this for I/O spaces for which ACPI
579 		 * indicates that the space is 1-to-1 mapped.  But at the
580 		 * moment, we don't support multiple PCI address spaces and
581 		 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
582 		 */
583 		return -EINVAL;
584 
585 	if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
586 		return -EINVAL;
587 
588 	prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
589 				    vma->vm_page_prot);
590 
591 	/*
592 	 * If the user requested WC, the kernel uses UC or WC for this region,
593 	 * and the chipset supports WC, we can use WC. Otherwise, we have to
594 	 * use the same attribute the kernel uses.
595 	 */
596 	if (write_combine &&
597 	    ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
598 	     (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
599 	    efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
600 		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
601 	else
602 		vma->vm_page_prot = prot;
603 
604 	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
605 			     vma->vm_end - vma->vm_start, vma->vm_page_prot))
606 		return -EAGAIN;
607 
608 	return 0;
609 }
610 
611 /**
612  * ia64_pci_get_legacy_mem - generic legacy mem routine
613  * @bus: bus to get legacy memory base address for
614  *
615  * Find the base of legacy memory for @bus.  This is typically the first
616  * megabyte of bus address space for @bus or is simply 0 on platforms whose
617  * chipsets support legacy I/O and memory routing.  Returns the base address
618  * or an error pointer if an error occurred.
619  *
620  * This is the ia64 generic version of this routine.  Other platforms
621  * are free to override it with a machine vector.
622  */
623 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
624 {
625 	return (char *)__IA64_UNCACHED_OFFSET;
626 }
627 
628 /**
629  * pci_mmap_legacy_page_range - map legacy memory space to userland
630  * @bus: bus whose legacy space we're mapping
631  * @vma: vma passed in by mmap
632  *
633  * Map legacy memory space for this device back to userspace using a machine
634  * vector to get the base address.
635  */
636 int
637 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
638 			   enum pci_mmap_state mmap_state)
639 {
640 	unsigned long size = vma->vm_end - vma->vm_start;
641 	pgprot_t prot;
642 	char *addr;
643 
644 	/* We only support mmap'ing of legacy memory space */
645 	if (mmap_state != pci_mmap_mem)
646 		return -ENOSYS;
647 
648 	/*
649 	 * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
650 	 * for more details.
651 	 */
652 	if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
653 		return -EINVAL;
654 	prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
655 				    vma->vm_page_prot);
656 
657 	addr = pci_get_legacy_mem(bus);
658 	if (IS_ERR(addr))
659 		return PTR_ERR(addr);
660 
661 	vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
662 	vma->vm_page_prot = prot;
663 
664 	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
665 			    size, vma->vm_page_prot))
666 		return -EAGAIN;
667 
668 	return 0;
669 }
670 
671 /**
672  * ia64_pci_legacy_read - read from legacy I/O space
673  * @bus: bus to read
674  * @port: legacy port value
675  * @val: caller allocated storage for returned value
676  * @size: number of bytes to read
677  *
678  * Simply reads @size bytes from @port and puts the result in @val.
679  *
680  * Again, this (and the write routine) are generic versions that can be
681  * overridden by the platform.  This is necessary on platforms that don't
682  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
683  */
684 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
685 {
686 	int ret = size;
687 
688 	switch (size) {
689 	case 1:
690 		*val = inb(port);
691 		break;
692 	case 2:
693 		*val = inw(port);
694 		break;
695 	case 4:
696 		*val = inl(port);
697 		break;
698 	default:
699 		ret = -EINVAL;
700 		break;
701 	}
702 
703 	return ret;
704 }
705 
706 /**
707  * ia64_pci_legacy_write - perform a legacy I/O write
708  * @bus: bus pointer
709  * @port: port to write
710  * @val: value to write
711  * @size: number of bytes to write from @val
712  *
713  * Simply writes @size bytes of @val to @port.
714  */
715 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
716 {
717 	int ret = size;
718 
719 	switch (size) {
720 	case 1:
721 		outb(val, port);
722 		break;
723 	case 2:
724 		outw(val, port);
725 		break;
726 	case 4:
727 		outl(val, port);
728 		break;
729 	default:
730 		ret = -EINVAL;
731 		break;
732 	}
733 
734 	return ret;
735 }
736 
737 /**
738  * set_pci_cacheline_size - determine cacheline size for PCI devices
739  *
740  * We want to use the line-size of the outer-most cache.  We assume
741  * that this line-size is the same for all CPUs.
742  *
743  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
744  */
745 static void __init set_pci_dfl_cacheline_size(void)
746 {
747 	unsigned long levels, unique_caches;
748 	long status;
749 	pal_cache_config_info_t cci;
750 
751 	status = ia64_pal_cache_summary(&levels, &unique_caches);
752 	if (status != 0) {
753 		printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
754 			"(status=%ld)\n", __func__, status);
755 		return;
756 	}
757 
758 	status = ia64_pal_cache_config_info(levels - 1,
759 				/* cache_type (data_or_unified)= */ 2, &cci);
760 	if (status != 0) {
761 		printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
762 			"(status=%ld)\n", __func__, status);
763 		return;
764 	}
765 	pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
766 }
767 
768 u64 ia64_dma_get_required_mask(struct device *dev)
769 {
770 	u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
771 	u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
772 	u64 mask;
773 
774 	if (!high_totalram) {
775 		/* convert to mask just covering totalram */
776 		low_totalram = (1 << (fls(low_totalram) - 1));
777 		low_totalram += low_totalram - 1;
778 		mask = low_totalram;
779 	} else {
780 		high_totalram = (1 << (fls(high_totalram) - 1));
781 		high_totalram += high_totalram - 1;
782 		mask = (((u64)high_totalram) << 32) + 0xffffffff;
783 	}
784 	return mask;
785 }
786 EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
787 
788 u64 dma_get_required_mask(struct device *dev)
789 {
790 	return platform_dma_get_required_mask(dev);
791 }
792 EXPORT_SYMBOL_GPL(dma_get_required_mask);
793 
794 static int __init pcibios_init(void)
795 {
796 	set_pci_dfl_cacheline_size();
797 	return 0;
798 }
799 
800 subsys_initcall(pcibios_init);
801