1 /* 2 * pci.c - Low-Level PCI Access in IA-64 3 * 4 * Derived from bios32.c of i386 tree. 5 * 6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. 7 * David Mosberger-Tang <davidm@hpl.hp.com> 8 * Bjorn Helgaas <bjorn.helgaas@hp.com> 9 * Copyright (C) 2004 Silicon Graphics, Inc. 10 * 11 * Note: Above list of copyright holders is incomplete... 12 */ 13 14 #include <linux/acpi.h> 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/ioport.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/bootmem.h> 23 24 #include <asm/machvec.h> 25 #include <asm/page.h> 26 #include <asm/system.h> 27 #include <asm/io.h> 28 #include <asm/sal.h> 29 #include <asm/smp.h> 30 #include <asm/irq.h> 31 #include <asm/hw_irq.h> 32 33 /* 34 * Low-level SAL-based PCI configuration access functions. Note that SAL 35 * calls are already serialized (via sal_lock), so we don't need another 36 * synchronization mechanism here. 37 */ 38 39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ 40 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) 41 42 /* SAL 3.2 adds support for extended config space. */ 43 44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ 45 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) 46 47 int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, 48 int reg, int len, u32 *value) 49 { 50 u64 addr, data = 0; 51 int mode, result; 52 53 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) 54 return -EINVAL; 55 56 if ((seg | reg) <= 255) { 57 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); 58 mode = 0; 59 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { 60 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); 61 mode = 1; 62 } else { 63 return -EINVAL; 64 } 65 66 result = ia64_sal_pci_config_read(addr, mode, len, &data); 67 if (result != 0) 68 return -EINVAL; 69 70 *value = (u32) data; 71 return 0; 72 } 73 74 int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, 75 int reg, int len, u32 value) 76 { 77 u64 addr; 78 int mode, result; 79 80 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) 81 return -EINVAL; 82 83 if ((seg | reg) <= 255) { 84 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); 85 mode = 0; 86 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { 87 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); 88 mode = 1; 89 } else { 90 return -EINVAL; 91 } 92 result = ia64_sal_pci_config_write(addr, mode, len, value); 93 if (result != 0) 94 return -EINVAL; 95 return 0; 96 } 97 98 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, 99 int size, u32 *value) 100 { 101 return raw_pci_read(pci_domain_nr(bus), bus->number, 102 devfn, where, size, value); 103 } 104 105 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, 106 int size, u32 value) 107 { 108 return raw_pci_write(pci_domain_nr(bus), bus->number, 109 devfn, where, size, value); 110 } 111 112 struct pci_ops pci_root_ops = { 113 .read = pci_read, 114 .write = pci_write, 115 }; 116 117 /* Called by ACPI when it finds a new root bus. */ 118 119 static struct pci_controller * __devinit 120 alloc_pci_controller (int seg) 121 { 122 struct pci_controller *controller; 123 124 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 125 if (!controller) 126 return NULL; 127 128 controller->segment = seg; 129 controller->node = -1; 130 return controller; 131 } 132 133 struct pci_root_info { 134 struct acpi_device *bridge; 135 struct pci_controller *controller; 136 char *name; 137 }; 138 139 static unsigned int 140 new_space (u64 phys_base, int sparse) 141 { 142 u64 mmio_base; 143 int i; 144 145 if (phys_base == 0) 146 return 0; /* legacy I/O port space */ 147 148 mmio_base = (u64) ioremap(phys_base, 0); 149 for (i = 0; i < num_io_spaces; i++) 150 if (io_space[i].mmio_base == mmio_base && 151 io_space[i].sparse == sparse) 152 return i; 153 154 if (num_io_spaces == MAX_IO_SPACES) { 155 printk(KERN_ERR "PCI: Too many IO port spaces " 156 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); 157 return ~0; 158 } 159 160 i = num_io_spaces++; 161 io_space[i].mmio_base = mmio_base; 162 io_space[i].sparse = sparse; 163 164 return i; 165 } 166 167 static u64 __devinit 168 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) 169 { 170 struct resource *resource; 171 char *name; 172 unsigned long base, min, max, base_port; 173 unsigned int sparse = 0, space_nr, len; 174 175 resource = kzalloc(sizeof(*resource), GFP_KERNEL); 176 if (!resource) { 177 printk(KERN_ERR "PCI: No memory for %s I/O port space\n", 178 info->name); 179 goto out; 180 } 181 182 len = strlen(info->name) + 32; 183 name = kzalloc(len, GFP_KERNEL); 184 if (!name) { 185 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", 186 info->name); 187 goto free_resource; 188 } 189 190 min = addr->minimum; 191 max = min + addr->address_length - 1; 192 if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) 193 sparse = 1; 194 195 space_nr = new_space(addr->translation_offset, sparse); 196 if (space_nr == ~0) 197 goto free_name; 198 199 base = __pa(io_space[space_nr].mmio_base); 200 base_port = IO_SPACE_BASE(space_nr); 201 snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, 202 base_port + min, base_port + max); 203 204 /* 205 * The SDM guarantees the legacy 0-64K space is sparse, but if the 206 * mapping is done by the processor (not the bridge), ACPI may not 207 * mark it as sparse. 208 */ 209 if (space_nr == 0) 210 sparse = 1; 211 212 resource->name = name; 213 resource->flags = IORESOURCE_MEM; 214 resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); 215 resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); 216 insert_resource(&iomem_resource, resource); 217 218 return base_port; 219 220 free_name: 221 kfree(name); 222 free_resource: 223 kfree(resource); 224 out: 225 return ~0; 226 } 227 228 static acpi_status __devinit resource_to_window(struct acpi_resource *resource, 229 struct acpi_resource_address64 *addr) 230 { 231 acpi_status status; 232 233 /* 234 * We're only interested in _CRS descriptors that are 235 * - address space descriptors for memory or I/O space 236 * - non-zero size 237 * - producers, i.e., the address space is routed downstream, 238 * not consumed by the bridge itself 239 */ 240 status = acpi_resource_to_address64(resource, addr); 241 if (ACPI_SUCCESS(status) && 242 (addr->resource_type == ACPI_MEMORY_RANGE || 243 addr->resource_type == ACPI_IO_RANGE) && 244 addr->address_length && 245 addr->producer_consumer == ACPI_PRODUCER) 246 return AE_OK; 247 248 return AE_ERROR; 249 } 250 251 static acpi_status __devinit 252 count_window (struct acpi_resource *resource, void *data) 253 { 254 unsigned int *windows = (unsigned int *) data; 255 struct acpi_resource_address64 addr; 256 acpi_status status; 257 258 status = resource_to_window(resource, &addr); 259 if (ACPI_SUCCESS(status)) 260 (*windows)++; 261 262 return AE_OK; 263 } 264 265 static __devinit acpi_status add_window(struct acpi_resource *res, void *data) 266 { 267 struct pci_root_info *info = data; 268 struct pci_window *window; 269 struct acpi_resource_address64 addr; 270 acpi_status status; 271 unsigned long flags, offset = 0; 272 struct resource *root; 273 274 /* Return AE_OK for non-window resources to keep scanning for more */ 275 status = resource_to_window(res, &addr); 276 if (!ACPI_SUCCESS(status)) 277 return AE_OK; 278 279 if (addr.resource_type == ACPI_MEMORY_RANGE) { 280 flags = IORESOURCE_MEM; 281 root = &iomem_resource; 282 offset = addr.translation_offset; 283 } else if (addr.resource_type == ACPI_IO_RANGE) { 284 flags = IORESOURCE_IO; 285 root = &ioport_resource; 286 offset = add_io_space(info, &addr); 287 if (offset == ~0) 288 return AE_OK; 289 } else 290 return AE_OK; 291 292 window = &info->controller->window[info->controller->windows++]; 293 window->resource.name = info->name; 294 window->resource.flags = flags; 295 window->resource.start = addr.minimum + offset; 296 window->resource.end = window->resource.start + addr.address_length - 1; 297 window->resource.child = NULL; 298 window->offset = offset; 299 300 if (insert_resource(root, &window->resource)) { 301 dev_err(&info->bridge->dev, 302 "can't allocate host bridge window %pR\n", 303 &window->resource); 304 } else { 305 if (offset) 306 dev_info(&info->bridge->dev, "host bridge window %pR " 307 "(PCI address [%#llx-%#llx])\n", 308 &window->resource, 309 window->resource.start - offset, 310 window->resource.end - offset); 311 else 312 dev_info(&info->bridge->dev, 313 "host bridge window %pR\n", 314 &window->resource); 315 } 316 317 return AE_OK; 318 } 319 320 static void __devinit 321 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) 322 { 323 int i; 324 325 pci_bus_remove_resources(bus); 326 for (i = 0; i < ctrl->windows; i++) { 327 struct resource *res = &ctrl->window[i].resource; 328 /* HP's firmware has a hack to work around a Windows bug. 329 * Ignore these tiny memory ranges */ 330 if ((res->flags & IORESOURCE_MEM) && 331 (res->end - res->start < 16)) 332 continue; 333 pci_bus_add_resource(bus, res, 0); 334 } 335 } 336 337 struct pci_bus * __devinit 338 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) 339 { 340 struct pci_controller *controller; 341 unsigned int windows = 0; 342 struct pci_bus *pbus; 343 char *name; 344 int pxm; 345 346 controller = alloc_pci_controller(domain); 347 if (!controller) 348 goto out1; 349 350 controller->acpi_handle = device->handle; 351 352 pxm = acpi_get_pxm(controller->acpi_handle); 353 #ifdef CONFIG_NUMA 354 if (pxm >= 0) 355 controller->node = pxm_to_node(pxm); 356 #endif 357 358 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, 359 &windows); 360 if (windows) { 361 struct pci_root_info info; 362 363 controller->window = 364 kmalloc_node(sizeof(*controller->window) * windows, 365 GFP_KERNEL, controller->node); 366 if (!controller->window) 367 goto out2; 368 369 name = kmalloc(16, GFP_KERNEL); 370 if (!name) 371 goto out3; 372 373 sprintf(name, "PCI Bus %04x:%02x", domain, bus); 374 info.bridge = device; 375 info.controller = controller; 376 info.name = name; 377 acpi_walk_resources(device->handle, METHOD_NAME__CRS, 378 add_window, &info); 379 } 380 /* 381 * See arch/x86/pci/acpi.c. 382 * The desired pci bus might already be scanned in a quirk. We 383 * should handle the case here, but it appears that IA64 hasn't 384 * such quirk. So we just ignore the case now. 385 */ 386 pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); 387 388 return pbus; 389 390 out3: 391 kfree(controller->window); 392 out2: 393 kfree(controller); 394 out1: 395 return NULL; 396 } 397 398 void pcibios_resource_to_bus(struct pci_dev *dev, 399 struct pci_bus_region *region, struct resource *res) 400 { 401 struct pci_controller *controller = PCI_CONTROLLER(dev); 402 unsigned long offset = 0; 403 int i; 404 405 for (i = 0; i < controller->windows; i++) { 406 struct pci_window *window = &controller->window[i]; 407 if (!(window->resource.flags & res->flags)) 408 continue; 409 if (window->resource.start > res->start) 410 continue; 411 if (window->resource.end < res->end) 412 continue; 413 offset = window->offset; 414 break; 415 } 416 417 region->start = res->start - offset; 418 region->end = res->end - offset; 419 } 420 EXPORT_SYMBOL(pcibios_resource_to_bus); 421 422 void pcibios_bus_to_resource(struct pci_dev *dev, 423 struct resource *res, struct pci_bus_region *region) 424 { 425 struct pci_controller *controller = PCI_CONTROLLER(dev); 426 unsigned long offset = 0; 427 int i; 428 429 for (i = 0; i < controller->windows; i++) { 430 struct pci_window *window = &controller->window[i]; 431 if (!(window->resource.flags & res->flags)) 432 continue; 433 if (window->resource.start - window->offset > region->start) 434 continue; 435 if (window->resource.end - window->offset < region->end) 436 continue; 437 offset = window->offset; 438 break; 439 } 440 441 res->start = region->start + offset; 442 res->end = region->end + offset; 443 } 444 EXPORT_SYMBOL(pcibios_bus_to_resource); 445 446 static int __devinit is_valid_resource(struct pci_dev *dev, int idx) 447 { 448 unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; 449 struct resource *devr = &dev->resource[idx], *busr; 450 451 if (!dev->bus) 452 return 0; 453 454 pci_bus_for_each_resource(dev->bus, busr, i) { 455 if (!busr || ((busr->flags ^ devr->flags) & type_mask)) 456 continue; 457 if ((devr->start) && (devr->start >= busr->start) && 458 (devr->end <= busr->end)) 459 return 1; 460 } 461 return 0; 462 } 463 464 static void __devinit 465 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) 466 { 467 struct pci_bus_region region; 468 int i; 469 470 for (i = start; i < limit; i++) { 471 if (!dev->resource[i].flags) 472 continue; 473 region.start = dev->resource[i].start; 474 region.end = dev->resource[i].end; 475 pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); 476 if ((is_valid_resource(dev, i))) 477 pci_claim_resource(dev, i); 478 } 479 } 480 481 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) 482 { 483 pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); 484 } 485 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); 486 487 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) 488 { 489 pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); 490 } 491 492 /* 493 * Called after each bus is probed, but before its children are examined. 494 */ 495 void __devinit 496 pcibios_fixup_bus (struct pci_bus *b) 497 { 498 struct pci_dev *dev; 499 500 if (b->self) { 501 pci_read_bridge_bases(b); 502 pcibios_fixup_bridge_resources(b->self); 503 } else { 504 pcibios_setup_root_windows(b, b->sysdata); 505 } 506 list_for_each_entry(dev, &b->devices, bus_list) 507 pcibios_fixup_device_resources(dev); 508 platform_pci_fixup_bus(b); 509 510 return; 511 } 512 513 void __devinit 514 pcibios_update_irq (struct pci_dev *dev, int irq) 515 { 516 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 517 518 /* ??? FIXME -- record old value for shutdown. */ 519 } 520 521 int 522 pcibios_enable_device (struct pci_dev *dev, int mask) 523 { 524 int ret; 525 526 ret = pci_enable_resources(dev, mask); 527 if (ret < 0) 528 return ret; 529 530 if (!dev->msi_enabled) 531 return acpi_pci_irq_enable(dev); 532 return 0; 533 } 534 535 void 536 pcibios_disable_device (struct pci_dev *dev) 537 { 538 BUG_ON(atomic_read(&dev->enable_cnt)); 539 if (!dev->msi_enabled) 540 acpi_pci_irq_disable(dev); 541 } 542 543 resource_size_t 544 pcibios_align_resource (void *data, const struct resource *res, 545 resource_size_t size, resource_size_t align) 546 { 547 return res->start; 548 } 549 550 /* 551 * PCI BIOS setup, always defaults to SAL interface 552 */ 553 char * __init 554 pcibios_setup (char *str) 555 { 556 return str; 557 } 558 559 int 560 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, 561 enum pci_mmap_state mmap_state, int write_combine) 562 { 563 unsigned long size = vma->vm_end - vma->vm_start; 564 pgprot_t prot; 565 566 /* 567 * I/O space cannot be accessed via normal processor loads and 568 * stores on this platform. 569 */ 570 if (mmap_state == pci_mmap_io) 571 /* 572 * XXX we could relax this for I/O spaces for which ACPI 573 * indicates that the space is 1-to-1 mapped. But at the 574 * moment, we don't support multiple PCI address spaces and 575 * the legacy I/O space is not 1-to-1 mapped, so this is moot. 576 */ 577 return -EINVAL; 578 579 if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) 580 return -EINVAL; 581 582 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, 583 vma->vm_page_prot); 584 585 /* 586 * If the user requested WC, the kernel uses UC or WC for this region, 587 * and the chipset supports WC, we can use WC. Otherwise, we have to 588 * use the same attribute the kernel uses. 589 */ 590 if (write_combine && 591 ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || 592 (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && 593 efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) 594 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 595 else 596 vma->vm_page_prot = prot; 597 598 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 599 vma->vm_end - vma->vm_start, vma->vm_page_prot)) 600 return -EAGAIN; 601 602 return 0; 603 } 604 605 /** 606 * ia64_pci_get_legacy_mem - generic legacy mem routine 607 * @bus: bus to get legacy memory base address for 608 * 609 * Find the base of legacy memory for @bus. This is typically the first 610 * megabyte of bus address space for @bus or is simply 0 on platforms whose 611 * chipsets support legacy I/O and memory routing. Returns the base address 612 * or an error pointer if an error occurred. 613 * 614 * This is the ia64 generic version of this routine. Other platforms 615 * are free to override it with a machine vector. 616 */ 617 char *ia64_pci_get_legacy_mem(struct pci_bus *bus) 618 { 619 return (char *)__IA64_UNCACHED_OFFSET; 620 } 621 622 /** 623 * pci_mmap_legacy_page_range - map legacy memory space to userland 624 * @bus: bus whose legacy space we're mapping 625 * @vma: vma passed in by mmap 626 * 627 * Map legacy memory space for this device back to userspace using a machine 628 * vector to get the base address. 629 */ 630 int 631 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, 632 enum pci_mmap_state mmap_state) 633 { 634 unsigned long size = vma->vm_end - vma->vm_start; 635 pgprot_t prot; 636 char *addr; 637 638 /* We only support mmap'ing of legacy memory space */ 639 if (mmap_state != pci_mmap_mem) 640 return -ENOSYS; 641 642 /* 643 * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt 644 * for more details. 645 */ 646 if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) 647 return -EINVAL; 648 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, 649 vma->vm_page_prot); 650 651 addr = pci_get_legacy_mem(bus); 652 if (IS_ERR(addr)) 653 return PTR_ERR(addr); 654 655 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; 656 vma->vm_page_prot = prot; 657 658 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 659 size, vma->vm_page_prot)) 660 return -EAGAIN; 661 662 return 0; 663 } 664 665 /** 666 * ia64_pci_legacy_read - read from legacy I/O space 667 * @bus: bus to read 668 * @port: legacy port value 669 * @val: caller allocated storage for returned value 670 * @size: number of bytes to read 671 * 672 * Simply reads @size bytes from @port and puts the result in @val. 673 * 674 * Again, this (and the write routine) are generic versions that can be 675 * overridden by the platform. This is necessary on platforms that don't 676 * support legacy I/O routing or that hard fail on legacy I/O timeouts. 677 */ 678 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) 679 { 680 int ret = size; 681 682 switch (size) { 683 case 1: 684 *val = inb(port); 685 break; 686 case 2: 687 *val = inw(port); 688 break; 689 case 4: 690 *val = inl(port); 691 break; 692 default: 693 ret = -EINVAL; 694 break; 695 } 696 697 return ret; 698 } 699 700 /** 701 * ia64_pci_legacy_write - perform a legacy I/O write 702 * @bus: bus pointer 703 * @port: port to write 704 * @val: value to write 705 * @size: number of bytes to write from @val 706 * 707 * Simply writes @size bytes of @val to @port. 708 */ 709 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) 710 { 711 int ret = size; 712 713 switch (size) { 714 case 1: 715 outb(val, port); 716 break; 717 case 2: 718 outw(val, port); 719 break; 720 case 4: 721 outl(val, port); 722 break; 723 default: 724 ret = -EINVAL; 725 break; 726 } 727 728 return ret; 729 } 730 731 /** 732 * set_pci_cacheline_size - determine cacheline size for PCI devices 733 * 734 * We want to use the line-size of the outer-most cache. We assume 735 * that this line-size is the same for all CPUs. 736 * 737 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). 738 */ 739 static void __init set_pci_dfl_cacheline_size(void) 740 { 741 unsigned long levels, unique_caches; 742 long status; 743 pal_cache_config_info_t cci; 744 745 status = ia64_pal_cache_summary(&levels, &unique_caches); 746 if (status != 0) { 747 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " 748 "(status=%ld)\n", __func__, status); 749 return; 750 } 751 752 status = ia64_pal_cache_config_info(levels - 1, 753 /* cache_type (data_or_unified)= */ 2, &cci); 754 if (status != 0) { 755 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " 756 "(status=%ld)\n", __func__, status); 757 return; 758 } 759 pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4; 760 } 761 762 u64 ia64_dma_get_required_mask(struct device *dev) 763 { 764 u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); 765 u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); 766 u64 mask; 767 768 if (!high_totalram) { 769 /* convert to mask just covering totalram */ 770 low_totalram = (1 << (fls(low_totalram) - 1)); 771 low_totalram += low_totalram - 1; 772 mask = low_totalram; 773 } else { 774 high_totalram = (1 << (fls(high_totalram) - 1)); 775 high_totalram += high_totalram - 1; 776 mask = (((u64)high_totalram) << 32) + 0xffffffff; 777 } 778 return mask; 779 } 780 EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); 781 782 u64 dma_get_required_mask(struct device *dev) 783 { 784 return platform_dma_get_required_mask(dev); 785 } 786 EXPORT_SYMBOL_GPL(dma_get_required_mask); 787 788 static int __init pcibios_init(void) 789 { 790 set_pci_dfl_cacheline_size(); 791 return 0; 792 } 793 794 subsys_initcall(pcibios_init); 795