xref: /openbmc/linux/arch/ia64/mm/tlb.c (revision ed1666f6) 
1 /*
2  * TLB support routines.
3  *
4  * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5  *	David Mosberger-Tang <davidm@hpl.hp.com>
6  *
7  * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
8  *		Modified RID allocation for SMP
9  *          Goutham Rao <goutham.rao@intel.com>
10  *              IPI based ptc implementation and A-step IPI implementation.
11  * Rohit Seth <rohit.seth@intel.com>
12  * Ken Chen <kenneth.w.chen@intel.com>
13  * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
14  * Copyright (C) 2007 Intel Corp
15  *	Fenghua Yu <fenghua.yu@intel.com>
16  *	Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
17  */
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/smp.h>
23 #include <linux/mm.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 
27 #include <asm/delay.h>
28 #include <asm/mmu_context.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pal.h>
31 #include <asm/tlbflush.h>
32 #include <asm/dma.h>
33 #include <asm/processor.h>
34 #include <asm/sal.h>
35 #include <asm/tlb.h>
36 
37 static struct {
38 	u64 mask;		/* mask of supported purge page-sizes */
39 	unsigned long max_bits;	/* log2 of largest supported purge page-size */
40 } purge;
41 
42 struct ia64_ctx ia64_ctx = {
43 	.lock =	__SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
44 	.next =	1,
45 	.max_ctx = ~0U
46 };
47 
48 DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
49 DEFINE_PER_CPU(u8, ia64_tr_num);  /*Number of TR slots in current processor*/
50 DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
51 
52 struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
53 
54 /*
55  * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
56  * Called after cpu_init() has setup ia64_ctx.max_ctx based on
57  * maximum RID that is supported by boot CPU.
58  */
59 void __init
60 mmu_context_init (void)
61 {
62 	ia64_ctx.bitmap = memblock_alloc((ia64_ctx.max_ctx + 1) >> 3,
63 					 SMP_CACHE_BYTES);
64 	if (!ia64_ctx.bitmap)
65 		panic("%s: Failed to allocate %u bytes\n", __func__,
66 		      (ia64_ctx.max_ctx + 1) >> 3);
67 	ia64_ctx.flushmap = memblock_alloc((ia64_ctx.max_ctx + 1) >> 3,
68 					   SMP_CACHE_BYTES);
69 	if (!ia64_ctx.flushmap)
70 		panic("%s: Failed to allocate %u bytes\n", __func__,
71 		      (ia64_ctx.max_ctx + 1) >> 3);
72 }
73 
74 /*
75  * Acquire the ia64_ctx.lock before calling this function!
76  */
77 void
78 wrap_mmu_context (struct mm_struct *mm)
79 {
80 	int i, cpu;
81 	unsigned long flush_bit;
82 
83 	for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
84 		flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
85 		ia64_ctx.bitmap[i] ^= flush_bit;
86 	}
87 
88 	/* use offset at 300 to skip daemons */
89 	ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
90 				ia64_ctx.max_ctx, 300);
91 	ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
92 				ia64_ctx.max_ctx, ia64_ctx.next);
93 
94 	/*
95 	 * can't call flush_tlb_all() here because of race condition
96 	 * with O(1) scheduler [EF]
97 	 */
98 	cpu = get_cpu(); /* prevent preemption/migration */
99 	for_each_online_cpu(i)
100 		if (i != cpu)
101 			per_cpu(ia64_need_tlb_flush, i) = 1;
102 	put_cpu();
103 	local_flush_tlb_all();
104 }
105 
106 /*
107  * Implement "spinaphores" ... like counting semaphores, but they
108  * spin instead of sleeping.  If there are ever any other users for
109  * this primitive it can be moved up to a spinaphore.h header.
110  */
111 struct spinaphore {
112 	unsigned long	ticket;
113 	unsigned long	serve;
114 };
115 
116 static inline void spinaphore_init(struct spinaphore *ss, int val)
117 {
118 	ss->ticket = 0;
119 	ss->serve = val;
120 }
121 
122 static inline void down_spin(struct spinaphore *ss)
123 {
124 	unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
125 
126 	if (time_before(t, ss->serve))
127 		return;
128 
129 	ia64_invala();
130 
131 	for (;;) {
132 		asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
133 		if (time_before(t, serve))
134 			return;
135 		cpu_relax();
136 	}
137 }
138 
139 static inline void up_spin(struct spinaphore *ss)
140 {
141 	ia64_fetchadd(1, &ss->serve, rel);
142 }
143 
144 static struct spinaphore ptcg_sem;
145 static u16 nptcg = 1;
146 static int need_ptcg_sem = 1;
147 static int toolatetochangeptcgsem = 0;
148 
149 /*
150  * Kernel parameter "nptcg=" overrides max number of concurrent global TLB
151  * purges which is reported from either PAL or SAL PALO.
152  *
153  * We don't have sanity checking for nptcg value. It's the user's responsibility
154  * for valid nptcg value on the platform. Otherwise, kernel may hang in some
155  * cases.
156  */
157 static int __init
158 set_nptcg(char *str)
159 {
160 	int value = 0;
161 
162 	get_option(&str, &value);
163 	setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
164 
165 	return 1;
166 }
167 
168 __setup("nptcg=", set_nptcg);
169 
170 /*
171  * Maximum number of simultaneous ptc.g purges in the system can
172  * be defined by PAL_VM_SUMMARY (in which case we should take
173  * the smallest value for any cpu in the system) or by the PAL
174  * override table (in which case we should ignore the value from
175  * PAL_VM_SUMMARY).
176  *
177  * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
178  * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
179  * we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
180  *
181  * Complicating the logic here is the fact that num_possible_cpus()
182  * isn't fully setup until we start bringing cpus online.
183  */
184 void
185 setup_ptcg_sem(int max_purges, int nptcg_from)
186 {
187 	static int kp_override;
188 	static int palo_override;
189 	static int firstcpu = 1;
190 
191 	if (toolatetochangeptcgsem) {
192 		if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
193 			BUG_ON(1 < nptcg);
194 		else
195 			BUG_ON(max_purges < nptcg);
196 		return;
197 	}
198 
199 	if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
200 		kp_override = 1;
201 		nptcg = max_purges;
202 		goto resetsema;
203 	}
204 	if (kp_override) {
205 		need_ptcg_sem = num_possible_cpus() > nptcg;
206 		return;
207 	}
208 
209 	if (nptcg_from == NPTCG_FROM_PALO) {
210 		palo_override = 1;
211 
212 		/* In PALO max_purges == 0 really means it! */
213 		if (max_purges == 0)
214 			panic("Whoa! Platform does not support global TLB purges.\n");
215 		nptcg = max_purges;
216 		if (nptcg == PALO_MAX_TLB_PURGES) {
217 			need_ptcg_sem = 0;
218 			return;
219 		}
220 		goto resetsema;
221 	}
222 	if (palo_override) {
223 		if (nptcg != PALO_MAX_TLB_PURGES)
224 			need_ptcg_sem = (num_possible_cpus() > nptcg);
225 		return;
226 	}
227 
228 	/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
229 	if (max_purges == 0) max_purges = 1;
230 
231 	if (firstcpu) {
232 		nptcg = max_purges;
233 		firstcpu = 0;
234 	}
235 	if (max_purges < nptcg)
236 		nptcg = max_purges;
237 	if (nptcg == PAL_MAX_PURGES) {
238 		need_ptcg_sem = 0;
239 		return;
240 	} else
241 		need_ptcg_sem = (num_possible_cpus() > nptcg);
242 
243 resetsema:
244 	spinaphore_init(&ptcg_sem, max_purges);
245 }
246 
247 void
248 ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
249 		       unsigned long end, unsigned long nbits)
250 {
251 	struct mm_struct *active_mm = current->active_mm;
252 
253 	toolatetochangeptcgsem = 1;
254 
255 	if (mm != active_mm) {
256 		/* Restore region IDs for mm */
257 		if (mm && active_mm) {
258 			activate_context(mm);
259 		} else {
260 			flush_tlb_all();
261 			return;
262 		}
263 	}
264 
265 	if (need_ptcg_sem)
266 		down_spin(&ptcg_sem);
267 
268 	do {
269 		/*
270 		 * Flush ALAT entries also.
271 		 */
272 		ia64_ptcga(start, (nbits << 2));
273 		ia64_srlz_i();
274 		start += (1UL << nbits);
275 	} while (start < end);
276 
277 	if (need_ptcg_sem)
278 		up_spin(&ptcg_sem);
279 
280         if (mm != active_mm) {
281                 activate_context(active_mm);
282         }
283 }
284 
285 void
286 local_flush_tlb_all (void)
287 {
288 	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
289 
290 	addr    = local_cpu_data->ptce_base;
291 	count0  = local_cpu_data->ptce_count[0];
292 	count1  = local_cpu_data->ptce_count[1];
293 	stride0 = local_cpu_data->ptce_stride[0];
294 	stride1 = local_cpu_data->ptce_stride[1];
295 
296 	local_irq_save(flags);
297 	for (i = 0; i < count0; ++i) {
298 		for (j = 0; j < count1; ++j) {
299 			ia64_ptce(addr);
300 			addr += stride1;
301 		}
302 		addr += stride0;
303 	}
304 	local_irq_restore(flags);
305 	ia64_srlz_i();			/* srlz.i implies srlz.d */
306 }
307 
308 void
309 flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
310 		 unsigned long end)
311 {
312 	struct mm_struct *mm = vma->vm_mm;
313 	unsigned long size = end - start;
314 	unsigned long nbits;
315 
316 #ifndef CONFIG_SMP
317 	if (mm != current->active_mm) {
318 		mm->context = 0;
319 		return;
320 	}
321 #endif
322 
323 	nbits = ia64_fls(size + 0xfff);
324 	while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
325 			(nbits < purge.max_bits))
326 		++nbits;
327 	if (nbits > purge.max_bits)
328 		nbits = purge.max_bits;
329 	start &= ~((1UL << nbits) - 1);
330 
331 	preempt_disable();
332 #ifdef CONFIG_SMP
333 	if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
334 		platform_global_tlb_purge(mm, start, end, nbits);
335 		preempt_enable();
336 		return;
337 	}
338 #endif
339 	do {
340 		ia64_ptcl(start, (nbits<<2));
341 		start += (1UL << nbits);
342 	} while (start < end);
343 	preempt_enable();
344 	ia64_srlz_i();			/* srlz.i implies srlz.d */
345 }
346 EXPORT_SYMBOL(flush_tlb_range);
347 
348 void ia64_tlb_init(void)
349 {
350 	ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
351 	u64 tr_pgbits;
352 	long status;
353 	pal_vm_info_1_u_t vm_info_1;
354 	pal_vm_info_2_u_t vm_info_2;
355 	int cpu = smp_processor_id();
356 
357 	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
358 		printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
359 		       "defaulting to architected purge page-sizes.\n", status);
360 		purge.mask = 0x115557000UL;
361 	}
362 	purge.max_bits = ia64_fls(purge.mask);
363 
364 	ia64_get_ptce(&ptce_info);
365 	local_cpu_data->ptce_base = ptce_info.base;
366 	local_cpu_data->ptce_count[0] = ptce_info.count[0];
367 	local_cpu_data->ptce_count[1] = ptce_info.count[1];
368 	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
369 	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
370 
371 	local_flush_tlb_all();	/* nuke left overs from bootstrapping... */
372 	status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
373 
374 	if (status) {
375 		printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
376 		per_cpu(ia64_tr_num, cpu) = 8;
377 		return;
378 	}
379 	per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
380 	if (per_cpu(ia64_tr_num, cpu) >
381 				(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
382 		per_cpu(ia64_tr_num, cpu) =
383 				vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
384 	if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
385 		static int justonce = 1;
386 		per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
387 		if (justonce) {
388 			justonce = 0;
389 			printk(KERN_DEBUG "TR register number exceeds "
390 			       "IA64_TR_ALLOC_MAX!\n");
391 		}
392 	}
393 }
394 
395 /*
396  * is_tr_overlap
397  *
398  * Check overlap with inserted TRs.
399  */
400 static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
401 {
402 	u64 tr_log_size;
403 	u64 tr_end;
404 	u64 va_rr = ia64_get_rr(va);
405 	u64 va_rid = RR_TO_RID(va_rr);
406 	u64 va_end = va + (1<<log_size) - 1;
407 
408 	if (va_rid != RR_TO_RID(p->rr))
409 		return 0;
410 	tr_log_size = (p->itir & 0xff) >> 2;
411 	tr_end = p->ifa + (1<<tr_log_size) - 1;
412 
413 	if (va > tr_end || p->ifa > va_end)
414 		return 0;
415 	return 1;
416 
417 }
418 
419 /*
420  * ia64_insert_tr in virtual mode. Allocate a TR slot
421  *
422  * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
423  *
424  * va 	: virtual address.
425  * pte 	: pte entries inserted.
426  * log_size: range to be covered.
427  *
428  * Return value:  <0 :  error No.
429  *
430  *		  >=0 : slot number allocated for TR.
431  * Must be called with preemption disabled.
432  */
433 int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
434 {
435 	int i, r;
436 	unsigned long psr;
437 	struct ia64_tr_entry *p;
438 	int cpu = smp_processor_id();
439 
440 	if (!ia64_idtrs[cpu]) {
441 		ia64_idtrs[cpu] = kmalloc_array(2 * IA64_TR_ALLOC_MAX,
442 						sizeof(struct ia64_tr_entry),
443 						GFP_KERNEL);
444 		if (!ia64_idtrs[cpu])
445 			return -ENOMEM;
446 	}
447 	r = -EINVAL;
448 	/*Check overlap with existing TR entries*/
449 	if (target_mask & 0x1) {
450 		p = ia64_idtrs[cpu];
451 		for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
452 								i++, p++) {
453 			if (p->pte & 0x1)
454 				if (is_tr_overlap(p, va, log_size)) {
455 					printk(KERN_DEBUG "Overlapped Entry"
456 						"Inserted for TR Register!!\n");
457 					goto out;
458 			}
459 		}
460 	}
461 	if (target_mask & 0x2) {
462 		p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX;
463 		for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
464 								i++, p++) {
465 			if (p->pte & 0x1)
466 				if (is_tr_overlap(p, va, log_size)) {
467 					printk(KERN_DEBUG "Overlapped Entry"
468 						"Inserted for TR Register!!\n");
469 					goto out;
470 				}
471 		}
472 	}
473 
474 	for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
475 		switch (target_mask & 0x3) {
476 		case 1:
477 			if (!((ia64_idtrs[cpu] + i)->pte & 0x1))
478 				goto found;
479 			continue;
480 		case 2:
481 			if (!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
482 				goto found;
483 			continue;
484 		case 3:
485 			if (!((ia64_idtrs[cpu] + i)->pte & 0x1) &&
486 			    !((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
487 				goto found;
488 			continue;
489 		default:
490 			r = -EINVAL;
491 			goto out;
492 		}
493 	}
494 found:
495 	if (i >= per_cpu(ia64_tr_num, cpu))
496 		return -EBUSY;
497 
498 	/*Record tr info for mca hander use!*/
499 	if (i > per_cpu(ia64_tr_used, cpu))
500 		per_cpu(ia64_tr_used, cpu) = i;
501 
502 	psr = ia64_clear_ic();
503 	if (target_mask & 0x1) {
504 		ia64_itr(0x1, i, va, pte, log_size);
505 		ia64_srlz_i();
506 		p = ia64_idtrs[cpu] + i;
507 		p->ifa = va;
508 		p->pte = pte;
509 		p->itir = log_size << 2;
510 		p->rr = ia64_get_rr(va);
511 	}
512 	if (target_mask & 0x2) {
513 		ia64_itr(0x2, i, va, pte, log_size);
514 		ia64_srlz_i();
515 		p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i;
516 		p->ifa = va;
517 		p->pte = pte;
518 		p->itir = log_size << 2;
519 		p->rr = ia64_get_rr(va);
520 	}
521 	ia64_set_psr(psr);
522 	r = i;
523 out:
524 	return r;
525 }
526 EXPORT_SYMBOL_GPL(ia64_itr_entry);
527 
528 /*
529  * ia64_purge_tr
530  *
531  * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
532  * slot: slot number to be freed.
533  *
534  * Must be called with preemption disabled.
535  */
536 void ia64_ptr_entry(u64 target_mask, int slot)
537 {
538 	int cpu = smp_processor_id();
539 	int i;
540 	struct ia64_tr_entry *p;
541 
542 	if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
543 		return;
544 
545 	if (target_mask & 0x1) {
546 		p = ia64_idtrs[cpu] + slot;
547 		if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
548 			p->pte = 0;
549 			ia64_ptr(0x1, p->ifa, p->itir>>2);
550 			ia64_srlz_i();
551 		}
552 	}
553 
554 	if (target_mask & 0x2) {
555 		p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + slot;
556 		if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
557 			p->pte = 0;
558 			ia64_ptr(0x2, p->ifa, p->itir>>2);
559 			ia64_srlz_i();
560 		}
561 	}
562 
563 	for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
564 		if (((ia64_idtrs[cpu] + i)->pte & 0x1) ||
565 		    ((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
566 			break;
567 	}
568 	per_cpu(ia64_tr_used, cpu) = i;
569 }
570 EXPORT_SYMBOL_GPL(ia64_ptr_entry);
571