1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds/* 31da177e4SLinus Torvalds * McKinley-optimized version of copy_page(). 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (C) 2002 Hewlett-Packard Co 61da177e4SLinus Torvalds * David Mosberger <davidm@hpl.hp.com> 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * Inputs: 91da177e4SLinus Torvalds * in0: address of target page 101da177e4SLinus Torvalds * in1: address of source page 111da177e4SLinus Torvalds * Output: 121da177e4SLinus Torvalds * no return value 131da177e4SLinus Torvalds * 141da177e4SLinus Torvalds * General idea: 151da177e4SLinus Torvalds * - use regular loads and stores to prefetch data to avoid consuming M-slot just for 161da177e4SLinus Torvalds * lfetches => good for in-cache performance 171da177e4SLinus Torvalds * - avoid l2 bank-conflicts by not storing into the same 16-byte bank within a single 181da177e4SLinus Torvalds * cycle 191da177e4SLinus Torvalds * 201da177e4SLinus Torvalds * Principle of operation: 211da177e4SLinus Torvalds * First, note that L1 has a line-size of 64 bytes and L2 a line-size of 128 bytes. 221da177e4SLinus Torvalds * To avoid secondary misses in L2, we prefetch both source and destination with a line-size 231da177e4SLinus Torvalds * of 128 bytes. When both of these lines are in the L2 and the first half of the 241da177e4SLinus Torvalds * source line is in L1, we start copying the remaining words. The second half of the 251da177e4SLinus Torvalds * source line is prefetched in an earlier iteration, so that by the time we start 261da177e4SLinus Torvalds * accessing it, it's also present in the L1. 271da177e4SLinus Torvalds * 281da177e4SLinus Torvalds * We use a software-pipelined loop to control the overall operation. The pipeline 291da177e4SLinus Torvalds * has 2*PREFETCH_DIST+K stages. The first PREFETCH_DIST stages are used for prefetching 301da177e4SLinus Torvalds * source cache-lines. The second PREFETCH_DIST stages are used for prefetching destination 311da177e4SLinus Torvalds * cache-lines, the last K stages are used to copy the cache-line words not copied by 321da177e4SLinus Torvalds * the prefetches. The four relevant points in the pipelined are called A, B, C, D: 331da177e4SLinus Torvalds * p[A] is TRUE if a source-line should be prefetched, p[B] is TRUE if a destination-line 341da177e4SLinus Torvalds * should be prefetched, p[C] is TRUE if the second half of an L2 line should be brought 351da177e4SLinus Torvalds * into L1D and p[D] is TRUE if a cacheline needs to be copied. 361da177e4SLinus Torvalds * 371da177e4SLinus Torvalds * This all sounds very complicated, but thanks to the modulo-scheduled loop support, 381da177e4SLinus Torvalds * the resulting code is very regular and quite easy to follow (once you get the idea). 391da177e4SLinus Torvalds * 401da177e4SLinus Torvalds * As a secondary optimization, the first 2*PREFETCH_DIST iterations are implemented 411da177e4SLinus Torvalds * as the separate .prefetch_loop. Logically, this loop performs exactly like the 421da177e4SLinus Torvalds * main-loop (.line_copy), but has all known-to-be-predicated-off instructions removed, 431da177e4SLinus Torvalds * so that each loop iteration is faster (again, good for cached case). 441da177e4SLinus Torvalds * 451da177e4SLinus Torvalds * When reading the code, it helps to keep the following picture in mind: 461da177e4SLinus Torvalds * 471da177e4SLinus Torvalds * word 0 word 1 481da177e4SLinus Torvalds * +------+------+--- 491da177e4SLinus Torvalds * | v[x] | t1 | ^ 501da177e4SLinus Torvalds * | t2 | t3 | | 511da177e4SLinus Torvalds * | t4 | t5 | | 521da177e4SLinus Torvalds * | t6 | t7 | | 128 bytes 531da177e4SLinus Torvalds * | n[y] | t9 | | (L2 cache line) 541da177e4SLinus Torvalds * | t10 | t11 | | 551da177e4SLinus Torvalds * | t12 | t13 | | 561da177e4SLinus Torvalds * | t14 | t15 | v 571da177e4SLinus Torvalds * +------+------+--- 581da177e4SLinus Torvalds * 591da177e4SLinus Torvalds * Here, v[x] is copied by the (memory) prefetch. n[y] is loaded at p[C] 601da177e4SLinus Torvalds * to fetch the second-half of the L2 cache line into L1, and the tX words are copied in 611da177e4SLinus Torvalds * an order that avoids bank conflicts. 621da177e4SLinus Torvalds */ 63*ab03e604SMasahiro Yamada#include <linux/export.h> 641da177e4SLinus Torvalds#include <asm/asmmacro.h> 651da177e4SLinus Torvalds#include <asm/page.h> 661da177e4SLinus Torvalds 671da177e4SLinus Torvalds#define PREFETCH_DIST 8 // McKinley sustains 16 outstanding L2 misses (8 ld, 8 st) 681da177e4SLinus Torvalds 691da177e4SLinus Torvalds#define src0 r2 701da177e4SLinus Torvalds#define src1 r3 711da177e4SLinus Torvalds#define dst0 r9 721da177e4SLinus Torvalds#define dst1 r10 731da177e4SLinus Torvalds#define src_pre_mem r11 741da177e4SLinus Torvalds#define dst_pre_mem r14 751da177e4SLinus Torvalds#define src_pre_l2 r15 761da177e4SLinus Torvalds#define dst_pre_l2 r16 771da177e4SLinus Torvalds#define t1 r17 781da177e4SLinus Torvalds#define t2 r18 791da177e4SLinus Torvalds#define t3 r19 801da177e4SLinus Torvalds#define t4 r20 811da177e4SLinus Torvalds#define t5 t1 // alias! 821da177e4SLinus Torvalds#define t6 t2 // alias! 831da177e4SLinus Torvalds#define t7 t3 // alias! 841da177e4SLinus Torvalds#define t9 t5 // alias! 851da177e4SLinus Torvalds#define t10 t4 // alias! 861da177e4SLinus Torvalds#define t11 t7 // alias! 871da177e4SLinus Torvalds#define t12 t6 // alias! 881da177e4SLinus Torvalds#define t14 t10 // alias! 891da177e4SLinus Torvalds#define t13 r21 901da177e4SLinus Torvalds#define t15 r22 911da177e4SLinus Torvalds 921da177e4SLinus Torvalds#define saved_lc r23 931da177e4SLinus Torvalds#define saved_pr r24 941da177e4SLinus Torvalds 951da177e4SLinus Torvalds#define A 0 961da177e4SLinus Torvalds#define B (PREFETCH_DIST) 971da177e4SLinus Torvalds#define C (B + PREFETCH_DIST) 981da177e4SLinus Torvalds#define D (C + 3) 991da177e4SLinus Torvalds#define N (D + 1) 1001da177e4SLinus Torvalds#define Nrot ((N + 7) & ~7) 1011da177e4SLinus Torvalds 1021da177e4SLinus TorvaldsGLOBAL_ENTRY(copy_page) 1031da177e4SLinus Torvalds .prologue 1041da177e4SLinus Torvalds alloc r8 = ar.pfs, 2, Nrot-2, 0, Nrot 1051da177e4SLinus Torvalds 1061da177e4SLinus Torvalds .rotr v[2*PREFETCH_DIST], n[D-C+1] 1071da177e4SLinus Torvalds .rotp p[N] 1081da177e4SLinus Torvalds 1091da177e4SLinus Torvalds .save ar.lc, saved_lc 1101da177e4SLinus Torvalds mov saved_lc = ar.lc 1111da177e4SLinus Torvalds .save pr, saved_pr 1121da177e4SLinus Torvalds mov saved_pr = pr 1131da177e4SLinus Torvalds .body 1141da177e4SLinus Torvalds 1151da177e4SLinus Torvalds mov src_pre_mem = in1 1161da177e4SLinus Torvalds mov pr.rot = 0x10000 1171da177e4SLinus Torvalds mov ar.ec = 1 // special unrolled loop 1181da177e4SLinus Torvalds 1191da177e4SLinus Torvalds mov dst_pre_mem = in0 1201da177e4SLinus Torvalds mov ar.lc = 2*PREFETCH_DIST - 1 1211da177e4SLinus Torvalds 1221da177e4SLinus Torvalds add src_pre_l2 = 8*8, in1 1231da177e4SLinus Torvalds add dst_pre_l2 = 8*8, in0 1241da177e4SLinus Torvalds add src0 = 8, in1 // first t1 src 1251da177e4SLinus Torvalds add src1 = 3*8, in1 // first t3 src 1261da177e4SLinus Torvalds add dst0 = 8, in0 // first t1 dst 1271da177e4SLinus Torvalds add dst1 = 3*8, in0 // first t3 dst 1281da177e4SLinus Torvalds mov t1 = (PAGE_SIZE/128) - (2*PREFETCH_DIST) - 1 1291da177e4SLinus Torvalds nop.m 0 1301da177e4SLinus Torvalds nop.i 0 1311da177e4SLinus Torvalds ;; 1321da177e4SLinus Torvalds // same as .line_copy loop, but with all predicated-off instructions removed: 1331da177e4SLinus Torvalds.prefetch_loop: 1341da177e4SLinus Torvalds(p[A]) ld8 v[A] = [src_pre_mem], 128 // M0 1351da177e4SLinus Torvalds(p[B]) st8 [dst_pre_mem] = v[B], 128 // M2 1361da177e4SLinus Torvalds br.ctop.sptk .prefetch_loop 1371da177e4SLinus Torvalds ;; 1381da177e4SLinus Torvalds cmp.eq p16, p0 = r0, r0 // reset p16 to 1 (br.ctop cleared it to zero) 1391da177e4SLinus Torvalds mov ar.lc = t1 // with 64KB pages, t1 is too big to fit in 8 bits! 1401da177e4SLinus Torvalds mov ar.ec = N // # of stages in pipeline 1411da177e4SLinus Torvalds ;; 1421da177e4SLinus Torvalds.line_copy: 1431da177e4SLinus Torvalds(p[D]) ld8 t2 = [src0], 3*8 // M0 1441da177e4SLinus Torvalds(p[D]) ld8 t4 = [src1], 3*8 // M1 1451da177e4SLinus Torvalds(p[B]) st8 [dst_pre_mem] = v[B], 128 // M2 prefetch dst from memory 1461da177e4SLinus Torvalds(p[D]) st8 [dst_pre_l2] = n[D-C], 128 // M3 prefetch dst from L2 1471da177e4SLinus Torvalds ;; 1481da177e4SLinus Torvalds(p[A]) ld8 v[A] = [src_pre_mem], 128 // M0 prefetch src from memory 1491da177e4SLinus Torvalds(p[C]) ld8 n[0] = [src_pre_l2], 128 // M1 prefetch src from L2 1501da177e4SLinus Torvalds(p[D]) st8 [dst0] = t1, 8 // M2 1511da177e4SLinus Torvalds(p[D]) st8 [dst1] = t3, 8 // M3 1521da177e4SLinus Torvalds ;; 1531da177e4SLinus Torvalds(p[D]) ld8 t5 = [src0], 8 1541da177e4SLinus Torvalds(p[D]) ld8 t7 = [src1], 3*8 1551da177e4SLinus Torvalds(p[D]) st8 [dst0] = t2, 3*8 1561da177e4SLinus Torvalds(p[D]) st8 [dst1] = t4, 3*8 1571da177e4SLinus Torvalds ;; 1581da177e4SLinus Torvalds(p[D]) ld8 t6 = [src0], 3*8 1591da177e4SLinus Torvalds(p[D]) ld8 t10 = [src1], 8 1601da177e4SLinus Torvalds(p[D]) st8 [dst0] = t5, 8 1611da177e4SLinus Torvalds(p[D]) st8 [dst1] = t7, 3*8 1621da177e4SLinus Torvalds ;; 1631da177e4SLinus Torvalds(p[D]) ld8 t9 = [src0], 3*8 1641da177e4SLinus Torvalds(p[D]) ld8 t11 = [src1], 3*8 1651da177e4SLinus Torvalds(p[D]) st8 [dst0] = t6, 3*8 1661da177e4SLinus Torvalds(p[D]) st8 [dst1] = t10, 8 1671da177e4SLinus Torvalds ;; 1681da177e4SLinus Torvalds(p[D]) ld8 t12 = [src0], 8 1691da177e4SLinus Torvalds(p[D]) ld8 t14 = [src1], 8 1701da177e4SLinus Torvalds(p[D]) st8 [dst0] = t9, 3*8 1711da177e4SLinus Torvalds(p[D]) st8 [dst1] = t11, 3*8 1721da177e4SLinus Torvalds ;; 1731da177e4SLinus Torvalds(p[D]) ld8 t13 = [src0], 4*8 1741da177e4SLinus Torvalds(p[D]) ld8 t15 = [src1], 4*8 1751da177e4SLinus Torvalds(p[D]) st8 [dst0] = t12, 8 1761da177e4SLinus Torvalds(p[D]) st8 [dst1] = t14, 8 1771da177e4SLinus Torvalds ;; 1781da177e4SLinus Torvalds(p[D-1])ld8 t1 = [src0], 8 1791da177e4SLinus Torvalds(p[D-1])ld8 t3 = [src1], 8 1801da177e4SLinus Torvalds(p[D]) st8 [dst0] = t13, 4*8 1811da177e4SLinus Torvalds(p[D]) st8 [dst1] = t15, 4*8 1821da177e4SLinus Torvalds br.ctop.sptk .line_copy 1831da177e4SLinus Torvalds ;; 1841da177e4SLinus Torvalds mov ar.lc = saved_lc 1851da177e4SLinus Torvalds mov pr = saved_pr, -1 1861da177e4SLinus Torvalds br.ret.sptk.many rp 1871da177e4SLinus TorvaldsEND(copy_page) 188e007c533SAl ViroEXPORT_SYMBOL(copy_page) 189