1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/machvec.h> 50 #include <asm/mca.h> 51 #include <asm/meminit.h> 52 #include <asm/page.h> 53 #include <asm/patch.h> 54 #include <asm/pgtable.h> 55 #include <asm/processor.h> 56 #include <asm/sal.h> 57 #include <asm/sections.h> 58 #include <asm/setup.h> 59 #include <asm/smp.h> 60 #include <asm/tlbflush.h> 61 #include <asm/unistd.h> 62 #include <asm/hpsim.h> 63 64 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 65 # error "struct cpuinfo_ia64 too big!" 66 #endif 67 68 #ifdef CONFIG_SMP 69 unsigned long __per_cpu_offset[NR_CPUS]; 70 EXPORT_SYMBOL(__per_cpu_offset); 71 #endif 72 73 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 74 EXPORT_SYMBOL(ia64_cpu_info); 75 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 76 #ifdef CONFIG_SMP 77 EXPORT_SYMBOL(local_per_cpu_offset); 78 #endif 79 unsigned long ia64_cycles_per_usec; 80 struct ia64_boot_param *ia64_boot_param; 81 struct screen_info screen_info; 82 unsigned long vga_console_iobase; 83 unsigned long vga_console_membase; 84 85 static struct resource data_resource = { 86 .name = "Kernel data", 87 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 88 }; 89 90 static struct resource code_resource = { 91 .name = "Kernel code", 92 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 93 }; 94 95 static struct resource bss_resource = { 96 .name = "Kernel bss", 97 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 98 }; 99 100 unsigned long ia64_max_cacheline_size; 101 102 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 103 EXPORT_SYMBOL(ia64_iobase); 104 struct io_space io_space[MAX_IO_SPACES]; 105 EXPORT_SYMBOL(io_space); 106 unsigned int num_io_spaces; 107 108 /* 109 * "flush_icache_range()" needs to know what processor dependent stride size to use 110 * when it makes i-cache(s) coherent with d-caches. 111 */ 112 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 113 unsigned long ia64_i_cache_stride_shift = ~0; 114 /* 115 * "clflush_cache_range()" needs to know what processor dependent stride size to 116 * use when it flushes cache lines including both d-cache and i-cache. 117 */ 118 /* Safest way to go: 32 bytes by 32 bytes */ 119 #define CACHE_STRIDE_SHIFT 5 120 unsigned long ia64_cache_stride_shift = ~0; 121 122 /* 123 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 124 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 125 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 126 * address of the second buffer must be aligned to (merge_mask+1) in order to be 127 * mergeable). By default, we assume there is no I/O MMU which can merge physically 128 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 129 * page-size of 2^64. 130 */ 131 unsigned long ia64_max_iommu_merge_mask = ~0UL; 132 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 133 134 /* 135 * We use a special marker for the end of memory and it uses the extra (+1) slot 136 */ 137 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 138 int num_rsvd_regions __initdata; 139 140 141 /* 142 * Filter incoming memory segments based on the primitive map created from the boot 143 * parameters. Segments contained in the map are removed from the memory ranges. A 144 * caller-specified function is called with the memory ranges that remain after filtering. 145 * This routine does not assume the incoming segments are sorted. 146 */ 147 int __init 148 filter_rsvd_memory (u64 start, u64 end, void *arg) 149 { 150 u64 range_start, range_end, prev_start; 151 void (*func)(unsigned long, unsigned long, int); 152 int i; 153 154 #if IGNORE_PFN0 155 if (start == PAGE_OFFSET) { 156 printk(KERN_WARNING "warning: skipping physical page 0\n"); 157 start += PAGE_SIZE; 158 if (start >= end) return 0; 159 } 160 #endif 161 /* 162 * lowest possible address(walker uses virtual) 163 */ 164 prev_start = PAGE_OFFSET; 165 func = arg; 166 167 for (i = 0; i < num_rsvd_regions; ++i) { 168 range_start = max(start, prev_start); 169 range_end = min(end, rsvd_region[i].start); 170 171 if (range_start < range_end) 172 call_pernode_memory(__pa(range_start), range_end - range_start, func); 173 174 /* nothing more available in this segment */ 175 if (range_end == end) return 0; 176 177 prev_start = rsvd_region[i].end; 178 } 179 /* end of memory marker allows full processing inside loop body */ 180 return 0; 181 } 182 183 /* 184 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 185 * are not filtered out. 186 */ 187 int __init 188 filter_memory(u64 start, u64 end, void *arg) 189 { 190 void (*func)(unsigned long, unsigned long, int); 191 192 #if IGNORE_PFN0 193 if (start == PAGE_OFFSET) { 194 printk(KERN_WARNING "warning: skipping physical page 0\n"); 195 start += PAGE_SIZE; 196 if (start >= end) 197 return 0; 198 } 199 #endif 200 func = arg; 201 if (start < end) 202 call_pernode_memory(__pa(start), end - start, func); 203 return 0; 204 } 205 206 static void __init 207 sort_regions (struct rsvd_region *rsvd_region, int max) 208 { 209 int j; 210 211 /* simple bubble sorting */ 212 while (max--) { 213 for (j = 0; j < max; ++j) { 214 if (rsvd_region[j].start > rsvd_region[j+1].start) { 215 struct rsvd_region tmp; 216 tmp = rsvd_region[j]; 217 rsvd_region[j] = rsvd_region[j + 1]; 218 rsvd_region[j + 1] = tmp; 219 } 220 } 221 } 222 } 223 224 /* merge overlaps */ 225 static int __init 226 merge_regions (struct rsvd_region *rsvd_region, int max) 227 { 228 int i; 229 for (i = 1; i < max; ++i) { 230 if (rsvd_region[i].start >= rsvd_region[i-1].end) 231 continue; 232 if (rsvd_region[i].end > rsvd_region[i-1].end) 233 rsvd_region[i-1].end = rsvd_region[i].end; 234 --max; 235 memmove(&rsvd_region[i], &rsvd_region[i+1], 236 (max - i) * sizeof(struct rsvd_region)); 237 } 238 return max; 239 } 240 241 /* 242 * Request address space for all standard resources 243 */ 244 static int __init register_memory(void) 245 { 246 code_resource.start = ia64_tpa(_text); 247 code_resource.end = ia64_tpa(_etext) - 1; 248 data_resource.start = ia64_tpa(_etext); 249 data_resource.end = ia64_tpa(_edata) - 1; 250 bss_resource.start = ia64_tpa(__bss_start); 251 bss_resource.end = ia64_tpa(_end) - 1; 252 efi_initialize_iomem_resources(&code_resource, &data_resource, 253 &bss_resource); 254 255 return 0; 256 } 257 258 __initcall(register_memory); 259 260 261 #ifdef CONFIG_KEXEC 262 263 /* 264 * This function checks if the reserved crashkernel is allowed on the specific 265 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 266 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 267 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 268 * in kdump case. See the comment in sba_init() in sba_iommu.c. 269 * 270 * So, the only machvec that really supports loading the kdump kernel 271 * over 4 GB is "sn2". 272 */ 273 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 274 { 275 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 276 return 1; 277 else 278 return pbase < (1UL << 32); 279 } 280 281 static void __init setup_crashkernel(unsigned long total, int *n) 282 { 283 unsigned long long base = 0, size = 0; 284 int ret; 285 286 ret = parse_crashkernel(boot_command_line, total, 287 &size, &base); 288 if (ret == 0 && size > 0) { 289 if (!base) { 290 sort_regions(rsvd_region, *n); 291 *n = merge_regions(rsvd_region, *n); 292 base = kdump_find_rsvd_region(size, 293 rsvd_region, *n); 294 } 295 296 if (!check_crashkernel_memory(base, size)) { 297 pr_warning("crashkernel: There would be kdump memory " 298 "at %ld GB but this is unusable because it " 299 "must\nbe below 4 GB. Change the memory " 300 "configuration of the machine.\n", 301 (unsigned long)(base >> 30)); 302 return; 303 } 304 305 if (base != ~0UL) { 306 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 307 "for crashkernel (System RAM: %ldMB)\n", 308 (unsigned long)(size >> 20), 309 (unsigned long)(base >> 20), 310 (unsigned long)(total >> 20)); 311 rsvd_region[*n].start = 312 (unsigned long)__va(base); 313 rsvd_region[*n].end = 314 (unsigned long)__va(base + size); 315 (*n)++; 316 crashk_res.start = base; 317 crashk_res.end = base + size - 1; 318 } 319 } 320 efi_memmap_res.start = ia64_boot_param->efi_memmap; 321 efi_memmap_res.end = efi_memmap_res.start + 322 ia64_boot_param->efi_memmap_size; 323 boot_param_res.start = __pa(ia64_boot_param); 324 boot_param_res.end = boot_param_res.start + 325 sizeof(*ia64_boot_param); 326 } 327 #else 328 static inline void __init setup_crashkernel(unsigned long total, int *n) 329 {} 330 #endif 331 332 /** 333 * reserve_memory - setup reserved memory areas 334 * 335 * Setup the reserved memory areas set aside for the boot parameters, 336 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 337 * see arch/ia64/include/asm/meminit.h if you need to define more. 338 */ 339 void __init 340 reserve_memory (void) 341 { 342 int n = 0; 343 unsigned long total_memory; 344 345 /* 346 * none of the entries in this table overlap 347 */ 348 rsvd_region[n].start = (unsigned long) ia64_boot_param; 349 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 350 n++; 351 352 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 353 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 354 n++; 355 356 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 357 rsvd_region[n].end = (rsvd_region[n].start 358 + strlen(__va(ia64_boot_param->command_line)) + 1); 359 n++; 360 361 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 362 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 363 n++; 364 365 #ifdef CONFIG_BLK_DEV_INITRD 366 if (ia64_boot_param->initrd_start) { 367 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 368 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 369 n++; 370 } 371 #endif 372 373 #ifdef CONFIG_CRASH_DUMP 374 if (reserve_elfcorehdr(&rsvd_region[n].start, 375 &rsvd_region[n].end) == 0) 376 n++; 377 #endif 378 379 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 380 n++; 381 382 setup_crashkernel(total_memory, &n); 383 384 /* end of memory marker */ 385 rsvd_region[n].start = ~0UL; 386 rsvd_region[n].end = ~0UL; 387 n++; 388 389 num_rsvd_regions = n; 390 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 391 392 sort_regions(rsvd_region, num_rsvd_regions); 393 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions); 394 } 395 396 397 /** 398 * find_initrd - get initrd parameters from the boot parameter structure 399 * 400 * Grab the initrd start and end from the boot parameter struct given us by 401 * the boot loader. 402 */ 403 void __init 404 find_initrd (void) 405 { 406 #ifdef CONFIG_BLK_DEV_INITRD 407 if (ia64_boot_param->initrd_start) { 408 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 409 initrd_end = initrd_start+ia64_boot_param->initrd_size; 410 411 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 412 initrd_start, ia64_boot_param->initrd_size); 413 } 414 #endif 415 } 416 417 static void __init 418 io_port_init (void) 419 { 420 unsigned long phys_iobase; 421 422 /* 423 * Set `iobase' based on the EFI memory map or, failing that, the 424 * value firmware left in ar.k0. 425 * 426 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 427 * the port's virtual address, so ia32_load_state() loads it with a 428 * user virtual address. But in ia64 mode, glibc uses the 429 * *physical* address in ar.k0 to mmap the appropriate area from 430 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 431 * cases, user-mode can only use the legacy 0-64K I/O port space. 432 * 433 * ar.k0 is not involved in kernel I/O port accesses, which can use 434 * any of the I/O port spaces and are done via MMIO using the 435 * virtual mmio_base from the appropriate io_space[]. 436 */ 437 phys_iobase = efi_get_iobase(); 438 if (!phys_iobase) { 439 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 440 printk(KERN_INFO "No I/O port range found in EFI memory map, " 441 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 442 } 443 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 444 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 445 446 /* setup legacy IO port space */ 447 io_space[0].mmio_base = ia64_iobase; 448 io_space[0].sparse = 1; 449 num_io_spaces = 1; 450 } 451 452 /** 453 * early_console_setup - setup debugging console 454 * 455 * Consoles started here require little enough setup that we can start using 456 * them very early in the boot process, either right after the machine 457 * vector initialization, or even before if the drivers can detect their hw. 458 * 459 * Returns non-zero if a console couldn't be setup. 460 */ 461 static inline int __init 462 early_console_setup (char *cmdline) 463 { 464 int earlycons = 0; 465 466 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 467 { 468 extern int sn_serial_console_early_setup(void); 469 if (!sn_serial_console_early_setup()) 470 earlycons++; 471 } 472 #endif 473 #ifdef CONFIG_EFI_PCDP 474 if (!efi_setup_pcdp_console(cmdline)) 475 earlycons++; 476 #endif 477 if (!simcons_register()) 478 earlycons++; 479 480 return (earlycons) ? 0 : -1; 481 } 482 483 static inline void 484 mark_bsp_online (void) 485 { 486 #ifdef CONFIG_SMP 487 /* If we register an early console, allow CPU 0 to printk */ 488 set_cpu_online(smp_processor_id(), true); 489 #endif 490 } 491 492 static __initdata int nomca; 493 static __init int setup_nomca(char *s) 494 { 495 nomca = 1; 496 return 0; 497 } 498 early_param("nomca", setup_nomca); 499 500 #ifdef CONFIG_CRASH_DUMP 501 int __init reserve_elfcorehdr(u64 *start, u64 *end) 502 { 503 u64 length; 504 505 /* We get the address using the kernel command line, 506 * but the size is extracted from the EFI tables. 507 * Both address and size are required for reservation 508 * to work properly. 509 */ 510 511 if (!is_vmcore_usable()) 512 return -EINVAL; 513 514 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 515 vmcore_unusable(); 516 return -EINVAL; 517 } 518 519 *start = (unsigned long)__va(elfcorehdr_addr); 520 *end = *start + length; 521 return 0; 522 } 523 524 #endif /* CONFIG_PROC_VMCORE */ 525 526 void __init 527 setup_arch (char **cmdline_p) 528 { 529 unw_init(); 530 531 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 532 533 *cmdline_p = __va(ia64_boot_param->command_line); 534 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 535 536 efi_init(); 537 io_port_init(); 538 539 #ifdef CONFIG_IA64_GENERIC 540 /* machvec needs to be parsed from the command line 541 * before parse_early_param() is called to ensure 542 * that ia64_mv is initialised before any command line 543 * settings may cause console setup to occur 544 */ 545 machvec_init_from_cmdline(*cmdline_p); 546 #endif 547 548 parse_early_param(); 549 550 if (early_console_setup(*cmdline_p) == 0) 551 mark_bsp_online(); 552 553 #ifdef CONFIG_ACPI 554 /* Initialize the ACPI boot-time table parser */ 555 acpi_table_init(); 556 early_acpi_boot_init(); 557 # ifdef CONFIG_ACPI_NUMA 558 acpi_numa_init(); 559 acpi_numa_fixup(); 560 # ifdef CONFIG_ACPI_HOTPLUG_CPU 561 prefill_possible_map(); 562 # endif 563 per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ? 564 32 : cpumask_weight(&early_cpu_possible_map)), 565 additional_cpus > 0 ? additional_cpus : 0); 566 # endif 567 #endif /* CONFIG_APCI_BOOT */ 568 569 #ifdef CONFIG_SMP 570 smp_build_cpu_map(); 571 #endif 572 find_memory(); 573 574 /* process SAL system table: */ 575 ia64_sal_init(__va(efi.sal_systab)); 576 577 #ifdef CONFIG_ITANIUM 578 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 579 #else 580 { 581 unsigned long num_phys_stacked; 582 583 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 584 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 585 } 586 #endif 587 588 #ifdef CONFIG_SMP 589 cpu_physical_id(0) = hard_smp_processor_id(); 590 #endif 591 592 cpu_init(); /* initialize the bootstrap CPU */ 593 mmu_context_init(); /* initialize context_id bitmap */ 594 595 #ifdef CONFIG_VT 596 if (!conswitchp) { 597 # if defined(CONFIG_DUMMY_CONSOLE) 598 conswitchp = &dummy_con; 599 # endif 600 # if defined(CONFIG_VGA_CONSOLE) 601 /* 602 * Non-legacy systems may route legacy VGA MMIO range to system 603 * memory. vga_con probes the MMIO hole, so memory looks like 604 * a VGA device to it. The EFI memory map can tell us if it's 605 * memory so we can avoid this problem. 606 */ 607 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 608 conswitchp = &vga_con; 609 # endif 610 } 611 #endif 612 613 /* enable IA-64 Machine Check Abort Handling unless disabled */ 614 if (!nomca) 615 ia64_mca_init(); 616 617 platform_setup(cmdline_p); 618 #ifndef CONFIG_IA64_HP_SIM 619 check_sal_cache_flush(); 620 #endif 621 paging_init(); 622 } 623 624 /* 625 * Display cpu info for all CPUs. 626 */ 627 static int 628 show_cpuinfo (struct seq_file *m, void *v) 629 { 630 #ifdef CONFIG_SMP 631 # define lpj c->loops_per_jiffy 632 # define cpunum c->cpu 633 #else 634 # define lpj loops_per_jiffy 635 # define cpunum 0 636 #endif 637 static struct { 638 unsigned long mask; 639 const char *feature_name; 640 } feature_bits[] = { 641 { 1UL << 0, "branchlong" }, 642 { 1UL << 1, "spontaneous deferral"}, 643 { 1UL << 2, "16-byte atomic ops" } 644 }; 645 char features[128], *cp, *sep; 646 struct cpuinfo_ia64 *c = v; 647 unsigned long mask; 648 unsigned long proc_freq; 649 int i, size; 650 651 mask = c->features; 652 653 /* build the feature string: */ 654 memcpy(features, "standard", 9); 655 cp = features; 656 size = sizeof(features); 657 sep = ""; 658 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 659 if (mask & feature_bits[i].mask) { 660 cp += snprintf(cp, size, "%s%s", sep, 661 feature_bits[i].feature_name), 662 sep = ", "; 663 mask &= ~feature_bits[i].mask; 664 size = sizeof(features) - (cp - features); 665 } 666 } 667 if (mask && size > 1) { 668 /* print unknown features as a hex value */ 669 snprintf(cp, size, "%s0x%lx", sep, mask); 670 } 671 672 proc_freq = cpufreq_quick_get(cpunum); 673 if (!proc_freq) 674 proc_freq = c->proc_freq / 1000; 675 676 seq_printf(m, 677 "processor : %d\n" 678 "vendor : %s\n" 679 "arch : IA-64\n" 680 "family : %u\n" 681 "model : %u\n" 682 "model name : %s\n" 683 "revision : %u\n" 684 "archrev : %u\n" 685 "features : %s\n" 686 "cpu number : %lu\n" 687 "cpu regs : %u\n" 688 "cpu MHz : %lu.%03lu\n" 689 "itc MHz : %lu.%06lu\n" 690 "BogoMIPS : %lu.%02lu\n", 691 cpunum, c->vendor, c->family, c->model, 692 c->model_name, c->revision, c->archrev, 693 features, c->ppn, c->number, 694 proc_freq / 1000, proc_freq % 1000, 695 c->itc_freq / 1000000, c->itc_freq % 1000000, 696 lpj*HZ/500000, (lpj*HZ/5000) % 100); 697 #ifdef CONFIG_SMP 698 seq_printf(m, "siblings : %u\n", 699 cpumask_weight(&cpu_core_map[cpunum])); 700 if (c->socket_id != -1) 701 seq_printf(m, "physical id: %u\n", c->socket_id); 702 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 703 seq_printf(m, 704 "core id : %u\n" 705 "thread id : %u\n", 706 c->core_id, c->thread_id); 707 #endif 708 seq_printf(m,"\n"); 709 710 return 0; 711 } 712 713 static void * 714 c_start (struct seq_file *m, loff_t *pos) 715 { 716 #ifdef CONFIG_SMP 717 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 718 ++*pos; 719 #endif 720 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 721 } 722 723 static void * 724 c_next (struct seq_file *m, void *v, loff_t *pos) 725 { 726 ++*pos; 727 return c_start(m, pos); 728 } 729 730 static void 731 c_stop (struct seq_file *m, void *v) 732 { 733 } 734 735 const struct seq_operations cpuinfo_op = { 736 .start = c_start, 737 .next = c_next, 738 .stop = c_stop, 739 .show = show_cpuinfo 740 }; 741 742 #define MAX_BRANDS 8 743 static char brandname[MAX_BRANDS][128]; 744 745 static char * 746 get_model_name(__u8 family, __u8 model) 747 { 748 static int overflow; 749 char brand[128]; 750 int i; 751 752 memcpy(brand, "Unknown", 8); 753 if (ia64_pal_get_brand_info(brand)) { 754 if (family == 0x7) 755 memcpy(brand, "Merced", 7); 756 else if (family == 0x1f) switch (model) { 757 case 0: memcpy(brand, "McKinley", 9); break; 758 case 1: memcpy(brand, "Madison", 8); break; 759 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 760 } 761 } 762 for (i = 0; i < MAX_BRANDS; i++) 763 if (strcmp(brandname[i], brand) == 0) 764 return brandname[i]; 765 for (i = 0; i < MAX_BRANDS; i++) 766 if (brandname[i][0] == '\0') 767 return strcpy(brandname[i], brand); 768 if (overflow++ == 0) 769 printk(KERN_ERR 770 "%s: Table overflow. Some processor model information will be missing\n", 771 __func__); 772 return "Unknown"; 773 } 774 775 static void 776 identify_cpu (struct cpuinfo_ia64 *c) 777 { 778 union { 779 unsigned long bits[5]; 780 struct { 781 /* id 0 & 1: */ 782 char vendor[16]; 783 784 /* id 2 */ 785 u64 ppn; /* processor serial number */ 786 787 /* id 3: */ 788 unsigned number : 8; 789 unsigned revision : 8; 790 unsigned model : 8; 791 unsigned family : 8; 792 unsigned archrev : 8; 793 unsigned reserved : 24; 794 795 /* id 4: */ 796 u64 features; 797 } field; 798 } cpuid; 799 pal_vm_info_1_u_t vm1; 800 pal_vm_info_2_u_t vm2; 801 pal_status_t status; 802 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 803 int i; 804 for (i = 0; i < 5; ++i) 805 cpuid.bits[i] = ia64_get_cpuid(i); 806 807 memcpy(c->vendor, cpuid.field.vendor, 16); 808 #ifdef CONFIG_SMP 809 c->cpu = smp_processor_id(); 810 811 /* below default values will be overwritten by identify_siblings() 812 * for Multi-Threading/Multi-Core capable CPUs 813 */ 814 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 815 c->socket_id = -1; 816 817 identify_siblings(c); 818 819 if (c->threads_per_core > smp_num_siblings) 820 smp_num_siblings = c->threads_per_core; 821 #endif 822 c->ppn = cpuid.field.ppn; 823 c->number = cpuid.field.number; 824 c->revision = cpuid.field.revision; 825 c->model = cpuid.field.model; 826 c->family = cpuid.field.family; 827 c->archrev = cpuid.field.archrev; 828 c->features = cpuid.field.features; 829 c->model_name = get_model_name(c->family, c->model); 830 831 status = ia64_pal_vm_summary(&vm1, &vm2); 832 if (status == PAL_STATUS_SUCCESS) { 833 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 834 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 835 } 836 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 837 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 838 } 839 840 /* 841 * Do the following calculations: 842 * 843 * 1. the max. cache line size. 844 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 845 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 846 */ 847 static void 848 get_cache_info(void) 849 { 850 unsigned long line_size, max = 1; 851 unsigned long l, levels, unique_caches; 852 pal_cache_config_info_t cci; 853 long status; 854 855 status = ia64_pal_cache_summary(&levels, &unique_caches); 856 if (status != 0) { 857 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 858 __func__, status); 859 max = SMP_CACHE_BYTES; 860 /* Safest setup for "flush_icache_range()" */ 861 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 862 /* Safest setup for "clflush_cache_range()" */ 863 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 864 goto out; 865 } 866 867 for (l = 0; l < levels; ++l) { 868 /* cache_type (data_or_unified)=2 */ 869 status = ia64_pal_cache_config_info(l, 2, &cci); 870 if (status != 0) { 871 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 872 "(l=%lu, 2) failed (status=%ld)\n", 873 __func__, l, status); 874 max = SMP_CACHE_BYTES; 875 /* The safest setup for "flush_icache_range()" */ 876 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 877 /* The safest setup for "clflush_cache_range()" */ 878 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 879 cci.pcci_unified = 1; 880 } else { 881 if (cci.pcci_stride < ia64_cache_stride_shift) 882 ia64_cache_stride_shift = cci.pcci_stride; 883 884 line_size = 1 << cci.pcci_line_size; 885 if (line_size > max) 886 max = line_size; 887 } 888 889 if (!cci.pcci_unified) { 890 /* cache_type (instruction)=1*/ 891 status = ia64_pal_cache_config_info(l, 1, &cci); 892 if (status != 0) { 893 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 894 "(l=%lu, 1) failed (status=%ld)\n", 895 __func__, l, status); 896 /* The safest setup for flush_icache_range() */ 897 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 898 } 899 } 900 if (cci.pcci_stride < ia64_i_cache_stride_shift) 901 ia64_i_cache_stride_shift = cci.pcci_stride; 902 } 903 out: 904 if (max > ia64_max_cacheline_size) 905 ia64_max_cacheline_size = max; 906 } 907 908 /* 909 * cpu_init() initializes state that is per-CPU. This function acts 910 * as a 'CPU state barrier', nothing should get across. 911 */ 912 void 913 cpu_init (void) 914 { 915 extern void ia64_mmu_init(void *); 916 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 917 unsigned long num_phys_stacked; 918 pal_vm_info_2_u_t vmi; 919 unsigned int max_ctx; 920 struct cpuinfo_ia64 *cpu_info; 921 void *cpu_data; 922 923 cpu_data = per_cpu_init(); 924 #ifdef CONFIG_SMP 925 /* 926 * insert boot cpu into sibling and core mapes 927 * (must be done after per_cpu area is setup) 928 */ 929 if (smp_processor_id() == 0) { 930 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0)); 931 cpumask_set_cpu(0, &cpu_core_map[0]); 932 } else { 933 /* 934 * Set ar.k3 so that assembly code in MCA handler can compute 935 * physical addresses of per cpu variables with a simple: 936 * phys = ar.k3 + &per_cpu_var 937 * and the alt-dtlb-miss handler can set per-cpu mapping into 938 * the TLB when needed. head.S already did this for cpu0. 939 */ 940 ia64_set_kr(IA64_KR_PER_CPU_DATA, 941 ia64_tpa(cpu_data) - (long) __per_cpu_start); 942 } 943 #endif 944 945 get_cache_info(); 946 947 /* 948 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 949 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 950 * depends on the data returned by identify_cpu(). We break the dependency by 951 * accessing cpu_data() through the canonical per-CPU address. 952 */ 953 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 954 identify_cpu(cpu_info); 955 956 #ifdef CONFIG_MCKINLEY 957 { 958 # define FEATURE_SET 16 959 struct ia64_pal_retval iprv; 960 961 if (cpu_info->family == 0x1f) { 962 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 963 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 964 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 965 (iprv.v1 | 0x80), FEATURE_SET, 0); 966 } 967 } 968 #endif 969 970 /* Clear the stack memory reserved for pt_regs: */ 971 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 972 973 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 974 975 /* 976 * Initialize the page-table base register to a global 977 * directory with all zeroes. This ensure that we can handle 978 * TLB-misses to user address-space even before we created the 979 * first user address-space. This may happen, e.g., due to 980 * aggressive use of lfetch.fault. 981 */ 982 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 983 984 /* 985 * Initialize default control register to defer speculative faults except 986 * for those arising from TLB misses, which are not deferred. The 987 * kernel MUST NOT depend on a particular setting of these bits (in other words, 988 * the kernel must have recovery code for all speculative accesses). Turn on 989 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 990 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 991 * be fine). 992 */ 993 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 994 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 995 atomic_inc(&init_mm.mm_count); 996 current->active_mm = &init_mm; 997 BUG_ON(current->mm); 998 999 ia64_mmu_init(ia64_imva(cpu_data)); 1000 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1001 1002 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1003 ia64_set_itc(0); 1004 1005 /* disable all local interrupt sources: */ 1006 ia64_set_itv(1 << 16); 1007 ia64_set_lrr0(1 << 16); 1008 ia64_set_lrr1(1 << 16); 1009 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1010 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1011 1012 /* clear TPR & XTP to enable all interrupt classes: */ 1013 ia64_setreg(_IA64_REG_CR_TPR, 0); 1014 1015 /* Clear any pending interrupts left by SAL/EFI */ 1016 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1017 ia64_eoi(); 1018 1019 #ifdef CONFIG_SMP 1020 normal_xtp(); 1021 #endif 1022 1023 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1024 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1025 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1026 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1027 } else { 1028 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1029 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1030 } 1031 while (max_ctx < ia64_ctx.max_ctx) { 1032 unsigned int old = ia64_ctx.max_ctx; 1033 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1034 break; 1035 } 1036 1037 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1038 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1039 "stacked regs\n"); 1040 num_phys_stacked = 96; 1041 } 1042 /* size of physical stacked register partition plus 8 bytes: */ 1043 if (num_phys_stacked > max_num_phys_stacked) { 1044 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1045 max_num_phys_stacked = num_phys_stacked; 1046 } 1047 platform_cpu_init(); 1048 } 1049 1050 void __init 1051 check_bugs (void) 1052 { 1053 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1054 (unsigned long) __end___mckinley_e9_bundles); 1055 } 1056 1057 static int __init run_dmi_scan(void) 1058 { 1059 dmi_scan_machine(); 1060 dmi_memdev_walk(); 1061 dmi_set_dump_stack_arch_desc(); 1062 return 0; 1063 } 1064 core_initcall(run_dmi_scan); 1065