1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/tlbflush.h> 63 #include <asm/unistd.h> 64 #include <asm/hpsim.h> 65 66 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 67 # error "struct cpuinfo_ia64 too big!" 68 #endif 69 70 #ifdef CONFIG_SMP 71 unsigned long __per_cpu_offset[NR_CPUS]; 72 EXPORT_SYMBOL(__per_cpu_offset); 73 #endif 74 75 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 76 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 77 unsigned long ia64_cycles_per_usec; 78 struct ia64_boot_param *ia64_boot_param; 79 struct screen_info screen_info; 80 unsigned long vga_console_iobase; 81 unsigned long vga_console_membase; 82 83 static struct resource data_resource = { 84 .name = "Kernel data", 85 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 86 }; 87 88 static struct resource code_resource = { 89 .name = "Kernel code", 90 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 91 }; 92 93 static struct resource bss_resource = { 94 .name = "Kernel bss", 95 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 96 }; 97 98 unsigned long ia64_max_cacheline_size; 99 100 int dma_get_cache_alignment(void) 101 { 102 return ia64_max_cacheline_size; 103 } 104 EXPORT_SYMBOL(dma_get_cache_alignment); 105 106 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 107 EXPORT_SYMBOL(ia64_iobase); 108 struct io_space io_space[MAX_IO_SPACES]; 109 EXPORT_SYMBOL(io_space); 110 unsigned int num_io_spaces; 111 112 /* 113 * "flush_icache_range()" needs to know what processor dependent stride size to use 114 * when it makes i-cache(s) coherent with d-caches. 115 */ 116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117 unsigned long ia64_i_cache_stride_shift = ~0; 118 119 /* 120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 123 * address of the second buffer must be aligned to (merge_mask+1) in order to be 124 * mergeable). By default, we assume there is no I/O MMU which can merge physically 125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 126 * page-size of 2^64. 127 */ 128 unsigned long ia64_max_iommu_merge_mask = ~0UL; 129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 130 131 /* 132 * We use a special marker for the end of memory and it uses the extra (+1) slot 133 */ 134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 135 int num_rsvd_regions __initdata; 136 137 138 /* 139 * Filter incoming memory segments based on the primitive map created from the boot 140 * parameters. Segments contained in the map are removed from the memory ranges. A 141 * caller-specified function is called with the memory ranges that remain after filtering. 142 * This routine does not assume the incoming segments are sorted. 143 */ 144 int __init 145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 146 { 147 unsigned long range_start, range_end, prev_start; 148 void (*func)(unsigned long, unsigned long, int); 149 int i; 150 151 #if IGNORE_PFN0 152 if (start == PAGE_OFFSET) { 153 printk(KERN_WARNING "warning: skipping physical page 0\n"); 154 start += PAGE_SIZE; 155 if (start >= end) return 0; 156 } 157 #endif 158 /* 159 * lowest possible address(walker uses virtual) 160 */ 161 prev_start = PAGE_OFFSET; 162 func = arg; 163 164 for (i = 0; i < num_rsvd_regions; ++i) { 165 range_start = max(start, prev_start); 166 range_end = min(end, rsvd_region[i].start); 167 168 if (range_start < range_end) 169 call_pernode_memory(__pa(range_start), range_end - range_start, func); 170 171 /* nothing more available in this segment */ 172 if (range_end == end) return 0; 173 174 prev_start = rsvd_region[i].end; 175 } 176 /* end of memory marker allows full processing inside loop body */ 177 return 0; 178 } 179 180 /* 181 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 182 * are not filtered out. 183 */ 184 int __init 185 filter_memory(unsigned long start, unsigned long end, void *arg) 186 { 187 void (*func)(unsigned long, unsigned long, int); 188 189 #if IGNORE_PFN0 190 if (start == PAGE_OFFSET) { 191 printk(KERN_WARNING "warning: skipping physical page 0\n"); 192 start += PAGE_SIZE; 193 if (start >= end) 194 return 0; 195 } 196 #endif 197 func = arg; 198 if (start < end) 199 call_pernode_memory(__pa(start), end - start, func); 200 return 0; 201 } 202 203 static void __init 204 sort_regions (struct rsvd_region *rsvd_region, int max) 205 { 206 int j; 207 208 /* simple bubble sorting */ 209 while (max--) { 210 for (j = 0; j < max; ++j) { 211 if (rsvd_region[j].start > rsvd_region[j+1].start) { 212 struct rsvd_region tmp; 213 tmp = rsvd_region[j]; 214 rsvd_region[j] = rsvd_region[j + 1]; 215 rsvd_region[j + 1] = tmp; 216 } 217 } 218 } 219 } 220 221 /* 222 * Request address space for all standard resources 223 */ 224 static int __init register_memory(void) 225 { 226 code_resource.start = ia64_tpa(_text); 227 code_resource.end = ia64_tpa(_etext) - 1; 228 data_resource.start = ia64_tpa(_etext); 229 data_resource.end = ia64_tpa(_edata) - 1; 230 bss_resource.start = ia64_tpa(__bss_start); 231 bss_resource.end = ia64_tpa(_end) - 1; 232 efi_initialize_iomem_resources(&code_resource, &data_resource, 233 &bss_resource); 234 235 return 0; 236 } 237 238 __initcall(register_memory); 239 240 241 #ifdef CONFIG_KEXEC 242 static void __init setup_crashkernel(unsigned long total, int *n) 243 { 244 unsigned long long base = 0, size = 0; 245 int ret; 246 247 ret = parse_crashkernel(boot_command_line, total, 248 &size, &base); 249 if (ret == 0 && size > 0) { 250 if (!base) { 251 sort_regions(rsvd_region, *n); 252 base = kdump_find_rsvd_region(size, 253 rsvd_region, *n); 254 } 255 if (base != ~0UL) { 256 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 257 "for crashkernel (System RAM: %ldMB)\n", 258 (unsigned long)(size >> 20), 259 (unsigned long)(base >> 20), 260 (unsigned long)(total >> 20)); 261 rsvd_region[*n].start = 262 (unsigned long)__va(base); 263 rsvd_region[*n].end = 264 (unsigned long)__va(base + size); 265 (*n)++; 266 crashk_res.start = base; 267 crashk_res.end = base + size - 1; 268 } 269 } 270 efi_memmap_res.start = ia64_boot_param->efi_memmap; 271 efi_memmap_res.end = efi_memmap_res.start + 272 ia64_boot_param->efi_memmap_size; 273 boot_param_res.start = __pa(ia64_boot_param); 274 boot_param_res.end = boot_param_res.start + 275 sizeof(*ia64_boot_param); 276 } 277 #else 278 static inline void __init setup_crashkernel(unsigned long total, int *n) 279 {} 280 #endif 281 282 /** 283 * reserve_memory - setup reserved memory areas 284 * 285 * Setup the reserved memory areas set aside for the boot parameters, 286 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 287 * see include/asm-ia64/meminit.h if you need to define more. 288 */ 289 void __init 290 reserve_memory (void) 291 { 292 int n = 0; 293 unsigned long total_memory; 294 295 /* 296 * none of the entries in this table overlap 297 */ 298 rsvd_region[n].start = (unsigned long) ia64_boot_param; 299 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 300 n++; 301 302 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 303 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 304 n++; 305 306 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 307 rsvd_region[n].end = (rsvd_region[n].start 308 + strlen(__va(ia64_boot_param->command_line)) + 1); 309 n++; 310 311 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 312 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 313 n++; 314 315 #ifdef CONFIG_BLK_DEV_INITRD 316 if (ia64_boot_param->initrd_start) { 317 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 318 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 319 n++; 320 } 321 #endif 322 323 #ifdef CONFIG_PROC_VMCORE 324 if (reserve_elfcorehdr(&rsvd_region[n].start, 325 &rsvd_region[n].end) == 0) 326 n++; 327 #endif 328 329 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 330 n++; 331 332 setup_crashkernel(total_memory, &n); 333 334 /* end of memory marker */ 335 rsvd_region[n].start = ~0UL; 336 rsvd_region[n].end = ~0UL; 337 n++; 338 339 num_rsvd_regions = n; 340 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 341 342 sort_regions(rsvd_region, num_rsvd_regions); 343 } 344 345 346 /** 347 * find_initrd - get initrd parameters from the boot parameter structure 348 * 349 * Grab the initrd start and end from the boot parameter struct given us by 350 * the boot loader. 351 */ 352 void __init 353 find_initrd (void) 354 { 355 #ifdef CONFIG_BLK_DEV_INITRD 356 if (ia64_boot_param->initrd_start) { 357 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 358 initrd_end = initrd_start+ia64_boot_param->initrd_size; 359 360 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 361 initrd_start, ia64_boot_param->initrd_size); 362 } 363 #endif 364 } 365 366 static void __init 367 io_port_init (void) 368 { 369 unsigned long phys_iobase; 370 371 /* 372 * Set `iobase' based on the EFI memory map or, failing that, the 373 * value firmware left in ar.k0. 374 * 375 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 376 * the port's virtual address, so ia32_load_state() loads it with a 377 * user virtual address. But in ia64 mode, glibc uses the 378 * *physical* address in ar.k0 to mmap the appropriate area from 379 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 380 * cases, user-mode can only use the legacy 0-64K I/O port space. 381 * 382 * ar.k0 is not involved in kernel I/O port accesses, which can use 383 * any of the I/O port spaces and are done via MMIO using the 384 * virtual mmio_base from the appropriate io_space[]. 385 */ 386 phys_iobase = efi_get_iobase(); 387 if (!phys_iobase) { 388 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 389 printk(KERN_INFO "No I/O port range found in EFI memory map, " 390 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 391 } 392 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 393 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 394 395 /* setup legacy IO port space */ 396 io_space[0].mmio_base = ia64_iobase; 397 io_space[0].sparse = 1; 398 num_io_spaces = 1; 399 } 400 401 /** 402 * early_console_setup - setup debugging console 403 * 404 * Consoles started here require little enough setup that we can start using 405 * them very early in the boot process, either right after the machine 406 * vector initialization, or even before if the drivers can detect their hw. 407 * 408 * Returns non-zero if a console couldn't be setup. 409 */ 410 static inline int __init 411 early_console_setup (char *cmdline) 412 { 413 int earlycons = 0; 414 415 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 416 { 417 extern int sn_serial_console_early_setup(void); 418 if (!sn_serial_console_early_setup()) 419 earlycons++; 420 } 421 #endif 422 #ifdef CONFIG_EFI_PCDP 423 if (!efi_setup_pcdp_console(cmdline)) 424 earlycons++; 425 #endif 426 if (!simcons_register()) 427 earlycons++; 428 429 return (earlycons) ? 0 : -1; 430 } 431 432 static inline void 433 mark_bsp_online (void) 434 { 435 #ifdef CONFIG_SMP 436 /* If we register an early console, allow CPU 0 to printk */ 437 cpu_set(smp_processor_id(), cpu_online_map); 438 #endif 439 } 440 441 static __initdata int nomca; 442 static __init int setup_nomca(char *s) 443 { 444 nomca = 1; 445 return 0; 446 } 447 early_param("nomca", setup_nomca); 448 449 #ifdef CONFIG_PROC_VMCORE 450 /* elfcorehdr= specifies the location of elf core header 451 * stored by the crashed kernel. 452 */ 453 static int __init parse_elfcorehdr(char *arg) 454 { 455 if (!arg) 456 return -EINVAL; 457 458 elfcorehdr_addr = memparse(arg, &arg); 459 return 0; 460 } 461 early_param("elfcorehdr", parse_elfcorehdr); 462 463 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 464 { 465 unsigned long length; 466 467 /* We get the address using the kernel command line, 468 * but the size is extracted from the EFI tables. 469 * Both address and size are required for reservation 470 * to work properly. 471 */ 472 473 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) 474 return -EINVAL; 475 476 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 477 elfcorehdr_addr = ELFCORE_ADDR_MAX; 478 return -EINVAL; 479 } 480 481 *start = (unsigned long)__va(elfcorehdr_addr); 482 *end = *start + length; 483 return 0; 484 } 485 486 #endif /* CONFIG_PROC_VMCORE */ 487 488 void __init 489 setup_arch (char **cmdline_p) 490 { 491 unw_init(); 492 493 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 494 495 *cmdline_p = __va(ia64_boot_param->command_line); 496 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 497 498 efi_init(); 499 io_port_init(); 500 501 #ifdef CONFIG_IA64_GENERIC 502 /* machvec needs to be parsed from the command line 503 * before parse_early_param() is called to ensure 504 * that ia64_mv is initialised before any command line 505 * settings may cause console setup to occur 506 */ 507 machvec_init_from_cmdline(*cmdline_p); 508 #endif 509 510 parse_early_param(); 511 512 if (early_console_setup(*cmdline_p) == 0) 513 mark_bsp_online(); 514 515 #ifdef CONFIG_ACPI 516 /* Initialize the ACPI boot-time table parser */ 517 acpi_table_init(); 518 # ifdef CONFIG_ACPI_NUMA 519 acpi_numa_init(); 520 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? 521 32 : cpus_weight(early_cpu_possible_map)), additional_cpus); 522 # endif 523 #else 524 # ifdef CONFIG_SMP 525 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 526 # endif 527 #endif /* CONFIG_APCI_BOOT */ 528 529 find_memory(); 530 531 /* process SAL system table: */ 532 ia64_sal_init(__va(efi.sal_systab)); 533 534 #ifdef CONFIG_SMP 535 cpu_physical_id(0) = hard_smp_processor_id(); 536 #endif 537 538 cpu_init(); /* initialize the bootstrap CPU */ 539 mmu_context_init(); /* initialize context_id bitmap */ 540 541 check_sal_cache_flush(); 542 543 #ifdef CONFIG_ACPI 544 acpi_boot_init(); 545 #endif 546 547 #ifdef CONFIG_VT 548 if (!conswitchp) { 549 # if defined(CONFIG_DUMMY_CONSOLE) 550 conswitchp = &dummy_con; 551 # endif 552 # if defined(CONFIG_VGA_CONSOLE) 553 /* 554 * Non-legacy systems may route legacy VGA MMIO range to system 555 * memory. vga_con probes the MMIO hole, so memory looks like 556 * a VGA device to it. The EFI memory map can tell us if it's 557 * memory so we can avoid this problem. 558 */ 559 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 560 conswitchp = &vga_con; 561 # endif 562 } 563 #endif 564 565 /* enable IA-64 Machine Check Abort Handling unless disabled */ 566 if (!nomca) 567 ia64_mca_init(); 568 569 platform_setup(cmdline_p); 570 paging_init(); 571 } 572 573 /* 574 * Display cpu info for all CPUs. 575 */ 576 static int 577 show_cpuinfo (struct seq_file *m, void *v) 578 { 579 #ifdef CONFIG_SMP 580 # define lpj c->loops_per_jiffy 581 # define cpunum c->cpu 582 #else 583 # define lpj loops_per_jiffy 584 # define cpunum 0 585 #endif 586 static struct { 587 unsigned long mask; 588 const char *feature_name; 589 } feature_bits[] = { 590 { 1UL << 0, "branchlong" }, 591 { 1UL << 1, "spontaneous deferral"}, 592 { 1UL << 2, "16-byte atomic ops" } 593 }; 594 char features[128], *cp, *sep; 595 struct cpuinfo_ia64 *c = v; 596 unsigned long mask; 597 unsigned long proc_freq; 598 int i, size; 599 600 mask = c->features; 601 602 /* build the feature string: */ 603 memcpy(features, "standard", 9); 604 cp = features; 605 size = sizeof(features); 606 sep = ""; 607 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 608 if (mask & feature_bits[i].mask) { 609 cp += snprintf(cp, size, "%s%s", sep, 610 feature_bits[i].feature_name), 611 sep = ", "; 612 mask &= ~feature_bits[i].mask; 613 size = sizeof(features) - (cp - features); 614 } 615 } 616 if (mask && size > 1) { 617 /* print unknown features as a hex value */ 618 snprintf(cp, size, "%s0x%lx", sep, mask); 619 } 620 621 proc_freq = cpufreq_quick_get(cpunum); 622 if (!proc_freq) 623 proc_freq = c->proc_freq / 1000; 624 625 seq_printf(m, 626 "processor : %d\n" 627 "vendor : %s\n" 628 "arch : IA-64\n" 629 "family : %u\n" 630 "model : %u\n" 631 "model name : %s\n" 632 "revision : %u\n" 633 "archrev : %u\n" 634 "features : %s\n" 635 "cpu number : %lu\n" 636 "cpu regs : %u\n" 637 "cpu MHz : %lu.%03lu\n" 638 "itc MHz : %lu.%06lu\n" 639 "BogoMIPS : %lu.%02lu\n", 640 cpunum, c->vendor, c->family, c->model, 641 c->model_name, c->revision, c->archrev, 642 features, c->ppn, c->number, 643 proc_freq / 1000, proc_freq % 1000, 644 c->itc_freq / 1000000, c->itc_freq % 1000000, 645 lpj*HZ/500000, (lpj*HZ/5000) % 100); 646 #ifdef CONFIG_SMP 647 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 648 if (c->socket_id != -1) 649 seq_printf(m, "physical id: %u\n", c->socket_id); 650 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 651 seq_printf(m, 652 "core id : %u\n" 653 "thread id : %u\n", 654 c->core_id, c->thread_id); 655 #endif 656 seq_printf(m,"\n"); 657 658 return 0; 659 } 660 661 static void * 662 c_start (struct seq_file *m, loff_t *pos) 663 { 664 #ifdef CONFIG_SMP 665 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 666 ++*pos; 667 #endif 668 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 669 } 670 671 static void * 672 c_next (struct seq_file *m, void *v, loff_t *pos) 673 { 674 ++*pos; 675 return c_start(m, pos); 676 } 677 678 static void 679 c_stop (struct seq_file *m, void *v) 680 { 681 } 682 683 const struct seq_operations cpuinfo_op = { 684 .start = c_start, 685 .next = c_next, 686 .stop = c_stop, 687 .show = show_cpuinfo 688 }; 689 690 #define MAX_BRANDS 8 691 static char brandname[MAX_BRANDS][128]; 692 693 static char * __cpuinit 694 get_model_name(__u8 family, __u8 model) 695 { 696 static int overflow; 697 char brand[128]; 698 int i; 699 700 memcpy(brand, "Unknown", 8); 701 if (ia64_pal_get_brand_info(brand)) { 702 if (family == 0x7) 703 memcpy(brand, "Merced", 7); 704 else if (family == 0x1f) switch (model) { 705 case 0: memcpy(brand, "McKinley", 9); break; 706 case 1: memcpy(brand, "Madison", 8); break; 707 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 708 } 709 } 710 for (i = 0; i < MAX_BRANDS; i++) 711 if (strcmp(brandname[i], brand) == 0) 712 return brandname[i]; 713 for (i = 0; i < MAX_BRANDS; i++) 714 if (brandname[i][0] == '\0') 715 return strcpy(brandname[i], brand); 716 if (overflow++ == 0) 717 printk(KERN_ERR 718 "%s: Table overflow. Some processor model information will be missing\n", 719 __func__); 720 return "Unknown"; 721 } 722 723 static void __cpuinit 724 identify_cpu (struct cpuinfo_ia64 *c) 725 { 726 union { 727 unsigned long bits[5]; 728 struct { 729 /* id 0 & 1: */ 730 char vendor[16]; 731 732 /* id 2 */ 733 u64 ppn; /* processor serial number */ 734 735 /* id 3: */ 736 unsigned number : 8; 737 unsigned revision : 8; 738 unsigned model : 8; 739 unsigned family : 8; 740 unsigned archrev : 8; 741 unsigned reserved : 24; 742 743 /* id 4: */ 744 u64 features; 745 } field; 746 } cpuid; 747 pal_vm_info_1_u_t vm1; 748 pal_vm_info_2_u_t vm2; 749 pal_status_t status; 750 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 751 int i; 752 for (i = 0; i < 5; ++i) 753 cpuid.bits[i] = ia64_get_cpuid(i); 754 755 memcpy(c->vendor, cpuid.field.vendor, 16); 756 #ifdef CONFIG_SMP 757 c->cpu = smp_processor_id(); 758 759 /* below default values will be overwritten by identify_siblings() 760 * for Multi-Threading/Multi-Core capable CPUs 761 */ 762 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 763 c->socket_id = -1; 764 765 identify_siblings(c); 766 767 if (c->threads_per_core > smp_num_siblings) 768 smp_num_siblings = c->threads_per_core; 769 #endif 770 c->ppn = cpuid.field.ppn; 771 c->number = cpuid.field.number; 772 c->revision = cpuid.field.revision; 773 c->model = cpuid.field.model; 774 c->family = cpuid.field.family; 775 c->archrev = cpuid.field.archrev; 776 c->features = cpuid.field.features; 777 c->model_name = get_model_name(c->family, c->model); 778 779 status = ia64_pal_vm_summary(&vm1, &vm2); 780 if (status == PAL_STATUS_SUCCESS) { 781 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 782 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 783 } 784 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 785 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 786 } 787 788 void __init 789 setup_per_cpu_areas (void) 790 { 791 /* start_kernel() requires this... */ 792 #ifdef CONFIG_ACPI_HOTPLUG_CPU 793 prefill_possible_map(); 794 #endif 795 } 796 797 /* 798 * Calculate the max. cache line size. 799 * 800 * In addition, the minimum of the i-cache stride sizes is calculated for 801 * "flush_icache_range()". 802 */ 803 static void __cpuinit 804 get_max_cacheline_size (void) 805 { 806 unsigned long line_size, max = 1; 807 u64 l, levels, unique_caches; 808 pal_cache_config_info_t cci; 809 s64 status; 810 811 status = ia64_pal_cache_summary(&levels, &unique_caches); 812 if (status != 0) { 813 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 814 __func__, status); 815 max = SMP_CACHE_BYTES; 816 /* Safest setup for "flush_icache_range()" */ 817 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 818 goto out; 819 } 820 821 for (l = 0; l < levels; ++l) { 822 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 823 &cci); 824 if (status != 0) { 825 printk(KERN_ERR 826 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 827 __func__, l, status); 828 max = SMP_CACHE_BYTES; 829 /* The safest setup for "flush_icache_range()" */ 830 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 831 cci.pcci_unified = 1; 832 } 833 line_size = 1 << cci.pcci_line_size; 834 if (line_size > max) 835 max = line_size; 836 if (!cci.pcci_unified) { 837 status = ia64_pal_cache_config_info(l, 838 /* cache_type (instruction)= */ 1, 839 &cci); 840 if (status != 0) { 841 printk(KERN_ERR 842 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 843 __func__, l, status); 844 /* The safest setup for "flush_icache_range()" */ 845 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 846 } 847 } 848 if (cci.pcci_stride < ia64_i_cache_stride_shift) 849 ia64_i_cache_stride_shift = cci.pcci_stride; 850 } 851 out: 852 if (max > ia64_max_cacheline_size) 853 ia64_max_cacheline_size = max; 854 } 855 856 /* 857 * cpu_init() initializes state that is per-CPU. This function acts 858 * as a 'CPU state barrier', nothing should get across. 859 */ 860 void __cpuinit 861 cpu_init (void) 862 { 863 extern void __cpuinit ia64_mmu_init (void *); 864 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 865 unsigned long num_phys_stacked; 866 pal_vm_info_2_u_t vmi; 867 unsigned int max_ctx; 868 struct cpuinfo_ia64 *cpu_info; 869 void *cpu_data; 870 871 cpu_data = per_cpu_init(); 872 #ifdef CONFIG_SMP 873 /* 874 * insert boot cpu into sibling and core mapes 875 * (must be done after per_cpu area is setup) 876 */ 877 if (smp_processor_id() == 0) { 878 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 879 cpu_set(0, cpu_core_map[0]); 880 } 881 #endif 882 883 /* 884 * We set ar.k3 so that assembly code in MCA handler can compute 885 * physical addresses of per cpu variables with a simple: 886 * phys = ar.k3 + &per_cpu_var 887 */ 888 ia64_set_kr(IA64_KR_PER_CPU_DATA, 889 ia64_tpa(cpu_data) - (long) __per_cpu_start); 890 891 get_max_cacheline_size(); 892 893 /* 894 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 895 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 896 * depends on the data returned by identify_cpu(). We break the dependency by 897 * accessing cpu_data() through the canonical per-CPU address. 898 */ 899 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 900 identify_cpu(cpu_info); 901 902 #ifdef CONFIG_MCKINLEY 903 { 904 # define FEATURE_SET 16 905 struct ia64_pal_retval iprv; 906 907 if (cpu_info->family == 0x1f) { 908 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 909 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 910 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 911 (iprv.v1 | 0x80), FEATURE_SET, 0); 912 } 913 } 914 #endif 915 916 /* Clear the stack memory reserved for pt_regs: */ 917 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 918 919 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 920 921 /* 922 * Initialize the page-table base register to a global 923 * directory with all zeroes. This ensure that we can handle 924 * TLB-misses to user address-space even before we created the 925 * first user address-space. This may happen, e.g., due to 926 * aggressive use of lfetch.fault. 927 */ 928 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 929 930 /* 931 * Initialize default control register to defer speculative faults except 932 * for those arising from TLB misses, which are not deferred. The 933 * kernel MUST NOT depend on a particular setting of these bits (in other words, 934 * the kernel must have recovery code for all speculative accesses). Turn on 935 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 936 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 937 * be fine). 938 */ 939 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 940 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 941 atomic_inc(&init_mm.mm_count); 942 current->active_mm = &init_mm; 943 if (current->mm) 944 BUG(); 945 946 ia64_mmu_init(ia64_imva(cpu_data)); 947 ia64_mca_cpu_init(ia64_imva(cpu_data)); 948 949 #ifdef CONFIG_IA32_SUPPORT 950 ia32_cpu_init(); 951 #endif 952 953 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 954 ia64_set_itc(0); 955 956 /* disable all local interrupt sources: */ 957 ia64_set_itv(1 << 16); 958 ia64_set_lrr0(1 << 16); 959 ia64_set_lrr1(1 << 16); 960 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 961 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 962 963 /* clear TPR & XTP to enable all interrupt classes: */ 964 ia64_setreg(_IA64_REG_CR_TPR, 0); 965 966 /* Clear any pending interrupts left by SAL/EFI */ 967 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 968 ia64_eoi(); 969 970 #ifdef CONFIG_SMP 971 normal_xtp(); 972 #endif 973 974 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 975 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 976 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 977 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 978 } else { 979 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 980 max_ctx = (1U << 15) - 1; /* use architected minimum */ 981 } 982 while (max_ctx < ia64_ctx.max_ctx) { 983 unsigned int old = ia64_ctx.max_ctx; 984 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 985 break; 986 } 987 988 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 989 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 990 "stacked regs\n"); 991 num_phys_stacked = 96; 992 } 993 /* size of physical stacked register partition plus 8 bytes: */ 994 if (num_phys_stacked > max_num_phys_stacked) { 995 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 996 max_num_phys_stacked = num_phys_stacked; 997 } 998 platform_cpu_init(); 999 pm_idle = default_idle; 1000 } 1001 1002 void __init 1003 check_bugs (void) 1004 { 1005 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1006 (unsigned long) __end___mckinley_e9_bundles); 1007 } 1008 1009 static int __init run_dmi_scan(void) 1010 { 1011 dmi_scan_machine(); 1012 return 0; 1013 } 1014 core_initcall(run_dmi_scan); 1015