1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/sched/clock.h> 36 #include <linux/seq_file.h> 37 #include <linux/string.h> 38 #include <linux/threads.h> 39 #include <linux/screen_info.h> 40 #include <linux/dmi.h> 41 #include <linux/serial.h> 42 #include <linux/serial_core.h> 43 #include <linux/efi.h> 44 #include <linux/initrd.h> 45 #include <linux/pm.h> 46 #include <linux/cpufreq.h> 47 #include <linux/kexec.h> 48 #include <linux/crash_dump.h> 49 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/tlbflush.h> 62 #include <asm/unistd.h> 63 #include <asm/hpsim.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 75 EXPORT_SYMBOL(ia64_cpu_info); 76 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 77 #ifdef CONFIG_SMP 78 EXPORT_SYMBOL(local_per_cpu_offset); 79 #endif 80 unsigned long ia64_cycles_per_usec; 81 struct ia64_boot_param *ia64_boot_param; 82 struct screen_info screen_info; 83 unsigned long vga_console_iobase; 84 unsigned long vga_console_membase; 85 86 static struct resource data_resource = { 87 .name = "Kernel data", 88 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 89 }; 90 91 static struct resource code_resource = { 92 .name = "Kernel code", 93 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 94 }; 95 96 static struct resource bss_resource = { 97 .name = "Kernel bss", 98 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 99 }; 100 101 unsigned long ia64_max_cacheline_size; 102 103 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 104 EXPORT_SYMBOL(ia64_iobase); 105 struct io_space io_space[MAX_IO_SPACES]; 106 EXPORT_SYMBOL(io_space); 107 unsigned int num_io_spaces; 108 109 /* 110 * "flush_icache_range()" needs to know what processor dependent stride size to use 111 * when it makes i-cache(s) coherent with d-caches. 112 */ 113 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 114 unsigned long ia64_i_cache_stride_shift = ~0; 115 /* 116 * "clflush_cache_range()" needs to know what processor dependent stride size to 117 * use when it flushes cache lines including both d-cache and i-cache. 118 */ 119 /* Safest way to go: 32 bytes by 32 bytes */ 120 #define CACHE_STRIDE_SHIFT 5 121 unsigned long ia64_cache_stride_shift = ~0; 122 123 /* 124 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 125 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 126 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 127 * address of the second buffer must be aligned to (merge_mask+1) in order to be 128 * mergeable). By default, we assume there is no I/O MMU which can merge physically 129 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 130 * page-size of 2^64. 131 */ 132 unsigned long ia64_max_iommu_merge_mask = ~0UL; 133 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 134 135 /* 136 * We use a special marker for the end of memory and it uses the extra (+1) slot 137 */ 138 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 139 int num_rsvd_regions __initdata; 140 141 142 /* 143 * Filter incoming memory segments based on the primitive map created from the boot 144 * parameters. Segments contained in the map are removed from the memory ranges. A 145 * caller-specified function is called with the memory ranges that remain after filtering. 146 * This routine does not assume the incoming segments are sorted. 147 */ 148 int __init 149 filter_rsvd_memory (u64 start, u64 end, void *arg) 150 { 151 u64 range_start, range_end, prev_start; 152 void (*func)(unsigned long, unsigned long, int); 153 int i; 154 155 #if IGNORE_PFN0 156 if (start == PAGE_OFFSET) { 157 printk(KERN_WARNING "warning: skipping physical page 0\n"); 158 start += PAGE_SIZE; 159 if (start >= end) return 0; 160 } 161 #endif 162 /* 163 * lowest possible address(walker uses virtual) 164 */ 165 prev_start = PAGE_OFFSET; 166 func = arg; 167 168 for (i = 0; i < num_rsvd_regions; ++i) { 169 range_start = max(start, prev_start); 170 range_end = min(end, rsvd_region[i].start); 171 172 if (range_start < range_end) 173 call_pernode_memory(__pa(range_start), range_end - range_start, func); 174 175 /* nothing more available in this segment */ 176 if (range_end == end) return 0; 177 178 prev_start = rsvd_region[i].end; 179 } 180 /* end of memory marker allows full processing inside loop body */ 181 return 0; 182 } 183 184 /* 185 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 186 * are not filtered out. 187 */ 188 int __init 189 filter_memory(u64 start, u64 end, void *arg) 190 { 191 void (*func)(unsigned long, unsigned long, int); 192 193 #if IGNORE_PFN0 194 if (start == PAGE_OFFSET) { 195 printk(KERN_WARNING "warning: skipping physical page 0\n"); 196 start += PAGE_SIZE; 197 if (start >= end) 198 return 0; 199 } 200 #endif 201 func = arg; 202 if (start < end) 203 call_pernode_memory(__pa(start), end - start, func); 204 return 0; 205 } 206 207 static void __init 208 sort_regions (struct rsvd_region *rsvd_region, int max) 209 { 210 int j; 211 212 /* simple bubble sorting */ 213 while (max--) { 214 for (j = 0; j < max; ++j) { 215 if (rsvd_region[j].start > rsvd_region[j+1].start) { 216 struct rsvd_region tmp; 217 tmp = rsvd_region[j]; 218 rsvd_region[j] = rsvd_region[j + 1]; 219 rsvd_region[j + 1] = tmp; 220 } 221 } 222 } 223 } 224 225 /* merge overlaps */ 226 static int __init 227 merge_regions (struct rsvd_region *rsvd_region, int max) 228 { 229 int i; 230 for (i = 1; i < max; ++i) { 231 if (rsvd_region[i].start >= rsvd_region[i-1].end) 232 continue; 233 if (rsvd_region[i].end > rsvd_region[i-1].end) 234 rsvd_region[i-1].end = rsvd_region[i].end; 235 --max; 236 memmove(&rsvd_region[i], &rsvd_region[i+1], 237 (max - i) * sizeof(struct rsvd_region)); 238 } 239 return max; 240 } 241 242 /* 243 * Request address space for all standard resources 244 */ 245 static int __init register_memory(void) 246 { 247 code_resource.start = ia64_tpa(_text); 248 code_resource.end = ia64_tpa(_etext) - 1; 249 data_resource.start = ia64_tpa(_etext); 250 data_resource.end = ia64_tpa(_edata) - 1; 251 bss_resource.start = ia64_tpa(__bss_start); 252 bss_resource.end = ia64_tpa(_end) - 1; 253 efi_initialize_iomem_resources(&code_resource, &data_resource, 254 &bss_resource); 255 256 return 0; 257 } 258 259 __initcall(register_memory); 260 261 262 #ifdef CONFIG_KEXEC 263 264 /* 265 * This function checks if the reserved crashkernel is allowed on the specific 266 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 267 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 268 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 269 * in kdump case. See the comment in sba_init() in sba_iommu.c. 270 * 271 * So, the only machvec that really supports loading the kdump kernel 272 * over 4 GB is "sn2". 273 */ 274 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 275 { 276 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 277 return 1; 278 else 279 return pbase < (1UL << 32); 280 } 281 282 static void __init setup_crashkernel(unsigned long total, int *n) 283 { 284 unsigned long long base = 0, size = 0; 285 int ret; 286 287 ret = parse_crashkernel(boot_command_line, total, 288 &size, &base); 289 if (ret == 0 && size > 0) { 290 if (!base) { 291 sort_regions(rsvd_region, *n); 292 *n = merge_regions(rsvd_region, *n); 293 base = kdump_find_rsvd_region(size, 294 rsvd_region, *n); 295 } 296 297 if (!check_crashkernel_memory(base, size)) { 298 pr_warning("crashkernel: There would be kdump memory " 299 "at %ld GB but this is unusable because it " 300 "must\nbe below 4 GB. Change the memory " 301 "configuration of the machine.\n", 302 (unsigned long)(base >> 30)); 303 return; 304 } 305 306 if (base != ~0UL) { 307 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 308 "for crashkernel (System RAM: %ldMB)\n", 309 (unsigned long)(size >> 20), 310 (unsigned long)(base >> 20), 311 (unsigned long)(total >> 20)); 312 rsvd_region[*n].start = 313 (unsigned long)__va(base); 314 rsvd_region[*n].end = 315 (unsigned long)__va(base + size); 316 (*n)++; 317 crashk_res.start = base; 318 crashk_res.end = base + size - 1; 319 } 320 } 321 efi_memmap_res.start = ia64_boot_param->efi_memmap; 322 efi_memmap_res.end = efi_memmap_res.start + 323 ia64_boot_param->efi_memmap_size; 324 boot_param_res.start = __pa(ia64_boot_param); 325 boot_param_res.end = boot_param_res.start + 326 sizeof(*ia64_boot_param); 327 } 328 #else 329 static inline void __init setup_crashkernel(unsigned long total, int *n) 330 {} 331 #endif 332 333 /** 334 * reserve_memory - setup reserved memory areas 335 * 336 * Setup the reserved memory areas set aside for the boot parameters, 337 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 338 * see arch/ia64/include/asm/meminit.h if you need to define more. 339 */ 340 void __init 341 reserve_memory (void) 342 { 343 int n = 0; 344 unsigned long total_memory; 345 346 /* 347 * none of the entries in this table overlap 348 */ 349 rsvd_region[n].start = (unsigned long) ia64_boot_param; 350 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 351 n++; 352 353 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 354 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 355 n++; 356 357 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 358 rsvd_region[n].end = (rsvd_region[n].start 359 + strlen(__va(ia64_boot_param->command_line)) + 1); 360 n++; 361 362 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 363 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 364 n++; 365 366 #ifdef CONFIG_BLK_DEV_INITRD 367 if (ia64_boot_param->initrd_start) { 368 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 369 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 370 n++; 371 } 372 #endif 373 374 #ifdef CONFIG_CRASH_DUMP 375 if (reserve_elfcorehdr(&rsvd_region[n].start, 376 &rsvd_region[n].end) == 0) 377 n++; 378 #endif 379 380 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 381 n++; 382 383 setup_crashkernel(total_memory, &n); 384 385 /* end of memory marker */ 386 rsvd_region[n].start = ~0UL; 387 rsvd_region[n].end = ~0UL; 388 n++; 389 390 num_rsvd_regions = n; 391 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 392 393 sort_regions(rsvd_region, num_rsvd_regions); 394 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions); 395 } 396 397 398 /** 399 * find_initrd - get initrd parameters from the boot parameter structure 400 * 401 * Grab the initrd start and end from the boot parameter struct given us by 402 * the boot loader. 403 */ 404 void __init 405 find_initrd (void) 406 { 407 #ifdef CONFIG_BLK_DEV_INITRD 408 if (ia64_boot_param->initrd_start) { 409 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 410 initrd_end = initrd_start+ia64_boot_param->initrd_size; 411 412 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 413 initrd_start, ia64_boot_param->initrd_size); 414 } 415 #endif 416 } 417 418 static void __init 419 io_port_init (void) 420 { 421 unsigned long phys_iobase; 422 423 /* 424 * Set `iobase' based on the EFI memory map or, failing that, the 425 * value firmware left in ar.k0. 426 * 427 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 428 * the port's virtual address, so ia32_load_state() loads it with a 429 * user virtual address. But in ia64 mode, glibc uses the 430 * *physical* address in ar.k0 to mmap the appropriate area from 431 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 432 * cases, user-mode can only use the legacy 0-64K I/O port space. 433 * 434 * ar.k0 is not involved in kernel I/O port accesses, which can use 435 * any of the I/O port spaces and are done via MMIO using the 436 * virtual mmio_base from the appropriate io_space[]. 437 */ 438 phys_iobase = efi_get_iobase(); 439 if (!phys_iobase) { 440 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 441 printk(KERN_INFO "No I/O port range found in EFI memory map, " 442 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 443 } 444 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 445 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 446 447 /* setup legacy IO port space */ 448 io_space[0].mmio_base = ia64_iobase; 449 io_space[0].sparse = 1; 450 num_io_spaces = 1; 451 } 452 453 /** 454 * early_console_setup - setup debugging console 455 * 456 * Consoles started here require little enough setup that we can start using 457 * them very early in the boot process, either right after the machine 458 * vector initialization, or even before if the drivers can detect their hw. 459 * 460 * Returns non-zero if a console couldn't be setup. 461 */ 462 static inline int __init 463 early_console_setup (char *cmdline) 464 { 465 int earlycons = 0; 466 467 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 468 { 469 extern int sn_serial_console_early_setup(void); 470 if (!sn_serial_console_early_setup()) 471 earlycons++; 472 } 473 #endif 474 #ifdef CONFIG_EFI_PCDP 475 if (!efi_setup_pcdp_console(cmdline)) 476 earlycons++; 477 #endif 478 if (!simcons_register()) 479 earlycons++; 480 481 return (earlycons) ? 0 : -1; 482 } 483 484 static inline void 485 mark_bsp_online (void) 486 { 487 #ifdef CONFIG_SMP 488 /* If we register an early console, allow CPU 0 to printk */ 489 set_cpu_online(smp_processor_id(), true); 490 #endif 491 } 492 493 static __initdata int nomca; 494 static __init int setup_nomca(char *s) 495 { 496 nomca = 1; 497 return 0; 498 } 499 early_param("nomca", setup_nomca); 500 501 #ifdef CONFIG_CRASH_DUMP 502 int __init reserve_elfcorehdr(u64 *start, u64 *end) 503 { 504 u64 length; 505 506 /* We get the address using the kernel command line, 507 * but the size is extracted from the EFI tables. 508 * Both address and size are required for reservation 509 * to work properly. 510 */ 511 512 if (!is_vmcore_usable()) 513 return -EINVAL; 514 515 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 516 vmcore_unusable(); 517 return -EINVAL; 518 } 519 520 *start = (unsigned long)__va(elfcorehdr_addr); 521 *end = *start + length; 522 return 0; 523 } 524 525 #endif /* CONFIG_PROC_VMCORE */ 526 527 void __init 528 setup_arch (char **cmdline_p) 529 { 530 unw_init(); 531 532 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 533 534 *cmdline_p = __va(ia64_boot_param->command_line); 535 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 536 537 efi_init(); 538 io_port_init(); 539 540 #ifdef CONFIG_IA64_GENERIC 541 /* machvec needs to be parsed from the command line 542 * before parse_early_param() is called to ensure 543 * that ia64_mv is initialised before any command line 544 * settings may cause console setup to occur 545 */ 546 machvec_init_from_cmdline(*cmdline_p); 547 #endif 548 549 parse_early_param(); 550 551 if (early_console_setup(*cmdline_p) == 0) 552 mark_bsp_online(); 553 554 #ifdef CONFIG_ACPI 555 /* Initialize the ACPI boot-time table parser */ 556 acpi_table_init(); 557 early_acpi_boot_init(); 558 # ifdef CONFIG_ACPI_NUMA 559 acpi_numa_init(); 560 acpi_numa_fixup(); 561 # ifdef CONFIG_ACPI_HOTPLUG_CPU 562 prefill_possible_map(); 563 # endif 564 per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ? 565 32 : cpumask_weight(&early_cpu_possible_map)), 566 additional_cpus > 0 ? additional_cpus : 0); 567 # endif 568 #endif /* CONFIG_APCI_BOOT */ 569 570 #ifdef CONFIG_SMP 571 smp_build_cpu_map(); 572 #endif 573 find_memory(); 574 575 /* process SAL system table: */ 576 ia64_sal_init(__va(efi.sal_systab)); 577 578 #ifdef CONFIG_ITANIUM 579 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 580 #else 581 { 582 unsigned long num_phys_stacked; 583 584 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 585 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 586 } 587 #endif 588 589 #ifdef CONFIG_SMP 590 cpu_physical_id(0) = hard_smp_processor_id(); 591 #endif 592 593 cpu_init(); /* initialize the bootstrap CPU */ 594 mmu_context_init(); /* initialize context_id bitmap */ 595 596 #ifdef CONFIG_VT 597 if (!conswitchp) { 598 # if defined(CONFIG_DUMMY_CONSOLE) 599 conswitchp = &dummy_con; 600 # endif 601 # if defined(CONFIG_VGA_CONSOLE) 602 /* 603 * Non-legacy systems may route legacy VGA MMIO range to system 604 * memory. vga_con probes the MMIO hole, so memory looks like 605 * a VGA device to it. The EFI memory map can tell us if it's 606 * memory so we can avoid this problem. 607 */ 608 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 609 conswitchp = &vga_con; 610 # endif 611 } 612 #endif 613 614 /* enable IA-64 Machine Check Abort Handling unless disabled */ 615 if (!nomca) 616 ia64_mca_init(); 617 618 platform_setup(cmdline_p); 619 #ifndef CONFIG_IA64_HP_SIM 620 check_sal_cache_flush(); 621 #endif 622 paging_init(); 623 624 clear_sched_clock_stable(); 625 } 626 627 /* 628 * Display cpu info for all CPUs. 629 */ 630 static int 631 show_cpuinfo (struct seq_file *m, void *v) 632 { 633 #ifdef CONFIG_SMP 634 # define lpj c->loops_per_jiffy 635 # define cpunum c->cpu 636 #else 637 # define lpj loops_per_jiffy 638 # define cpunum 0 639 #endif 640 static struct { 641 unsigned long mask; 642 const char *feature_name; 643 } feature_bits[] = { 644 { 1UL << 0, "branchlong" }, 645 { 1UL << 1, "spontaneous deferral"}, 646 { 1UL << 2, "16-byte atomic ops" } 647 }; 648 char features[128], *cp, *sep; 649 struct cpuinfo_ia64 *c = v; 650 unsigned long mask; 651 unsigned long proc_freq; 652 int i, size; 653 654 mask = c->features; 655 656 /* build the feature string: */ 657 memcpy(features, "standard", 9); 658 cp = features; 659 size = sizeof(features); 660 sep = ""; 661 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 662 if (mask & feature_bits[i].mask) { 663 cp += snprintf(cp, size, "%s%s", sep, 664 feature_bits[i].feature_name), 665 sep = ", "; 666 mask &= ~feature_bits[i].mask; 667 size = sizeof(features) - (cp - features); 668 } 669 } 670 if (mask && size > 1) { 671 /* print unknown features as a hex value */ 672 snprintf(cp, size, "%s0x%lx", sep, mask); 673 } 674 675 proc_freq = cpufreq_quick_get(cpunum); 676 if (!proc_freq) 677 proc_freq = c->proc_freq / 1000; 678 679 seq_printf(m, 680 "processor : %d\n" 681 "vendor : %s\n" 682 "arch : IA-64\n" 683 "family : %u\n" 684 "model : %u\n" 685 "model name : %s\n" 686 "revision : %u\n" 687 "archrev : %u\n" 688 "features : %s\n" 689 "cpu number : %lu\n" 690 "cpu regs : %u\n" 691 "cpu MHz : %lu.%03lu\n" 692 "itc MHz : %lu.%06lu\n" 693 "BogoMIPS : %lu.%02lu\n", 694 cpunum, c->vendor, c->family, c->model, 695 c->model_name, c->revision, c->archrev, 696 features, c->ppn, c->number, 697 proc_freq / 1000, proc_freq % 1000, 698 c->itc_freq / 1000000, c->itc_freq % 1000000, 699 lpj*HZ/500000, (lpj*HZ/5000) % 100); 700 #ifdef CONFIG_SMP 701 seq_printf(m, "siblings : %u\n", 702 cpumask_weight(&cpu_core_map[cpunum])); 703 if (c->socket_id != -1) 704 seq_printf(m, "physical id: %u\n", c->socket_id); 705 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 706 seq_printf(m, 707 "core id : %u\n" 708 "thread id : %u\n", 709 c->core_id, c->thread_id); 710 #endif 711 seq_printf(m,"\n"); 712 713 return 0; 714 } 715 716 static void * 717 c_start (struct seq_file *m, loff_t *pos) 718 { 719 #ifdef CONFIG_SMP 720 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 721 ++*pos; 722 #endif 723 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 724 } 725 726 static void * 727 c_next (struct seq_file *m, void *v, loff_t *pos) 728 { 729 ++*pos; 730 return c_start(m, pos); 731 } 732 733 static void 734 c_stop (struct seq_file *m, void *v) 735 { 736 } 737 738 const struct seq_operations cpuinfo_op = { 739 .start = c_start, 740 .next = c_next, 741 .stop = c_stop, 742 .show = show_cpuinfo 743 }; 744 745 #define MAX_BRANDS 8 746 static char brandname[MAX_BRANDS][128]; 747 748 static char * 749 get_model_name(__u8 family, __u8 model) 750 { 751 static int overflow; 752 char brand[128]; 753 int i; 754 755 memcpy(brand, "Unknown", 8); 756 if (ia64_pal_get_brand_info(brand)) { 757 if (family == 0x7) 758 memcpy(brand, "Merced", 7); 759 else if (family == 0x1f) switch (model) { 760 case 0: memcpy(brand, "McKinley", 9); break; 761 case 1: memcpy(brand, "Madison", 8); break; 762 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 763 } 764 } 765 for (i = 0; i < MAX_BRANDS; i++) 766 if (strcmp(brandname[i], brand) == 0) 767 return brandname[i]; 768 for (i = 0; i < MAX_BRANDS; i++) 769 if (brandname[i][0] == '\0') 770 return strcpy(brandname[i], brand); 771 if (overflow++ == 0) 772 printk(KERN_ERR 773 "%s: Table overflow. Some processor model information will be missing\n", 774 __func__); 775 return "Unknown"; 776 } 777 778 static void 779 identify_cpu (struct cpuinfo_ia64 *c) 780 { 781 union { 782 unsigned long bits[5]; 783 struct { 784 /* id 0 & 1: */ 785 char vendor[16]; 786 787 /* id 2 */ 788 u64 ppn; /* processor serial number */ 789 790 /* id 3: */ 791 unsigned number : 8; 792 unsigned revision : 8; 793 unsigned model : 8; 794 unsigned family : 8; 795 unsigned archrev : 8; 796 unsigned reserved : 24; 797 798 /* id 4: */ 799 u64 features; 800 } field; 801 } cpuid; 802 pal_vm_info_1_u_t vm1; 803 pal_vm_info_2_u_t vm2; 804 pal_status_t status; 805 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 806 int i; 807 for (i = 0; i < 5; ++i) 808 cpuid.bits[i] = ia64_get_cpuid(i); 809 810 memcpy(c->vendor, cpuid.field.vendor, 16); 811 #ifdef CONFIG_SMP 812 c->cpu = smp_processor_id(); 813 814 /* below default values will be overwritten by identify_siblings() 815 * for Multi-Threading/Multi-Core capable CPUs 816 */ 817 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 818 c->socket_id = -1; 819 820 identify_siblings(c); 821 822 if (c->threads_per_core > smp_num_siblings) 823 smp_num_siblings = c->threads_per_core; 824 #endif 825 c->ppn = cpuid.field.ppn; 826 c->number = cpuid.field.number; 827 c->revision = cpuid.field.revision; 828 c->model = cpuid.field.model; 829 c->family = cpuid.field.family; 830 c->archrev = cpuid.field.archrev; 831 c->features = cpuid.field.features; 832 c->model_name = get_model_name(c->family, c->model); 833 834 status = ia64_pal_vm_summary(&vm1, &vm2); 835 if (status == PAL_STATUS_SUCCESS) { 836 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 837 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 838 } 839 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 840 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 841 } 842 843 /* 844 * Do the following calculations: 845 * 846 * 1. the max. cache line size. 847 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 848 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 849 */ 850 static void 851 get_cache_info(void) 852 { 853 unsigned long line_size, max = 1; 854 unsigned long l, levels, unique_caches; 855 pal_cache_config_info_t cci; 856 long status; 857 858 status = ia64_pal_cache_summary(&levels, &unique_caches); 859 if (status != 0) { 860 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 861 __func__, status); 862 max = SMP_CACHE_BYTES; 863 /* Safest setup for "flush_icache_range()" */ 864 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 865 /* Safest setup for "clflush_cache_range()" */ 866 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 867 goto out; 868 } 869 870 for (l = 0; l < levels; ++l) { 871 /* cache_type (data_or_unified)=2 */ 872 status = ia64_pal_cache_config_info(l, 2, &cci); 873 if (status != 0) { 874 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 875 "(l=%lu, 2) failed (status=%ld)\n", 876 __func__, l, status); 877 max = SMP_CACHE_BYTES; 878 /* The safest setup for "flush_icache_range()" */ 879 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 880 /* The safest setup for "clflush_cache_range()" */ 881 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 882 cci.pcci_unified = 1; 883 } else { 884 if (cci.pcci_stride < ia64_cache_stride_shift) 885 ia64_cache_stride_shift = cci.pcci_stride; 886 887 line_size = 1 << cci.pcci_line_size; 888 if (line_size > max) 889 max = line_size; 890 } 891 892 if (!cci.pcci_unified) { 893 /* cache_type (instruction)=1*/ 894 status = ia64_pal_cache_config_info(l, 1, &cci); 895 if (status != 0) { 896 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 897 "(l=%lu, 1) failed (status=%ld)\n", 898 __func__, l, status); 899 /* The safest setup for flush_icache_range() */ 900 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 901 } 902 } 903 if (cci.pcci_stride < ia64_i_cache_stride_shift) 904 ia64_i_cache_stride_shift = cci.pcci_stride; 905 } 906 out: 907 if (max > ia64_max_cacheline_size) 908 ia64_max_cacheline_size = max; 909 } 910 911 /* 912 * cpu_init() initializes state that is per-CPU. This function acts 913 * as a 'CPU state barrier', nothing should get across. 914 */ 915 void 916 cpu_init (void) 917 { 918 extern void ia64_mmu_init(void *); 919 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 920 unsigned long num_phys_stacked; 921 pal_vm_info_2_u_t vmi; 922 unsigned int max_ctx; 923 struct cpuinfo_ia64 *cpu_info; 924 void *cpu_data; 925 926 cpu_data = per_cpu_init(); 927 #ifdef CONFIG_SMP 928 /* 929 * insert boot cpu into sibling and core mapes 930 * (must be done after per_cpu area is setup) 931 */ 932 if (smp_processor_id() == 0) { 933 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0)); 934 cpumask_set_cpu(0, &cpu_core_map[0]); 935 } else { 936 /* 937 * Set ar.k3 so that assembly code in MCA handler can compute 938 * physical addresses of per cpu variables with a simple: 939 * phys = ar.k3 + &per_cpu_var 940 * and the alt-dtlb-miss handler can set per-cpu mapping into 941 * the TLB when needed. head.S already did this for cpu0. 942 */ 943 ia64_set_kr(IA64_KR_PER_CPU_DATA, 944 ia64_tpa(cpu_data) - (long) __per_cpu_start); 945 } 946 #endif 947 948 get_cache_info(); 949 950 /* 951 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 952 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 953 * depends on the data returned by identify_cpu(). We break the dependency by 954 * accessing cpu_data() through the canonical per-CPU address. 955 */ 956 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 957 identify_cpu(cpu_info); 958 959 #ifdef CONFIG_MCKINLEY 960 { 961 # define FEATURE_SET 16 962 struct ia64_pal_retval iprv; 963 964 if (cpu_info->family == 0x1f) { 965 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 966 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 967 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 968 (iprv.v1 | 0x80), FEATURE_SET, 0); 969 } 970 } 971 #endif 972 973 /* Clear the stack memory reserved for pt_regs: */ 974 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 975 976 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 977 978 /* 979 * Initialize the page-table base register to a global 980 * directory with all zeroes. This ensure that we can handle 981 * TLB-misses to user address-space even before we created the 982 * first user address-space. This may happen, e.g., due to 983 * aggressive use of lfetch.fault. 984 */ 985 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 986 987 /* 988 * Initialize default control register to defer speculative faults except 989 * for those arising from TLB misses, which are not deferred. The 990 * kernel MUST NOT depend on a particular setting of these bits (in other words, 991 * the kernel must have recovery code for all speculative accesses). Turn on 992 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 993 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 994 * be fine). 995 */ 996 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 997 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 998 mmgrab(&init_mm); 999 current->active_mm = &init_mm; 1000 BUG_ON(current->mm); 1001 1002 ia64_mmu_init(ia64_imva(cpu_data)); 1003 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1004 1005 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1006 ia64_set_itc(0); 1007 1008 /* disable all local interrupt sources: */ 1009 ia64_set_itv(1 << 16); 1010 ia64_set_lrr0(1 << 16); 1011 ia64_set_lrr1(1 << 16); 1012 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1013 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1014 1015 /* clear TPR & XTP to enable all interrupt classes: */ 1016 ia64_setreg(_IA64_REG_CR_TPR, 0); 1017 1018 /* Clear any pending interrupts left by SAL/EFI */ 1019 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1020 ia64_eoi(); 1021 1022 #ifdef CONFIG_SMP 1023 normal_xtp(); 1024 #endif 1025 1026 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1027 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1028 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1029 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1030 } else { 1031 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1032 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1033 } 1034 while (max_ctx < ia64_ctx.max_ctx) { 1035 unsigned int old = ia64_ctx.max_ctx; 1036 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1037 break; 1038 } 1039 1040 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1041 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1042 "stacked regs\n"); 1043 num_phys_stacked = 96; 1044 } 1045 /* size of physical stacked register partition plus 8 bytes: */ 1046 if (num_phys_stacked > max_num_phys_stacked) { 1047 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1048 max_num_phys_stacked = num_phys_stacked; 1049 } 1050 platform_cpu_init(); 1051 } 1052 1053 void __init 1054 check_bugs (void) 1055 { 1056 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1057 (unsigned long) __end___mckinley_e9_bundles); 1058 } 1059 1060 static int __init run_dmi_scan(void) 1061 { 1062 dmi_scan_machine(); 1063 dmi_memdev_walk(); 1064 dmi_set_dump_stack_arch_desc(); 1065 return 0; 1066 } 1067 core_initcall(run_dmi_scan); 1068