1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/config.h> 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/bootmem.h> 31 #include <linux/console.h> 32 #include <linux/delay.h> 33 #include <linux/kernel.h> 34 #include <linux/reboot.h> 35 #include <linux/sched.h> 36 #include <linux/seq_file.h> 37 #include <linux/string.h> 38 #include <linux/threads.h> 39 #include <linux/tty.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/platform.h> 45 #include <linux/pm.h> 46 47 #include <asm/ia32.h> 48 #include <asm/machvec.h> 49 #include <asm/mca.h> 50 #include <asm/meminit.h> 51 #include <asm/page.h> 52 #include <asm/patch.h> 53 #include <asm/pgtable.h> 54 #include <asm/processor.h> 55 #include <asm/sal.h> 56 #include <asm/sections.h> 57 #include <asm/serial.h> 58 #include <asm/setup.h> 59 #include <asm/smp.h> 60 #include <asm/system.h> 61 #include <asm/unistd.h> 62 63 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 64 # error "struct cpuinfo_ia64 too big!" 65 #endif 66 67 #ifdef CONFIG_SMP 68 unsigned long __per_cpu_offset[NR_CPUS]; 69 EXPORT_SYMBOL(__per_cpu_offset); 70 #endif 71 72 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 73 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 74 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 75 unsigned long ia64_cycles_per_usec; 76 struct ia64_boot_param *ia64_boot_param; 77 struct screen_info screen_info; 78 unsigned long vga_console_iobase; 79 unsigned long vga_console_membase; 80 81 static struct resource data_resource = { 82 .name = "Kernel data", 83 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 84 }; 85 86 static struct resource code_resource = { 87 .name = "Kernel code", 88 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 89 }; 90 extern void efi_initialize_iomem_resources(struct resource *, 91 struct resource *); 92 extern char _text[], _end[], _etext[]; 93 94 unsigned long ia64_max_cacheline_size; 95 96 int dma_get_cache_alignment(void) 97 { 98 return ia64_max_cacheline_size; 99 } 100 EXPORT_SYMBOL(dma_get_cache_alignment); 101 102 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 103 EXPORT_SYMBOL(ia64_iobase); 104 struct io_space io_space[MAX_IO_SPACES]; 105 EXPORT_SYMBOL(io_space); 106 unsigned int num_io_spaces; 107 108 /* 109 * "flush_icache_range()" needs to know what processor dependent stride size to use 110 * when it makes i-cache(s) coherent with d-caches. 111 */ 112 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 113 unsigned long ia64_i_cache_stride_shift = ~0; 114 115 /* 116 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 117 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 118 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 119 * address of the second buffer must be aligned to (merge_mask+1) in order to be 120 * mergeable). By default, we assume there is no I/O MMU which can merge physically 121 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 122 * page-size of 2^64. 123 */ 124 unsigned long ia64_max_iommu_merge_mask = ~0UL; 125 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 126 127 /* 128 * We use a special marker for the end of memory and it uses the extra (+1) slot 129 */ 130 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1]; 131 int num_rsvd_regions; 132 133 134 /* 135 * Filter incoming memory segments based on the primitive map created from the boot 136 * parameters. Segments contained in the map are removed from the memory ranges. A 137 * caller-specified function is called with the memory ranges that remain after filtering. 138 * This routine does not assume the incoming segments are sorted. 139 */ 140 int 141 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 142 { 143 unsigned long range_start, range_end, prev_start; 144 void (*func)(unsigned long, unsigned long, int); 145 int i; 146 147 #if IGNORE_PFN0 148 if (start == PAGE_OFFSET) { 149 printk(KERN_WARNING "warning: skipping physical page 0\n"); 150 start += PAGE_SIZE; 151 if (start >= end) return 0; 152 } 153 #endif 154 /* 155 * lowest possible address(walker uses virtual) 156 */ 157 prev_start = PAGE_OFFSET; 158 func = arg; 159 160 for (i = 0; i < num_rsvd_regions; ++i) { 161 range_start = max(start, prev_start); 162 range_end = min(end, rsvd_region[i].start); 163 164 if (range_start < range_end) 165 call_pernode_memory(__pa(range_start), range_end - range_start, func); 166 167 /* nothing more available in this segment */ 168 if (range_end == end) return 0; 169 170 prev_start = rsvd_region[i].end; 171 } 172 /* end of memory marker allows full processing inside loop body */ 173 return 0; 174 } 175 176 static void 177 sort_regions (struct rsvd_region *rsvd_region, int max) 178 { 179 int j; 180 181 /* simple bubble sorting */ 182 while (max--) { 183 for (j = 0; j < max; ++j) { 184 if (rsvd_region[j].start > rsvd_region[j+1].start) { 185 struct rsvd_region tmp; 186 tmp = rsvd_region[j]; 187 rsvd_region[j] = rsvd_region[j + 1]; 188 rsvd_region[j + 1] = tmp; 189 } 190 } 191 } 192 } 193 194 /* 195 * Request address space for all standard resources 196 */ 197 static int __init register_memory(void) 198 { 199 code_resource.start = ia64_tpa(_text); 200 code_resource.end = ia64_tpa(_etext) - 1; 201 data_resource.start = ia64_tpa(_etext); 202 data_resource.end = ia64_tpa(_end) - 1; 203 efi_initialize_iomem_resources(&code_resource, &data_resource); 204 205 return 0; 206 } 207 208 __initcall(register_memory); 209 210 /** 211 * reserve_memory - setup reserved memory areas 212 * 213 * Setup the reserved memory areas set aside for the boot parameters, 214 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 215 * see include/asm-ia64/meminit.h if you need to define more. 216 */ 217 void 218 reserve_memory (void) 219 { 220 int n = 0; 221 222 /* 223 * none of the entries in this table overlap 224 */ 225 rsvd_region[n].start = (unsigned long) ia64_boot_param; 226 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 227 n++; 228 229 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 230 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 231 n++; 232 233 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 234 rsvd_region[n].end = (rsvd_region[n].start 235 + strlen(__va(ia64_boot_param->command_line)) + 1); 236 n++; 237 238 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 239 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 240 n++; 241 242 #ifdef CONFIG_BLK_DEV_INITRD 243 if (ia64_boot_param->initrd_start) { 244 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 245 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 246 n++; 247 } 248 #endif 249 250 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 251 n++; 252 253 /* end of memory marker */ 254 rsvd_region[n].start = ~0UL; 255 rsvd_region[n].end = ~0UL; 256 n++; 257 258 num_rsvd_regions = n; 259 260 sort_regions(rsvd_region, num_rsvd_regions); 261 } 262 263 /** 264 * find_initrd - get initrd parameters from the boot parameter structure 265 * 266 * Grab the initrd start and end from the boot parameter struct given us by 267 * the boot loader. 268 */ 269 void 270 find_initrd (void) 271 { 272 #ifdef CONFIG_BLK_DEV_INITRD 273 if (ia64_boot_param->initrd_start) { 274 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 275 initrd_end = initrd_start+ia64_boot_param->initrd_size; 276 277 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 278 initrd_start, ia64_boot_param->initrd_size); 279 } 280 #endif 281 } 282 283 static void __init 284 io_port_init (void) 285 { 286 unsigned long phys_iobase; 287 288 /* 289 * Set `iobase' based on the EFI memory map or, failing that, the 290 * value firmware left in ar.k0. 291 * 292 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 293 * the port's virtual address, so ia32_load_state() loads it with a 294 * user virtual address. But in ia64 mode, glibc uses the 295 * *physical* address in ar.k0 to mmap the appropriate area from 296 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 297 * cases, user-mode can only use the legacy 0-64K I/O port space. 298 * 299 * ar.k0 is not involved in kernel I/O port accesses, which can use 300 * any of the I/O port spaces and are done via MMIO using the 301 * virtual mmio_base from the appropriate io_space[]. 302 */ 303 phys_iobase = efi_get_iobase(); 304 if (!phys_iobase) { 305 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 306 printk(KERN_INFO "No I/O port range found in EFI memory map, " 307 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 308 } 309 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 310 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 311 312 /* setup legacy IO port space */ 313 io_space[0].mmio_base = ia64_iobase; 314 io_space[0].sparse = 1; 315 num_io_spaces = 1; 316 } 317 318 /** 319 * early_console_setup - setup debugging console 320 * 321 * Consoles started here require little enough setup that we can start using 322 * them very early in the boot process, either right after the machine 323 * vector initialization, or even before if the drivers can detect their hw. 324 * 325 * Returns non-zero if a console couldn't be setup. 326 */ 327 static inline int __init 328 early_console_setup (char *cmdline) 329 { 330 int earlycons = 0; 331 332 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 333 { 334 extern int sn_serial_console_early_setup(void); 335 if (!sn_serial_console_early_setup()) 336 earlycons++; 337 } 338 #endif 339 #ifdef CONFIG_EFI_PCDP 340 if (!efi_setup_pcdp_console(cmdline)) 341 earlycons++; 342 #endif 343 #ifdef CONFIG_SERIAL_8250_CONSOLE 344 if (!early_serial_console_init(cmdline)) 345 earlycons++; 346 #endif 347 348 return (earlycons) ? 0 : -1; 349 } 350 351 static inline void 352 mark_bsp_online (void) 353 { 354 #ifdef CONFIG_SMP 355 /* If we register an early console, allow CPU 0 to printk */ 356 cpu_set(smp_processor_id(), cpu_online_map); 357 #endif 358 } 359 360 #ifdef CONFIG_SMP 361 static void 362 check_for_logical_procs (void) 363 { 364 pal_logical_to_physical_t info; 365 s64 status; 366 367 status = ia64_pal_logical_to_phys(0, &info); 368 if (status == -1) { 369 printk(KERN_INFO "No logical to physical processor mapping " 370 "available\n"); 371 return; 372 } 373 if (status) { 374 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 375 status); 376 return; 377 } 378 /* 379 * Total number of siblings that BSP has. Though not all of them 380 * may have booted successfully. The correct number of siblings 381 * booted is in info.overview_num_log. 382 */ 383 smp_num_siblings = info.overview_tpc; 384 smp_num_cpucores = info.overview_cpp; 385 } 386 #endif 387 388 void __init 389 setup_arch (char **cmdline_p) 390 { 391 unw_init(); 392 393 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 394 395 *cmdline_p = __va(ia64_boot_param->command_line); 396 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 397 398 efi_init(); 399 io_port_init(); 400 401 #ifdef CONFIG_IA64_GENERIC 402 { 403 const char *mvec_name = strstr (*cmdline_p, "machvec="); 404 char str[64]; 405 406 if (mvec_name) { 407 const char *end; 408 size_t len; 409 410 mvec_name += 8; 411 end = strchr (mvec_name, ' '); 412 if (end) 413 len = end - mvec_name; 414 else 415 len = strlen (mvec_name); 416 len = min(len, sizeof (str) - 1); 417 strncpy (str, mvec_name, len); 418 str[len] = '\0'; 419 mvec_name = str; 420 } else 421 mvec_name = acpi_get_sysname(); 422 machvec_init(mvec_name); 423 } 424 #endif 425 426 if (early_console_setup(*cmdline_p) == 0) 427 mark_bsp_online(); 428 429 #ifdef CONFIG_ACPI 430 /* Initialize the ACPI boot-time table parser */ 431 acpi_table_init(); 432 # ifdef CONFIG_ACPI_NUMA 433 acpi_numa_init(); 434 # endif 435 #else 436 # ifdef CONFIG_SMP 437 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 438 # endif 439 #endif /* CONFIG_APCI_BOOT */ 440 441 find_memory(); 442 443 /* process SAL system table: */ 444 ia64_sal_init(efi.sal_systab); 445 446 #ifdef CONFIG_SMP 447 cpu_physical_id(0) = hard_smp_processor_id(); 448 449 cpu_set(0, cpu_sibling_map[0]); 450 cpu_set(0, cpu_core_map[0]); 451 452 check_for_logical_procs(); 453 if (smp_num_cpucores > 1) 454 printk(KERN_INFO 455 "cpu package is Multi-Core capable: number of cores=%d\n", 456 smp_num_cpucores); 457 if (smp_num_siblings > 1) 458 printk(KERN_INFO 459 "cpu package is Multi-Threading capable: number of siblings=%d\n", 460 smp_num_siblings); 461 #endif 462 463 cpu_init(); /* initialize the bootstrap CPU */ 464 465 #ifdef CONFIG_ACPI 466 acpi_boot_init(); 467 #endif 468 469 #ifdef CONFIG_VT 470 if (!conswitchp) { 471 # if defined(CONFIG_DUMMY_CONSOLE) 472 conswitchp = &dummy_con; 473 # endif 474 # if defined(CONFIG_VGA_CONSOLE) 475 /* 476 * Non-legacy systems may route legacy VGA MMIO range to system 477 * memory. vga_con probes the MMIO hole, so memory looks like 478 * a VGA device to it. The EFI memory map can tell us if it's 479 * memory so we can avoid this problem. 480 */ 481 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 482 conswitchp = &vga_con; 483 # endif 484 } 485 #endif 486 487 /* enable IA-64 Machine Check Abort Handling unless disabled */ 488 if (!strstr(saved_command_line, "nomca")) 489 ia64_mca_init(); 490 491 platform_setup(cmdline_p); 492 paging_init(); 493 } 494 495 /* 496 * Display cpu info for all cpu's. 497 */ 498 static int 499 show_cpuinfo (struct seq_file *m, void *v) 500 { 501 #ifdef CONFIG_SMP 502 # define lpj c->loops_per_jiffy 503 # define cpunum c->cpu 504 #else 505 # define lpj loops_per_jiffy 506 # define cpunum 0 507 #endif 508 static struct { 509 unsigned long mask; 510 const char *feature_name; 511 } feature_bits[] = { 512 { 1UL << 0, "branchlong" }, 513 { 1UL << 1, "spontaneous deferral"}, 514 { 1UL << 2, "16-byte atomic ops" } 515 }; 516 char family[32], features[128], *cp, sep; 517 struct cpuinfo_ia64 *c = v; 518 unsigned long mask; 519 int i; 520 521 mask = c->features; 522 523 switch (c->family) { 524 case 0x07: memcpy(family, "Itanium", 8); break; 525 case 0x1f: memcpy(family, "Itanium 2", 10); break; 526 default: sprintf(family, "%u", c->family); break; 527 } 528 529 /* build the feature string: */ 530 memcpy(features, " standard", 10); 531 cp = features; 532 sep = 0; 533 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 534 if (mask & feature_bits[i].mask) { 535 if (sep) 536 *cp++ = sep; 537 sep = ','; 538 *cp++ = ' '; 539 strcpy(cp, feature_bits[i].feature_name); 540 cp += strlen(feature_bits[i].feature_name); 541 mask &= ~feature_bits[i].mask; 542 } 543 } 544 if (mask) { 545 /* print unknown features as a hex value: */ 546 if (sep) 547 *cp++ = sep; 548 sprintf(cp, " 0x%lx", mask); 549 } 550 551 seq_printf(m, 552 "processor : %d\n" 553 "vendor : %s\n" 554 "arch : IA-64\n" 555 "family : %s\n" 556 "model : %u\n" 557 "revision : %u\n" 558 "archrev : %u\n" 559 "features :%s\n" /* don't change this---it _is_ right! */ 560 "cpu number : %lu\n" 561 "cpu regs : %u\n" 562 "cpu MHz : %lu.%06lu\n" 563 "itc MHz : %lu.%06lu\n" 564 "BogoMIPS : %lu.%02lu\n", 565 cpunum, c->vendor, family, c->model, c->revision, c->archrev, 566 features, c->ppn, c->number, 567 c->proc_freq / 1000000, c->proc_freq % 1000000, 568 c->itc_freq / 1000000, c->itc_freq % 1000000, 569 lpj*HZ/500000, (lpj*HZ/5000) % 100); 570 #ifdef CONFIG_SMP 571 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 572 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 573 seq_printf(m, 574 "physical id: %u\n" 575 "core id : %u\n" 576 "thread id : %u\n", 577 c->socket_id, c->core_id, c->thread_id); 578 #endif 579 seq_printf(m,"\n"); 580 581 return 0; 582 } 583 584 static void * 585 c_start (struct seq_file *m, loff_t *pos) 586 { 587 #ifdef CONFIG_SMP 588 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 589 ++*pos; 590 #endif 591 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 592 } 593 594 static void * 595 c_next (struct seq_file *m, void *v, loff_t *pos) 596 { 597 ++*pos; 598 return c_start(m, pos); 599 } 600 601 static void 602 c_stop (struct seq_file *m, void *v) 603 { 604 } 605 606 struct seq_operations cpuinfo_op = { 607 .start = c_start, 608 .next = c_next, 609 .stop = c_stop, 610 .show = show_cpuinfo 611 }; 612 613 void 614 identify_cpu (struct cpuinfo_ia64 *c) 615 { 616 union { 617 unsigned long bits[5]; 618 struct { 619 /* id 0 & 1: */ 620 char vendor[16]; 621 622 /* id 2 */ 623 u64 ppn; /* processor serial number */ 624 625 /* id 3: */ 626 unsigned number : 8; 627 unsigned revision : 8; 628 unsigned model : 8; 629 unsigned family : 8; 630 unsigned archrev : 8; 631 unsigned reserved : 24; 632 633 /* id 4: */ 634 u64 features; 635 } field; 636 } cpuid; 637 pal_vm_info_1_u_t vm1; 638 pal_vm_info_2_u_t vm2; 639 pal_status_t status; 640 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 641 int i; 642 643 for (i = 0; i < 5; ++i) 644 cpuid.bits[i] = ia64_get_cpuid(i); 645 646 memcpy(c->vendor, cpuid.field.vendor, 16); 647 #ifdef CONFIG_SMP 648 c->cpu = smp_processor_id(); 649 650 /* below default values will be overwritten by identify_siblings() 651 * for Multi-Threading/Multi-Core capable cpu's 652 */ 653 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 654 c->socket_id = -1; 655 656 identify_siblings(c); 657 #endif 658 c->ppn = cpuid.field.ppn; 659 c->number = cpuid.field.number; 660 c->revision = cpuid.field.revision; 661 c->model = cpuid.field.model; 662 c->family = cpuid.field.family; 663 c->archrev = cpuid.field.archrev; 664 c->features = cpuid.field.features; 665 666 status = ia64_pal_vm_summary(&vm1, &vm2); 667 if (status == PAL_STATUS_SUCCESS) { 668 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 669 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 670 } 671 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 672 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 673 } 674 675 void 676 setup_per_cpu_areas (void) 677 { 678 /* start_kernel() requires this... */ 679 } 680 681 /* 682 * Calculate the max. cache line size. 683 * 684 * In addition, the minimum of the i-cache stride sizes is calculated for 685 * "flush_icache_range()". 686 */ 687 static void 688 get_max_cacheline_size (void) 689 { 690 unsigned long line_size, max = 1; 691 u64 l, levels, unique_caches; 692 pal_cache_config_info_t cci; 693 s64 status; 694 695 status = ia64_pal_cache_summary(&levels, &unique_caches); 696 if (status != 0) { 697 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 698 __FUNCTION__, status); 699 max = SMP_CACHE_BYTES; 700 /* Safest setup for "flush_icache_range()" */ 701 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 702 goto out; 703 } 704 705 for (l = 0; l < levels; ++l) { 706 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 707 &cci); 708 if (status != 0) { 709 printk(KERN_ERR 710 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 711 __FUNCTION__, l, status); 712 max = SMP_CACHE_BYTES; 713 /* The safest setup for "flush_icache_range()" */ 714 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 715 cci.pcci_unified = 1; 716 } 717 line_size = 1 << cci.pcci_line_size; 718 if (line_size > max) 719 max = line_size; 720 if (!cci.pcci_unified) { 721 status = ia64_pal_cache_config_info(l, 722 /* cache_type (instruction)= */ 1, 723 &cci); 724 if (status != 0) { 725 printk(KERN_ERR 726 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 727 __FUNCTION__, l, status); 728 /* The safest setup for "flush_icache_range()" */ 729 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 730 } 731 } 732 if (cci.pcci_stride < ia64_i_cache_stride_shift) 733 ia64_i_cache_stride_shift = cci.pcci_stride; 734 } 735 out: 736 if (max > ia64_max_cacheline_size) 737 ia64_max_cacheline_size = max; 738 } 739 740 /* 741 * cpu_init() initializes state that is per-CPU. This function acts 742 * as a 'CPU state barrier', nothing should get across. 743 */ 744 void 745 cpu_init (void) 746 { 747 extern void __devinit ia64_mmu_init (void *); 748 unsigned long num_phys_stacked; 749 pal_vm_info_2_u_t vmi; 750 unsigned int max_ctx; 751 struct cpuinfo_ia64 *cpu_info; 752 void *cpu_data; 753 754 cpu_data = per_cpu_init(); 755 756 /* 757 * We set ar.k3 so that assembly code in MCA handler can compute 758 * physical addresses of per cpu variables with a simple: 759 * phys = ar.k3 + &per_cpu_var 760 */ 761 ia64_set_kr(IA64_KR_PER_CPU_DATA, 762 ia64_tpa(cpu_data) - (long) __per_cpu_start); 763 764 get_max_cacheline_size(); 765 766 /* 767 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 768 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 769 * depends on the data returned by identify_cpu(). We break the dependency by 770 * accessing cpu_data() through the canonical per-CPU address. 771 */ 772 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 773 identify_cpu(cpu_info); 774 775 #ifdef CONFIG_MCKINLEY 776 { 777 # define FEATURE_SET 16 778 struct ia64_pal_retval iprv; 779 780 if (cpu_info->family == 0x1f) { 781 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 782 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 783 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 784 (iprv.v1 | 0x80), FEATURE_SET, 0); 785 } 786 } 787 #endif 788 789 /* Clear the stack memory reserved for pt_regs: */ 790 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs)); 791 792 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 793 794 /* 795 * Initialize the page-table base register to a global 796 * directory with all zeroes. This ensure that we can handle 797 * TLB-misses to user address-space even before we created the 798 * first user address-space. This may happen, e.g., due to 799 * aggressive use of lfetch.fault. 800 */ 801 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 802 803 /* 804 * Initialize default control register to defer speculative faults except 805 * for those arising from TLB misses, which are not deferred. The 806 * kernel MUST NOT depend on a particular setting of these bits (in other words, 807 * the kernel must have recovery code for all speculative accesses). Turn on 808 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 809 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 810 * be fine). 811 */ 812 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 813 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 814 atomic_inc(&init_mm.mm_count); 815 current->active_mm = &init_mm; 816 if (current->mm) 817 BUG(); 818 819 ia64_mmu_init(ia64_imva(cpu_data)); 820 ia64_mca_cpu_init(ia64_imva(cpu_data)); 821 822 #ifdef CONFIG_IA32_SUPPORT 823 ia32_cpu_init(); 824 #endif 825 826 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 827 ia64_set_itc(0); 828 829 /* disable all local interrupt sources: */ 830 ia64_set_itv(1 << 16); 831 ia64_set_lrr0(1 << 16); 832 ia64_set_lrr1(1 << 16); 833 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 834 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 835 836 /* clear TPR & XTP to enable all interrupt classes: */ 837 ia64_setreg(_IA64_REG_CR_TPR, 0); 838 #ifdef CONFIG_SMP 839 normal_xtp(); 840 #endif 841 842 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 843 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 844 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 845 else { 846 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 847 max_ctx = (1U << 15) - 1; /* use architected minimum */ 848 } 849 while (max_ctx < ia64_ctx.max_ctx) { 850 unsigned int old = ia64_ctx.max_ctx; 851 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 852 break; 853 } 854 855 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 856 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 857 "stacked regs\n"); 858 num_phys_stacked = 96; 859 } 860 /* size of physical stacked register partition plus 8 bytes: */ 861 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 862 platform_cpu_init(); 863 pm_idle = default_idle; 864 } 865 866 void 867 check_bugs (void) 868 { 869 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 870 (unsigned long) __end___mckinley_e9_bundles); 871 } 872