1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/hpsim.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 75 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 76 unsigned long ia64_cycles_per_usec; 77 struct ia64_boot_param *ia64_boot_param; 78 struct screen_info screen_info; 79 unsigned long vga_console_iobase; 80 unsigned long vga_console_membase; 81 82 static struct resource data_resource = { 83 .name = "Kernel data", 84 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 85 }; 86 87 static struct resource code_resource = { 88 .name = "Kernel code", 89 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 90 }; 91 92 static struct resource bss_resource = { 93 .name = "Kernel bss", 94 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 95 }; 96 97 unsigned long ia64_max_cacheline_size; 98 99 int dma_get_cache_alignment(void) 100 { 101 return ia64_max_cacheline_size; 102 } 103 EXPORT_SYMBOL(dma_get_cache_alignment); 104 105 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 106 EXPORT_SYMBOL(ia64_iobase); 107 struct io_space io_space[MAX_IO_SPACES]; 108 EXPORT_SYMBOL(io_space); 109 unsigned int num_io_spaces; 110 111 /* 112 * "flush_icache_range()" needs to know what processor dependent stride size to use 113 * when it makes i-cache(s) coherent with d-caches. 114 */ 115 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 116 unsigned long ia64_i_cache_stride_shift = ~0; 117 118 /* 119 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 120 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 121 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 122 * address of the second buffer must be aligned to (merge_mask+1) in order to be 123 * mergeable). By default, we assume there is no I/O MMU which can merge physically 124 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 125 * page-size of 2^64. 126 */ 127 unsigned long ia64_max_iommu_merge_mask = ~0UL; 128 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 129 130 /* 131 * We use a special marker for the end of memory and it uses the extra (+1) slot 132 */ 133 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 134 int num_rsvd_regions __initdata; 135 136 137 /* 138 * Filter incoming memory segments based on the primitive map created from the boot 139 * parameters. Segments contained in the map are removed from the memory ranges. A 140 * caller-specified function is called with the memory ranges that remain after filtering. 141 * This routine does not assume the incoming segments are sorted. 142 */ 143 int __init 144 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 145 { 146 unsigned long range_start, range_end, prev_start; 147 void (*func)(unsigned long, unsigned long, int); 148 int i; 149 150 #if IGNORE_PFN0 151 if (start == PAGE_OFFSET) { 152 printk(KERN_WARNING "warning: skipping physical page 0\n"); 153 start += PAGE_SIZE; 154 if (start >= end) return 0; 155 } 156 #endif 157 /* 158 * lowest possible address(walker uses virtual) 159 */ 160 prev_start = PAGE_OFFSET; 161 func = arg; 162 163 for (i = 0; i < num_rsvd_regions; ++i) { 164 range_start = max(start, prev_start); 165 range_end = min(end, rsvd_region[i].start); 166 167 if (range_start < range_end) 168 call_pernode_memory(__pa(range_start), range_end - range_start, func); 169 170 /* nothing more available in this segment */ 171 if (range_end == end) return 0; 172 173 prev_start = rsvd_region[i].end; 174 } 175 /* end of memory marker allows full processing inside loop body */ 176 return 0; 177 } 178 179 static void __init 180 sort_regions (struct rsvd_region *rsvd_region, int max) 181 { 182 int j; 183 184 /* simple bubble sorting */ 185 while (max--) { 186 for (j = 0; j < max; ++j) { 187 if (rsvd_region[j].start > rsvd_region[j+1].start) { 188 struct rsvd_region tmp; 189 tmp = rsvd_region[j]; 190 rsvd_region[j] = rsvd_region[j + 1]; 191 rsvd_region[j + 1] = tmp; 192 } 193 } 194 } 195 } 196 197 /* 198 * Request address space for all standard resources 199 */ 200 static int __init register_memory(void) 201 { 202 code_resource.start = ia64_tpa(_text); 203 code_resource.end = ia64_tpa(_etext) - 1; 204 data_resource.start = ia64_tpa(_etext); 205 data_resource.end = ia64_tpa(_edata) - 1; 206 bss_resource.start = ia64_tpa(__bss_start); 207 bss_resource.end = ia64_tpa(_end) - 1; 208 efi_initialize_iomem_resources(&code_resource, &data_resource, 209 &bss_resource); 210 211 return 0; 212 } 213 214 __initcall(register_memory); 215 216 217 #ifdef CONFIG_KEXEC 218 static void __init setup_crashkernel(unsigned long total, int *n) 219 { 220 unsigned long long base = 0, size = 0; 221 int ret; 222 223 ret = parse_crashkernel(boot_command_line, total, 224 &size, &base); 225 if (ret == 0 && size > 0) { 226 if (!base) { 227 sort_regions(rsvd_region, *n); 228 base = kdump_find_rsvd_region(size, 229 rsvd_region, *n); 230 } 231 if (base != ~0UL) { 232 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 233 "for crashkernel (System RAM: %ldMB)\n", 234 (unsigned long)(size >> 20), 235 (unsigned long)(base >> 20), 236 (unsigned long)(total >> 20)); 237 rsvd_region[*n].start = 238 (unsigned long)__va(base); 239 rsvd_region[*n].end = 240 (unsigned long)__va(base + size); 241 (*n)++; 242 crashk_res.start = base; 243 crashk_res.end = base + size - 1; 244 } 245 } 246 efi_memmap_res.start = ia64_boot_param->efi_memmap; 247 efi_memmap_res.end = efi_memmap_res.start + 248 ia64_boot_param->efi_memmap_size; 249 boot_param_res.start = __pa(ia64_boot_param); 250 boot_param_res.end = boot_param_res.start + 251 sizeof(*ia64_boot_param); 252 } 253 #else 254 static inline void __init setup_crashkernel(unsigned long total, int *n) 255 {} 256 #endif 257 258 /** 259 * reserve_memory - setup reserved memory areas 260 * 261 * Setup the reserved memory areas set aside for the boot parameters, 262 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 263 * see include/asm-ia64/meminit.h if you need to define more. 264 */ 265 void __init 266 reserve_memory (void) 267 { 268 int n = 0; 269 unsigned long total_memory; 270 271 /* 272 * none of the entries in this table overlap 273 */ 274 rsvd_region[n].start = (unsigned long) ia64_boot_param; 275 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 276 n++; 277 278 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 279 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 280 n++; 281 282 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 283 rsvd_region[n].end = (rsvd_region[n].start 284 + strlen(__va(ia64_boot_param->command_line)) + 1); 285 n++; 286 287 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 288 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 289 n++; 290 291 #ifdef CONFIG_BLK_DEV_INITRD 292 if (ia64_boot_param->initrd_start) { 293 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 294 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 295 n++; 296 } 297 #endif 298 299 #ifdef CONFIG_PROC_VMCORE 300 if (reserve_elfcorehdr(&rsvd_region[n].start, 301 &rsvd_region[n].end) == 0) 302 n++; 303 #endif 304 305 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 306 n++; 307 308 setup_crashkernel(total_memory, &n); 309 310 /* end of memory marker */ 311 rsvd_region[n].start = ~0UL; 312 rsvd_region[n].end = ~0UL; 313 n++; 314 315 num_rsvd_regions = n; 316 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 317 318 sort_regions(rsvd_region, num_rsvd_regions); 319 } 320 321 322 /** 323 * find_initrd - get initrd parameters from the boot parameter structure 324 * 325 * Grab the initrd start and end from the boot parameter struct given us by 326 * the boot loader. 327 */ 328 void __init 329 find_initrd (void) 330 { 331 #ifdef CONFIG_BLK_DEV_INITRD 332 if (ia64_boot_param->initrd_start) { 333 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 334 initrd_end = initrd_start+ia64_boot_param->initrd_size; 335 336 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 337 initrd_start, ia64_boot_param->initrd_size); 338 } 339 #endif 340 } 341 342 static void __init 343 io_port_init (void) 344 { 345 unsigned long phys_iobase; 346 347 /* 348 * Set `iobase' based on the EFI memory map or, failing that, the 349 * value firmware left in ar.k0. 350 * 351 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 352 * the port's virtual address, so ia32_load_state() loads it with a 353 * user virtual address. But in ia64 mode, glibc uses the 354 * *physical* address in ar.k0 to mmap the appropriate area from 355 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 356 * cases, user-mode can only use the legacy 0-64K I/O port space. 357 * 358 * ar.k0 is not involved in kernel I/O port accesses, which can use 359 * any of the I/O port spaces and are done via MMIO using the 360 * virtual mmio_base from the appropriate io_space[]. 361 */ 362 phys_iobase = efi_get_iobase(); 363 if (!phys_iobase) { 364 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 365 printk(KERN_INFO "No I/O port range found in EFI memory map, " 366 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 367 } 368 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 369 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 370 371 /* setup legacy IO port space */ 372 io_space[0].mmio_base = ia64_iobase; 373 io_space[0].sparse = 1; 374 num_io_spaces = 1; 375 } 376 377 /** 378 * early_console_setup - setup debugging console 379 * 380 * Consoles started here require little enough setup that we can start using 381 * them very early in the boot process, either right after the machine 382 * vector initialization, or even before if the drivers can detect their hw. 383 * 384 * Returns non-zero if a console couldn't be setup. 385 */ 386 static inline int __init 387 early_console_setup (char *cmdline) 388 { 389 int earlycons = 0; 390 391 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 392 { 393 extern int sn_serial_console_early_setup(void); 394 if (!sn_serial_console_early_setup()) 395 earlycons++; 396 } 397 #endif 398 #ifdef CONFIG_EFI_PCDP 399 if (!efi_setup_pcdp_console(cmdline)) 400 earlycons++; 401 #endif 402 if (!simcons_register()) 403 earlycons++; 404 405 return (earlycons) ? 0 : -1; 406 } 407 408 static inline void 409 mark_bsp_online (void) 410 { 411 #ifdef CONFIG_SMP 412 /* If we register an early console, allow CPU 0 to printk */ 413 cpu_set(smp_processor_id(), cpu_online_map); 414 #endif 415 } 416 417 static __initdata int nomca; 418 static __init int setup_nomca(char *s) 419 { 420 nomca = 1; 421 return 0; 422 } 423 early_param("nomca", setup_nomca); 424 425 #ifdef CONFIG_PROC_VMCORE 426 /* elfcorehdr= specifies the location of elf core header 427 * stored by the crashed kernel. 428 */ 429 static int __init parse_elfcorehdr(char *arg) 430 { 431 if (!arg) 432 return -EINVAL; 433 434 elfcorehdr_addr = memparse(arg, &arg); 435 return 0; 436 } 437 early_param("elfcorehdr", parse_elfcorehdr); 438 439 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 440 { 441 unsigned long length; 442 443 /* We get the address using the kernel command line, 444 * but the size is extracted from the EFI tables. 445 * Both address and size are required for reservation 446 * to work properly. 447 */ 448 449 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) 450 return -EINVAL; 451 452 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 453 elfcorehdr_addr = ELFCORE_ADDR_MAX; 454 return -EINVAL; 455 } 456 457 *start = (unsigned long)__va(elfcorehdr_addr); 458 *end = *start + length; 459 return 0; 460 } 461 462 #endif /* CONFIG_PROC_VMCORE */ 463 464 void __init 465 setup_arch (char **cmdline_p) 466 { 467 unw_init(); 468 469 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 470 471 *cmdline_p = __va(ia64_boot_param->command_line); 472 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 473 474 efi_init(); 475 io_port_init(); 476 477 #ifdef CONFIG_IA64_GENERIC 478 /* machvec needs to be parsed from the command line 479 * before parse_early_param() is called to ensure 480 * that ia64_mv is initialised before any command line 481 * settings may cause console setup to occur 482 */ 483 machvec_init_from_cmdline(*cmdline_p); 484 #endif 485 486 parse_early_param(); 487 488 if (early_console_setup(*cmdline_p) == 0) 489 mark_bsp_online(); 490 491 #ifdef CONFIG_ACPI 492 /* Initialize the ACPI boot-time table parser */ 493 acpi_table_init(); 494 # ifdef CONFIG_ACPI_NUMA 495 acpi_numa_init(); 496 # endif 497 #else 498 # ifdef CONFIG_SMP 499 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 500 # endif 501 #endif /* CONFIG_APCI_BOOT */ 502 503 find_memory(); 504 505 /* process SAL system table: */ 506 ia64_sal_init(__va(efi.sal_systab)); 507 508 #ifdef CONFIG_SMP 509 cpu_physical_id(0) = hard_smp_processor_id(); 510 #endif 511 512 cpu_init(); /* initialize the bootstrap CPU */ 513 mmu_context_init(); /* initialize context_id bitmap */ 514 515 check_sal_cache_flush(); 516 517 #ifdef CONFIG_ACPI 518 acpi_boot_init(); 519 #endif 520 521 #ifdef CONFIG_VT 522 if (!conswitchp) { 523 # if defined(CONFIG_DUMMY_CONSOLE) 524 conswitchp = &dummy_con; 525 # endif 526 # if defined(CONFIG_VGA_CONSOLE) 527 /* 528 * Non-legacy systems may route legacy VGA MMIO range to system 529 * memory. vga_con probes the MMIO hole, so memory looks like 530 * a VGA device to it. The EFI memory map can tell us if it's 531 * memory so we can avoid this problem. 532 */ 533 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 534 conswitchp = &vga_con; 535 # endif 536 } 537 #endif 538 539 /* enable IA-64 Machine Check Abort Handling unless disabled */ 540 if (!nomca) 541 ia64_mca_init(); 542 543 platform_setup(cmdline_p); 544 paging_init(); 545 } 546 547 /* 548 * Display cpu info for all CPUs. 549 */ 550 static int 551 show_cpuinfo (struct seq_file *m, void *v) 552 { 553 #ifdef CONFIG_SMP 554 # define lpj c->loops_per_jiffy 555 # define cpunum c->cpu 556 #else 557 # define lpj loops_per_jiffy 558 # define cpunum 0 559 #endif 560 static struct { 561 unsigned long mask; 562 const char *feature_name; 563 } feature_bits[] = { 564 { 1UL << 0, "branchlong" }, 565 { 1UL << 1, "spontaneous deferral"}, 566 { 1UL << 2, "16-byte atomic ops" } 567 }; 568 char features[128], *cp, *sep; 569 struct cpuinfo_ia64 *c = v; 570 unsigned long mask; 571 unsigned long proc_freq; 572 int i, size; 573 574 mask = c->features; 575 576 /* build the feature string: */ 577 memcpy(features, "standard", 9); 578 cp = features; 579 size = sizeof(features); 580 sep = ""; 581 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 582 if (mask & feature_bits[i].mask) { 583 cp += snprintf(cp, size, "%s%s", sep, 584 feature_bits[i].feature_name), 585 sep = ", "; 586 mask &= ~feature_bits[i].mask; 587 size = sizeof(features) - (cp - features); 588 } 589 } 590 if (mask && size > 1) { 591 /* print unknown features as a hex value */ 592 snprintf(cp, size, "%s0x%lx", sep, mask); 593 } 594 595 proc_freq = cpufreq_quick_get(cpunum); 596 if (!proc_freq) 597 proc_freq = c->proc_freq / 1000; 598 599 seq_printf(m, 600 "processor : %d\n" 601 "vendor : %s\n" 602 "arch : IA-64\n" 603 "family : %u\n" 604 "model : %u\n" 605 "model name : %s\n" 606 "revision : %u\n" 607 "archrev : %u\n" 608 "features : %s\n" 609 "cpu number : %lu\n" 610 "cpu regs : %u\n" 611 "cpu MHz : %lu.%03lu\n" 612 "itc MHz : %lu.%06lu\n" 613 "BogoMIPS : %lu.%02lu\n", 614 cpunum, c->vendor, c->family, c->model, 615 c->model_name, c->revision, c->archrev, 616 features, c->ppn, c->number, 617 proc_freq / 1000, proc_freq % 1000, 618 c->itc_freq / 1000000, c->itc_freq % 1000000, 619 lpj*HZ/500000, (lpj*HZ/5000) % 100); 620 #ifdef CONFIG_SMP 621 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 622 if (c->socket_id != -1) 623 seq_printf(m, "physical id: %u\n", c->socket_id); 624 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 625 seq_printf(m, 626 "core id : %u\n" 627 "thread id : %u\n", 628 c->core_id, c->thread_id); 629 #endif 630 seq_printf(m,"\n"); 631 632 return 0; 633 } 634 635 static void * 636 c_start (struct seq_file *m, loff_t *pos) 637 { 638 #ifdef CONFIG_SMP 639 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 640 ++*pos; 641 #endif 642 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 643 } 644 645 static void * 646 c_next (struct seq_file *m, void *v, loff_t *pos) 647 { 648 ++*pos; 649 return c_start(m, pos); 650 } 651 652 static void 653 c_stop (struct seq_file *m, void *v) 654 { 655 } 656 657 const struct seq_operations cpuinfo_op = { 658 .start = c_start, 659 .next = c_next, 660 .stop = c_stop, 661 .show = show_cpuinfo 662 }; 663 664 #define MAX_BRANDS 8 665 static char brandname[MAX_BRANDS][128]; 666 667 static char * __cpuinit 668 get_model_name(__u8 family, __u8 model) 669 { 670 static int overflow; 671 char brand[128]; 672 int i; 673 674 memcpy(brand, "Unknown", 8); 675 if (ia64_pal_get_brand_info(brand)) { 676 if (family == 0x7) 677 memcpy(brand, "Merced", 7); 678 else if (family == 0x1f) switch (model) { 679 case 0: memcpy(brand, "McKinley", 9); break; 680 case 1: memcpy(brand, "Madison", 8); break; 681 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 682 } 683 } 684 for (i = 0; i < MAX_BRANDS; i++) 685 if (strcmp(brandname[i], brand) == 0) 686 return brandname[i]; 687 for (i = 0; i < MAX_BRANDS; i++) 688 if (brandname[i][0] == '\0') 689 return strcpy(brandname[i], brand); 690 if (overflow++ == 0) 691 printk(KERN_ERR 692 "%s: Table overflow. Some processor model information will be missing\n", 693 __func__); 694 return "Unknown"; 695 } 696 697 static void __cpuinit 698 identify_cpu (struct cpuinfo_ia64 *c) 699 { 700 union { 701 unsigned long bits[5]; 702 struct { 703 /* id 0 & 1: */ 704 char vendor[16]; 705 706 /* id 2 */ 707 u64 ppn; /* processor serial number */ 708 709 /* id 3: */ 710 unsigned number : 8; 711 unsigned revision : 8; 712 unsigned model : 8; 713 unsigned family : 8; 714 unsigned archrev : 8; 715 unsigned reserved : 24; 716 717 /* id 4: */ 718 u64 features; 719 } field; 720 } cpuid; 721 pal_vm_info_1_u_t vm1; 722 pal_vm_info_2_u_t vm2; 723 pal_status_t status; 724 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 725 int i; 726 for (i = 0; i < 5; ++i) 727 cpuid.bits[i] = ia64_get_cpuid(i); 728 729 memcpy(c->vendor, cpuid.field.vendor, 16); 730 #ifdef CONFIG_SMP 731 c->cpu = smp_processor_id(); 732 733 /* below default values will be overwritten by identify_siblings() 734 * for Multi-Threading/Multi-Core capable CPUs 735 */ 736 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 737 c->socket_id = -1; 738 739 identify_siblings(c); 740 741 if (c->threads_per_core > smp_num_siblings) 742 smp_num_siblings = c->threads_per_core; 743 #endif 744 c->ppn = cpuid.field.ppn; 745 c->number = cpuid.field.number; 746 c->revision = cpuid.field.revision; 747 c->model = cpuid.field.model; 748 c->family = cpuid.field.family; 749 c->archrev = cpuid.field.archrev; 750 c->features = cpuid.field.features; 751 c->model_name = get_model_name(c->family, c->model); 752 753 status = ia64_pal_vm_summary(&vm1, &vm2); 754 if (status == PAL_STATUS_SUCCESS) { 755 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 756 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 757 } 758 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 759 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 760 } 761 762 void __init 763 setup_per_cpu_areas (void) 764 { 765 /* start_kernel() requires this... */ 766 #ifdef CONFIG_ACPI_HOTPLUG_CPU 767 prefill_possible_map(); 768 #endif 769 } 770 771 /* 772 * Calculate the max. cache line size. 773 * 774 * In addition, the minimum of the i-cache stride sizes is calculated for 775 * "flush_icache_range()". 776 */ 777 static void __cpuinit 778 get_max_cacheline_size (void) 779 { 780 unsigned long line_size, max = 1; 781 u64 l, levels, unique_caches; 782 pal_cache_config_info_t cci; 783 s64 status; 784 785 status = ia64_pal_cache_summary(&levels, &unique_caches); 786 if (status != 0) { 787 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 788 __func__, status); 789 max = SMP_CACHE_BYTES; 790 /* Safest setup for "flush_icache_range()" */ 791 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 792 goto out; 793 } 794 795 for (l = 0; l < levels; ++l) { 796 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 797 &cci); 798 if (status != 0) { 799 printk(KERN_ERR 800 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 801 __func__, l, status); 802 max = SMP_CACHE_BYTES; 803 /* The safest setup for "flush_icache_range()" */ 804 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 805 cci.pcci_unified = 1; 806 } 807 line_size = 1 << cci.pcci_line_size; 808 if (line_size > max) 809 max = line_size; 810 if (!cci.pcci_unified) { 811 status = ia64_pal_cache_config_info(l, 812 /* cache_type (instruction)= */ 1, 813 &cci); 814 if (status != 0) { 815 printk(KERN_ERR 816 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 817 __func__, l, status); 818 /* The safest setup for "flush_icache_range()" */ 819 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 820 } 821 } 822 if (cci.pcci_stride < ia64_i_cache_stride_shift) 823 ia64_i_cache_stride_shift = cci.pcci_stride; 824 } 825 out: 826 if (max > ia64_max_cacheline_size) 827 ia64_max_cacheline_size = max; 828 } 829 830 /* 831 * cpu_init() initializes state that is per-CPU. This function acts 832 * as a 'CPU state barrier', nothing should get across. 833 */ 834 void __cpuinit 835 cpu_init (void) 836 { 837 extern void __cpuinit ia64_mmu_init (void *); 838 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 839 unsigned long num_phys_stacked; 840 pal_vm_info_2_u_t vmi; 841 unsigned int max_ctx; 842 struct cpuinfo_ia64 *cpu_info; 843 void *cpu_data; 844 845 cpu_data = per_cpu_init(); 846 #ifdef CONFIG_SMP 847 /* 848 * insert boot cpu into sibling and core mapes 849 * (must be done after per_cpu area is setup) 850 */ 851 if (smp_processor_id() == 0) { 852 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 853 cpu_set(0, cpu_core_map[0]); 854 } 855 #endif 856 857 /* 858 * We set ar.k3 so that assembly code in MCA handler can compute 859 * physical addresses of per cpu variables with a simple: 860 * phys = ar.k3 + &per_cpu_var 861 */ 862 ia64_set_kr(IA64_KR_PER_CPU_DATA, 863 ia64_tpa(cpu_data) - (long) __per_cpu_start); 864 865 get_max_cacheline_size(); 866 867 /* 868 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 869 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 870 * depends on the data returned by identify_cpu(). We break the dependency by 871 * accessing cpu_data() through the canonical per-CPU address. 872 */ 873 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 874 identify_cpu(cpu_info); 875 876 #ifdef CONFIG_MCKINLEY 877 { 878 # define FEATURE_SET 16 879 struct ia64_pal_retval iprv; 880 881 if (cpu_info->family == 0x1f) { 882 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 883 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 884 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 885 (iprv.v1 | 0x80), FEATURE_SET, 0); 886 } 887 } 888 #endif 889 890 /* Clear the stack memory reserved for pt_regs: */ 891 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 892 893 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 894 895 /* 896 * Initialize the page-table base register to a global 897 * directory with all zeroes. This ensure that we can handle 898 * TLB-misses to user address-space even before we created the 899 * first user address-space. This may happen, e.g., due to 900 * aggressive use of lfetch.fault. 901 */ 902 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 903 904 /* 905 * Initialize default control register to defer speculative faults except 906 * for those arising from TLB misses, which are not deferred. The 907 * kernel MUST NOT depend on a particular setting of these bits (in other words, 908 * the kernel must have recovery code for all speculative accesses). Turn on 909 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 910 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 911 * be fine). 912 */ 913 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 914 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 915 atomic_inc(&init_mm.mm_count); 916 current->active_mm = &init_mm; 917 if (current->mm) 918 BUG(); 919 920 ia64_mmu_init(ia64_imva(cpu_data)); 921 ia64_mca_cpu_init(ia64_imva(cpu_data)); 922 923 #ifdef CONFIG_IA32_SUPPORT 924 ia32_cpu_init(); 925 #endif 926 927 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 928 ia64_set_itc(0); 929 930 /* disable all local interrupt sources: */ 931 ia64_set_itv(1 << 16); 932 ia64_set_lrr0(1 << 16); 933 ia64_set_lrr1(1 << 16); 934 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 935 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 936 937 /* clear TPR & XTP to enable all interrupt classes: */ 938 ia64_setreg(_IA64_REG_CR_TPR, 0); 939 940 /* Clear any pending interrupts left by SAL/EFI */ 941 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 942 ia64_eoi(); 943 944 #ifdef CONFIG_SMP 945 normal_xtp(); 946 #endif 947 948 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 949 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 950 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 951 else { 952 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 953 max_ctx = (1U << 15) - 1; /* use architected minimum */ 954 } 955 while (max_ctx < ia64_ctx.max_ctx) { 956 unsigned int old = ia64_ctx.max_ctx; 957 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 958 break; 959 } 960 961 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 962 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 963 "stacked regs\n"); 964 num_phys_stacked = 96; 965 } 966 /* size of physical stacked register partition plus 8 bytes: */ 967 if (num_phys_stacked > max_num_phys_stacked) { 968 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 969 max_num_phys_stacked = num_phys_stacked; 970 } 971 platform_cpu_init(); 972 pm_idle = default_idle; 973 } 974 975 void __init 976 check_bugs (void) 977 { 978 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 979 (unsigned long) __end___mckinley_e9_bundles); 980 } 981 982 static int __init run_dmi_scan(void) 983 { 984 dmi_scan_machine(); 985 return 0; 986 } 987 core_initcall(run_dmi_scan); 988