1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/hpsim.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 extern void ia64_setup_printk_clock(void); 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 94 static struct resource bss_resource = { 95 .name = "Kernel bss", 96 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 97 }; 98 99 unsigned long ia64_max_cacheline_size; 100 101 int dma_get_cache_alignment(void) 102 { 103 return ia64_max_cacheline_size; 104 } 105 EXPORT_SYMBOL(dma_get_cache_alignment); 106 107 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 108 EXPORT_SYMBOL(ia64_iobase); 109 struct io_space io_space[MAX_IO_SPACES]; 110 EXPORT_SYMBOL(io_space); 111 unsigned int num_io_spaces; 112 113 /* 114 * "flush_icache_range()" needs to know what processor dependent stride size to use 115 * when it makes i-cache(s) coherent with d-caches. 116 */ 117 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 118 unsigned long ia64_i_cache_stride_shift = ~0; 119 120 /* 121 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 122 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 123 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 124 * address of the second buffer must be aligned to (merge_mask+1) in order to be 125 * mergeable). By default, we assume there is no I/O MMU which can merge physically 126 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 127 * page-size of 2^64. 128 */ 129 unsigned long ia64_max_iommu_merge_mask = ~0UL; 130 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 131 132 /* 133 * We use a special marker for the end of memory and it uses the extra (+1) slot 134 */ 135 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 136 int num_rsvd_regions __initdata; 137 138 139 /* 140 * Filter incoming memory segments based on the primitive map created from the boot 141 * parameters. Segments contained in the map are removed from the memory ranges. A 142 * caller-specified function is called with the memory ranges that remain after filtering. 143 * This routine does not assume the incoming segments are sorted. 144 */ 145 int __init 146 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 147 { 148 unsigned long range_start, range_end, prev_start; 149 void (*func)(unsigned long, unsigned long, int); 150 int i; 151 152 #if IGNORE_PFN0 153 if (start == PAGE_OFFSET) { 154 printk(KERN_WARNING "warning: skipping physical page 0\n"); 155 start += PAGE_SIZE; 156 if (start >= end) return 0; 157 } 158 #endif 159 /* 160 * lowest possible address(walker uses virtual) 161 */ 162 prev_start = PAGE_OFFSET; 163 func = arg; 164 165 for (i = 0; i < num_rsvd_regions; ++i) { 166 range_start = max(start, prev_start); 167 range_end = min(end, rsvd_region[i].start); 168 169 if (range_start < range_end) 170 call_pernode_memory(__pa(range_start), range_end - range_start, func); 171 172 /* nothing more available in this segment */ 173 if (range_end == end) return 0; 174 175 prev_start = rsvd_region[i].end; 176 } 177 /* end of memory marker allows full processing inside loop body */ 178 return 0; 179 } 180 181 static void __init 182 sort_regions (struct rsvd_region *rsvd_region, int max) 183 { 184 int j; 185 186 /* simple bubble sorting */ 187 while (max--) { 188 for (j = 0; j < max; ++j) { 189 if (rsvd_region[j].start > rsvd_region[j+1].start) { 190 struct rsvd_region tmp; 191 tmp = rsvd_region[j]; 192 rsvd_region[j] = rsvd_region[j + 1]; 193 rsvd_region[j + 1] = tmp; 194 } 195 } 196 } 197 } 198 199 /* 200 * Request address space for all standard resources 201 */ 202 static int __init register_memory(void) 203 { 204 code_resource.start = ia64_tpa(_text); 205 code_resource.end = ia64_tpa(_etext) - 1; 206 data_resource.start = ia64_tpa(_etext); 207 data_resource.end = ia64_tpa(_edata) - 1; 208 bss_resource.start = ia64_tpa(__bss_start); 209 bss_resource.end = ia64_tpa(_end) - 1; 210 efi_initialize_iomem_resources(&code_resource, &data_resource, 211 &bss_resource); 212 213 return 0; 214 } 215 216 __initcall(register_memory); 217 218 219 #ifdef CONFIG_KEXEC 220 static void __init setup_crashkernel(unsigned long total, int *n) 221 { 222 unsigned long long base = 0, size = 0; 223 int ret; 224 225 ret = parse_crashkernel(boot_command_line, total, 226 &size, &base); 227 if (ret == 0 && size > 0) { 228 if (!base) { 229 sort_regions(rsvd_region, *n); 230 base = kdump_find_rsvd_region(size, 231 rsvd_region, *n); 232 } 233 if (base != ~0UL) { 234 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 235 "for crashkernel (System RAM: %ldMB)\n", 236 (unsigned long)(size >> 20), 237 (unsigned long)(base >> 20), 238 (unsigned long)(total >> 20)); 239 rsvd_region[*n].start = 240 (unsigned long)__va(base); 241 rsvd_region[*n].end = 242 (unsigned long)__va(base + size); 243 (*n)++; 244 crashk_res.start = base; 245 crashk_res.end = base + size - 1; 246 } 247 } 248 efi_memmap_res.start = ia64_boot_param->efi_memmap; 249 efi_memmap_res.end = efi_memmap_res.start + 250 ia64_boot_param->efi_memmap_size; 251 boot_param_res.start = __pa(ia64_boot_param); 252 boot_param_res.end = boot_param_res.start + 253 sizeof(*ia64_boot_param); 254 } 255 #else 256 static inline void __init setup_crashkernel(unsigned long total, int *n) 257 {} 258 #endif 259 260 /** 261 * reserve_memory - setup reserved memory areas 262 * 263 * Setup the reserved memory areas set aside for the boot parameters, 264 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 265 * see include/asm-ia64/meminit.h if you need to define more. 266 */ 267 void __init 268 reserve_memory (void) 269 { 270 int n = 0; 271 unsigned long total_memory; 272 273 /* 274 * none of the entries in this table overlap 275 */ 276 rsvd_region[n].start = (unsigned long) ia64_boot_param; 277 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 278 n++; 279 280 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 281 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 282 n++; 283 284 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 285 rsvd_region[n].end = (rsvd_region[n].start 286 + strlen(__va(ia64_boot_param->command_line)) + 1); 287 n++; 288 289 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 290 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 291 n++; 292 293 #ifdef CONFIG_BLK_DEV_INITRD 294 if (ia64_boot_param->initrd_start) { 295 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 296 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 297 n++; 298 } 299 #endif 300 301 #ifdef CONFIG_PROC_VMCORE 302 if (reserve_elfcorehdr(&rsvd_region[n].start, 303 &rsvd_region[n].end) == 0) 304 n++; 305 #endif 306 307 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 308 n++; 309 310 setup_crashkernel(total_memory, &n); 311 312 /* end of memory marker */ 313 rsvd_region[n].start = ~0UL; 314 rsvd_region[n].end = ~0UL; 315 n++; 316 317 num_rsvd_regions = n; 318 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 319 320 sort_regions(rsvd_region, num_rsvd_regions); 321 } 322 323 324 /** 325 * find_initrd - get initrd parameters from the boot parameter structure 326 * 327 * Grab the initrd start and end from the boot parameter struct given us by 328 * the boot loader. 329 */ 330 void __init 331 find_initrd (void) 332 { 333 #ifdef CONFIG_BLK_DEV_INITRD 334 if (ia64_boot_param->initrd_start) { 335 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 336 initrd_end = initrd_start+ia64_boot_param->initrd_size; 337 338 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 339 initrd_start, ia64_boot_param->initrd_size); 340 } 341 #endif 342 } 343 344 static void __init 345 io_port_init (void) 346 { 347 unsigned long phys_iobase; 348 349 /* 350 * Set `iobase' based on the EFI memory map or, failing that, the 351 * value firmware left in ar.k0. 352 * 353 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 354 * the port's virtual address, so ia32_load_state() loads it with a 355 * user virtual address. But in ia64 mode, glibc uses the 356 * *physical* address in ar.k0 to mmap the appropriate area from 357 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 358 * cases, user-mode can only use the legacy 0-64K I/O port space. 359 * 360 * ar.k0 is not involved in kernel I/O port accesses, which can use 361 * any of the I/O port spaces and are done via MMIO using the 362 * virtual mmio_base from the appropriate io_space[]. 363 */ 364 phys_iobase = efi_get_iobase(); 365 if (!phys_iobase) { 366 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 367 printk(KERN_INFO "No I/O port range found in EFI memory map, " 368 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 369 } 370 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 371 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 372 373 /* setup legacy IO port space */ 374 io_space[0].mmio_base = ia64_iobase; 375 io_space[0].sparse = 1; 376 num_io_spaces = 1; 377 } 378 379 /** 380 * early_console_setup - setup debugging console 381 * 382 * Consoles started here require little enough setup that we can start using 383 * them very early in the boot process, either right after the machine 384 * vector initialization, or even before if the drivers can detect their hw. 385 * 386 * Returns non-zero if a console couldn't be setup. 387 */ 388 static inline int __init 389 early_console_setup (char *cmdline) 390 { 391 int earlycons = 0; 392 393 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 394 { 395 extern int sn_serial_console_early_setup(void); 396 if (!sn_serial_console_early_setup()) 397 earlycons++; 398 } 399 #endif 400 #ifdef CONFIG_EFI_PCDP 401 if (!efi_setup_pcdp_console(cmdline)) 402 earlycons++; 403 #endif 404 if (!simcons_register()) 405 earlycons++; 406 407 return (earlycons) ? 0 : -1; 408 } 409 410 static inline void 411 mark_bsp_online (void) 412 { 413 #ifdef CONFIG_SMP 414 /* If we register an early console, allow CPU 0 to printk */ 415 cpu_set(smp_processor_id(), cpu_online_map); 416 #endif 417 } 418 419 static __initdata int nomca; 420 static __init int setup_nomca(char *s) 421 { 422 nomca = 1; 423 return 0; 424 } 425 early_param("nomca", setup_nomca); 426 427 #ifdef CONFIG_PROC_VMCORE 428 /* elfcorehdr= specifies the location of elf core header 429 * stored by the crashed kernel. 430 */ 431 static int __init parse_elfcorehdr(char *arg) 432 { 433 if (!arg) 434 return -EINVAL; 435 436 elfcorehdr_addr = memparse(arg, &arg); 437 return 0; 438 } 439 early_param("elfcorehdr", parse_elfcorehdr); 440 441 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 442 { 443 unsigned long length; 444 445 /* We get the address using the kernel command line, 446 * but the size is extracted from the EFI tables. 447 * Both address and size are required for reservation 448 * to work properly. 449 */ 450 451 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) 452 return -EINVAL; 453 454 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 455 elfcorehdr_addr = ELFCORE_ADDR_MAX; 456 return -EINVAL; 457 } 458 459 *start = (unsigned long)__va(elfcorehdr_addr); 460 *end = *start + length; 461 return 0; 462 } 463 464 #endif /* CONFIG_PROC_VMCORE */ 465 466 void __init 467 setup_arch (char **cmdline_p) 468 { 469 unw_init(); 470 471 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 472 473 *cmdline_p = __va(ia64_boot_param->command_line); 474 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 475 476 efi_init(); 477 io_port_init(); 478 479 #ifdef CONFIG_IA64_GENERIC 480 /* machvec needs to be parsed from the command line 481 * before parse_early_param() is called to ensure 482 * that ia64_mv is initialised before any command line 483 * settings may cause console setup to occur 484 */ 485 machvec_init_from_cmdline(*cmdline_p); 486 #endif 487 488 parse_early_param(); 489 490 if (early_console_setup(*cmdline_p) == 0) 491 mark_bsp_online(); 492 493 #ifdef CONFIG_ACPI 494 /* Initialize the ACPI boot-time table parser */ 495 acpi_table_init(); 496 # ifdef CONFIG_ACPI_NUMA 497 acpi_numa_init(); 498 # endif 499 #else 500 # ifdef CONFIG_SMP 501 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 502 # endif 503 #endif /* CONFIG_APCI_BOOT */ 504 505 find_memory(); 506 507 /* process SAL system table: */ 508 ia64_sal_init(__va(efi.sal_systab)); 509 510 ia64_setup_printk_clock(); 511 512 #ifdef CONFIG_SMP 513 cpu_physical_id(0) = hard_smp_processor_id(); 514 #endif 515 516 cpu_init(); /* initialize the bootstrap CPU */ 517 mmu_context_init(); /* initialize context_id bitmap */ 518 519 check_sal_cache_flush(); 520 521 #ifdef CONFIG_ACPI 522 acpi_boot_init(); 523 #endif 524 525 #ifdef CONFIG_VT 526 if (!conswitchp) { 527 # if defined(CONFIG_DUMMY_CONSOLE) 528 conswitchp = &dummy_con; 529 # endif 530 # if defined(CONFIG_VGA_CONSOLE) 531 /* 532 * Non-legacy systems may route legacy VGA MMIO range to system 533 * memory. vga_con probes the MMIO hole, so memory looks like 534 * a VGA device to it. The EFI memory map can tell us if it's 535 * memory so we can avoid this problem. 536 */ 537 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 538 conswitchp = &vga_con; 539 # endif 540 } 541 #endif 542 543 /* enable IA-64 Machine Check Abort Handling unless disabled */ 544 if (!nomca) 545 ia64_mca_init(); 546 547 platform_setup(cmdline_p); 548 paging_init(); 549 } 550 551 /* 552 * Display cpu info for all CPUs. 553 */ 554 static int 555 show_cpuinfo (struct seq_file *m, void *v) 556 { 557 #ifdef CONFIG_SMP 558 # define lpj c->loops_per_jiffy 559 # define cpunum c->cpu 560 #else 561 # define lpj loops_per_jiffy 562 # define cpunum 0 563 #endif 564 static struct { 565 unsigned long mask; 566 const char *feature_name; 567 } feature_bits[] = { 568 { 1UL << 0, "branchlong" }, 569 { 1UL << 1, "spontaneous deferral"}, 570 { 1UL << 2, "16-byte atomic ops" } 571 }; 572 char features[128], *cp, *sep; 573 struct cpuinfo_ia64 *c = v; 574 unsigned long mask; 575 unsigned long proc_freq; 576 int i, size; 577 578 mask = c->features; 579 580 /* build the feature string: */ 581 memcpy(features, "standard", 9); 582 cp = features; 583 size = sizeof(features); 584 sep = ""; 585 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 586 if (mask & feature_bits[i].mask) { 587 cp += snprintf(cp, size, "%s%s", sep, 588 feature_bits[i].feature_name), 589 sep = ", "; 590 mask &= ~feature_bits[i].mask; 591 size = sizeof(features) - (cp - features); 592 } 593 } 594 if (mask && size > 1) { 595 /* print unknown features as a hex value */ 596 snprintf(cp, size, "%s0x%lx", sep, mask); 597 } 598 599 proc_freq = cpufreq_quick_get(cpunum); 600 if (!proc_freq) 601 proc_freq = c->proc_freq / 1000; 602 603 seq_printf(m, 604 "processor : %d\n" 605 "vendor : %s\n" 606 "arch : IA-64\n" 607 "family : %u\n" 608 "model : %u\n" 609 "model name : %s\n" 610 "revision : %u\n" 611 "archrev : %u\n" 612 "features : %s\n" 613 "cpu number : %lu\n" 614 "cpu regs : %u\n" 615 "cpu MHz : %lu.%03lu\n" 616 "itc MHz : %lu.%06lu\n" 617 "BogoMIPS : %lu.%02lu\n", 618 cpunum, c->vendor, c->family, c->model, 619 c->model_name, c->revision, c->archrev, 620 features, c->ppn, c->number, 621 proc_freq / 1000, proc_freq % 1000, 622 c->itc_freq / 1000000, c->itc_freq % 1000000, 623 lpj*HZ/500000, (lpj*HZ/5000) % 100); 624 #ifdef CONFIG_SMP 625 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 626 if (c->socket_id != -1) 627 seq_printf(m, "physical id: %u\n", c->socket_id); 628 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 629 seq_printf(m, 630 "core id : %u\n" 631 "thread id : %u\n", 632 c->core_id, c->thread_id); 633 #endif 634 seq_printf(m,"\n"); 635 636 return 0; 637 } 638 639 static void * 640 c_start (struct seq_file *m, loff_t *pos) 641 { 642 #ifdef CONFIG_SMP 643 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 644 ++*pos; 645 #endif 646 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 647 } 648 649 static void * 650 c_next (struct seq_file *m, void *v, loff_t *pos) 651 { 652 ++*pos; 653 return c_start(m, pos); 654 } 655 656 static void 657 c_stop (struct seq_file *m, void *v) 658 { 659 } 660 661 struct seq_operations cpuinfo_op = { 662 .start = c_start, 663 .next = c_next, 664 .stop = c_stop, 665 .show = show_cpuinfo 666 }; 667 668 #define MAX_BRANDS 8 669 static char brandname[MAX_BRANDS][128]; 670 671 static char * __cpuinit 672 get_model_name(__u8 family, __u8 model) 673 { 674 static int overflow; 675 char brand[128]; 676 int i; 677 678 memcpy(brand, "Unknown", 8); 679 if (ia64_pal_get_brand_info(brand)) { 680 if (family == 0x7) 681 memcpy(brand, "Merced", 7); 682 else if (family == 0x1f) switch (model) { 683 case 0: memcpy(brand, "McKinley", 9); break; 684 case 1: memcpy(brand, "Madison", 8); break; 685 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 686 } 687 } 688 for (i = 0; i < MAX_BRANDS; i++) 689 if (strcmp(brandname[i], brand) == 0) 690 return brandname[i]; 691 for (i = 0; i < MAX_BRANDS; i++) 692 if (brandname[i][0] == '\0') 693 return strcpy(brandname[i], brand); 694 if (overflow++ == 0) 695 printk(KERN_ERR 696 "%s: Table overflow. Some processor model information will be missing\n", 697 __FUNCTION__); 698 return "Unknown"; 699 } 700 701 static void __cpuinit 702 identify_cpu (struct cpuinfo_ia64 *c) 703 { 704 union { 705 unsigned long bits[5]; 706 struct { 707 /* id 0 & 1: */ 708 char vendor[16]; 709 710 /* id 2 */ 711 u64 ppn; /* processor serial number */ 712 713 /* id 3: */ 714 unsigned number : 8; 715 unsigned revision : 8; 716 unsigned model : 8; 717 unsigned family : 8; 718 unsigned archrev : 8; 719 unsigned reserved : 24; 720 721 /* id 4: */ 722 u64 features; 723 } field; 724 } cpuid; 725 pal_vm_info_1_u_t vm1; 726 pal_vm_info_2_u_t vm2; 727 pal_status_t status; 728 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 729 int i; 730 for (i = 0; i < 5; ++i) 731 cpuid.bits[i] = ia64_get_cpuid(i); 732 733 memcpy(c->vendor, cpuid.field.vendor, 16); 734 #ifdef CONFIG_SMP 735 c->cpu = smp_processor_id(); 736 737 /* below default values will be overwritten by identify_siblings() 738 * for Multi-Threading/Multi-Core capable CPUs 739 */ 740 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 741 c->socket_id = -1; 742 743 identify_siblings(c); 744 745 if (c->threads_per_core > smp_num_siblings) 746 smp_num_siblings = c->threads_per_core; 747 #endif 748 c->ppn = cpuid.field.ppn; 749 c->number = cpuid.field.number; 750 c->revision = cpuid.field.revision; 751 c->model = cpuid.field.model; 752 c->family = cpuid.field.family; 753 c->archrev = cpuid.field.archrev; 754 c->features = cpuid.field.features; 755 c->model_name = get_model_name(c->family, c->model); 756 757 status = ia64_pal_vm_summary(&vm1, &vm2); 758 if (status == PAL_STATUS_SUCCESS) { 759 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 760 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 761 } 762 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 763 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 764 } 765 766 void __init 767 setup_per_cpu_areas (void) 768 { 769 /* start_kernel() requires this... */ 770 #ifdef CONFIG_ACPI_HOTPLUG_CPU 771 prefill_possible_map(); 772 #endif 773 } 774 775 /* 776 * Calculate the max. cache line size. 777 * 778 * In addition, the minimum of the i-cache stride sizes is calculated for 779 * "flush_icache_range()". 780 */ 781 static void __cpuinit 782 get_max_cacheline_size (void) 783 { 784 unsigned long line_size, max = 1; 785 u64 l, levels, unique_caches; 786 pal_cache_config_info_t cci; 787 s64 status; 788 789 status = ia64_pal_cache_summary(&levels, &unique_caches); 790 if (status != 0) { 791 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 792 __FUNCTION__, status); 793 max = SMP_CACHE_BYTES; 794 /* Safest setup for "flush_icache_range()" */ 795 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 796 goto out; 797 } 798 799 for (l = 0; l < levels; ++l) { 800 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 801 &cci); 802 if (status != 0) { 803 printk(KERN_ERR 804 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 805 __FUNCTION__, l, status); 806 max = SMP_CACHE_BYTES; 807 /* The safest setup for "flush_icache_range()" */ 808 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 809 cci.pcci_unified = 1; 810 } 811 line_size = 1 << cci.pcci_line_size; 812 if (line_size > max) 813 max = line_size; 814 if (!cci.pcci_unified) { 815 status = ia64_pal_cache_config_info(l, 816 /* cache_type (instruction)= */ 1, 817 &cci); 818 if (status != 0) { 819 printk(KERN_ERR 820 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 821 __FUNCTION__, l, status); 822 /* The safest setup for "flush_icache_range()" */ 823 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 824 } 825 } 826 if (cci.pcci_stride < ia64_i_cache_stride_shift) 827 ia64_i_cache_stride_shift = cci.pcci_stride; 828 } 829 out: 830 if (max > ia64_max_cacheline_size) 831 ia64_max_cacheline_size = max; 832 } 833 834 /* 835 * cpu_init() initializes state that is per-CPU. This function acts 836 * as a 'CPU state barrier', nothing should get across. 837 */ 838 void __cpuinit 839 cpu_init (void) 840 { 841 extern void __cpuinit ia64_mmu_init (void *); 842 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 843 unsigned long num_phys_stacked; 844 pal_vm_info_2_u_t vmi; 845 unsigned int max_ctx; 846 struct cpuinfo_ia64 *cpu_info; 847 void *cpu_data; 848 849 cpu_data = per_cpu_init(); 850 #ifdef CONFIG_SMP 851 /* 852 * insert boot cpu into sibling and core mapes 853 * (must be done after per_cpu area is setup) 854 */ 855 if (smp_processor_id() == 0) { 856 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 857 cpu_set(0, cpu_core_map[0]); 858 } 859 #endif 860 861 /* 862 * We set ar.k3 so that assembly code in MCA handler can compute 863 * physical addresses of per cpu variables with a simple: 864 * phys = ar.k3 + &per_cpu_var 865 */ 866 ia64_set_kr(IA64_KR_PER_CPU_DATA, 867 ia64_tpa(cpu_data) - (long) __per_cpu_start); 868 869 get_max_cacheline_size(); 870 871 /* 872 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 873 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 874 * depends on the data returned by identify_cpu(). We break the dependency by 875 * accessing cpu_data() through the canonical per-CPU address. 876 */ 877 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 878 identify_cpu(cpu_info); 879 880 #ifdef CONFIG_MCKINLEY 881 { 882 # define FEATURE_SET 16 883 struct ia64_pal_retval iprv; 884 885 if (cpu_info->family == 0x1f) { 886 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 887 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 888 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 889 (iprv.v1 | 0x80), FEATURE_SET, 0); 890 } 891 } 892 #endif 893 894 /* Clear the stack memory reserved for pt_regs: */ 895 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 896 897 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 898 899 /* 900 * Initialize the page-table base register to a global 901 * directory with all zeroes. This ensure that we can handle 902 * TLB-misses to user address-space even before we created the 903 * first user address-space. This may happen, e.g., due to 904 * aggressive use of lfetch.fault. 905 */ 906 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 907 908 /* 909 * Initialize default control register to defer speculative faults except 910 * for those arising from TLB misses, which are not deferred. The 911 * kernel MUST NOT depend on a particular setting of these bits (in other words, 912 * the kernel must have recovery code for all speculative accesses). Turn on 913 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 914 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 915 * be fine). 916 */ 917 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 918 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 919 atomic_inc(&init_mm.mm_count); 920 current->active_mm = &init_mm; 921 if (current->mm) 922 BUG(); 923 924 ia64_mmu_init(ia64_imva(cpu_data)); 925 ia64_mca_cpu_init(ia64_imva(cpu_data)); 926 927 #ifdef CONFIG_IA32_SUPPORT 928 ia32_cpu_init(); 929 #endif 930 931 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 932 ia64_set_itc(0); 933 934 /* disable all local interrupt sources: */ 935 ia64_set_itv(1 << 16); 936 ia64_set_lrr0(1 << 16); 937 ia64_set_lrr1(1 << 16); 938 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 939 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 940 941 /* clear TPR & XTP to enable all interrupt classes: */ 942 ia64_setreg(_IA64_REG_CR_TPR, 0); 943 944 /* Clear any pending interrupts left by SAL/EFI */ 945 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 946 ia64_eoi(); 947 948 #ifdef CONFIG_SMP 949 normal_xtp(); 950 #endif 951 952 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 953 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 954 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 955 else { 956 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 957 max_ctx = (1U << 15) - 1; /* use architected minimum */ 958 } 959 while (max_ctx < ia64_ctx.max_ctx) { 960 unsigned int old = ia64_ctx.max_ctx; 961 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 962 break; 963 } 964 965 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 966 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 967 "stacked regs\n"); 968 num_phys_stacked = 96; 969 } 970 /* size of physical stacked register partition plus 8 bytes: */ 971 if (num_phys_stacked > max_num_phys_stacked) { 972 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 973 max_num_phys_stacked = num_phys_stacked; 974 } 975 platform_cpu_init(); 976 pm_idle = default_idle; 977 } 978 979 void __init 980 check_bugs (void) 981 { 982 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 983 (unsigned long) __end___mckinley_e9_bundles); 984 } 985 986 static int __init run_dmi_scan(void) 987 { 988 dmi_scan_machine(); 989 return 0; 990 } 991 core_initcall(run_dmi_scan); 992