1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/system.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 extern void ia64_setup_printk_clock(void); 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 79 unsigned long ia64_cycles_per_usec; 80 struct ia64_boot_param *ia64_boot_param; 81 struct screen_info screen_info; 82 unsigned long vga_console_iobase; 83 unsigned long vga_console_membase; 84 85 static struct resource data_resource = { 86 .name = "Kernel data", 87 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 88 }; 89 90 static struct resource code_resource = { 91 .name = "Kernel code", 92 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 93 }; 94 extern void efi_initialize_iomem_resources(struct resource *, 95 struct resource *); 96 extern char _text[], _end[], _etext[]; 97 98 unsigned long ia64_max_cacheline_size; 99 100 int dma_get_cache_alignment(void) 101 { 102 return ia64_max_cacheline_size; 103 } 104 EXPORT_SYMBOL(dma_get_cache_alignment); 105 106 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 107 EXPORT_SYMBOL(ia64_iobase); 108 struct io_space io_space[MAX_IO_SPACES]; 109 EXPORT_SYMBOL(io_space); 110 unsigned int num_io_spaces; 111 112 /* 113 * "flush_icache_range()" needs to know what processor dependent stride size to use 114 * when it makes i-cache(s) coherent with d-caches. 115 */ 116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117 unsigned long ia64_i_cache_stride_shift = ~0; 118 119 /* 120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 123 * address of the second buffer must be aligned to (merge_mask+1) in order to be 124 * mergeable). By default, we assume there is no I/O MMU which can merge physically 125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 126 * page-size of 2^64. 127 */ 128 unsigned long ia64_max_iommu_merge_mask = ~0UL; 129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 130 131 /* 132 * We use a special marker for the end of memory and it uses the extra (+1) slot 133 */ 134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 135 int num_rsvd_regions __initdata; 136 137 138 /* 139 * Filter incoming memory segments based on the primitive map created from the boot 140 * parameters. Segments contained in the map are removed from the memory ranges. A 141 * caller-specified function is called with the memory ranges that remain after filtering. 142 * This routine does not assume the incoming segments are sorted. 143 */ 144 int __init 145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 146 { 147 unsigned long range_start, range_end, prev_start; 148 void (*func)(unsigned long, unsigned long, int); 149 int i; 150 151 #if IGNORE_PFN0 152 if (start == PAGE_OFFSET) { 153 printk(KERN_WARNING "warning: skipping physical page 0\n"); 154 start += PAGE_SIZE; 155 if (start >= end) return 0; 156 } 157 #endif 158 /* 159 * lowest possible address(walker uses virtual) 160 */ 161 prev_start = PAGE_OFFSET; 162 func = arg; 163 164 for (i = 0; i < num_rsvd_regions; ++i) { 165 range_start = max(start, prev_start); 166 range_end = min(end, rsvd_region[i].start); 167 168 if (range_start < range_end) 169 call_pernode_memory(__pa(range_start), range_end - range_start, func); 170 171 /* nothing more available in this segment */ 172 if (range_end == end) return 0; 173 174 prev_start = rsvd_region[i].end; 175 } 176 /* end of memory marker allows full processing inside loop body */ 177 return 0; 178 } 179 180 static void __init 181 sort_regions (struct rsvd_region *rsvd_region, int max) 182 { 183 int j; 184 185 /* simple bubble sorting */ 186 while (max--) { 187 for (j = 0; j < max; ++j) { 188 if (rsvd_region[j].start > rsvd_region[j+1].start) { 189 struct rsvd_region tmp; 190 tmp = rsvd_region[j]; 191 rsvd_region[j] = rsvd_region[j + 1]; 192 rsvd_region[j + 1] = tmp; 193 } 194 } 195 } 196 } 197 198 /* 199 * Request address space for all standard resources 200 */ 201 static int __init register_memory(void) 202 { 203 code_resource.start = ia64_tpa(_text); 204 code_resource.end = ia64_tpa(_etext) - 1; 205 data_resource.start = ia64_tpa(_etext); 206 data_resource.end = ia64_tpa(_end) - 1; 207 efi_initialize_iomem_resources(&code_resource, &data_resource); 208 209 return 0; 210 } 211 212 __initcall(register_memory); 213 214 /** 215 * reserve_memory - setup reserved memory areas 216 * 217 * Setup the reserved memory areas set aside for the boot parameters, 218 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 219 * see include/asm-ia64/meminit.h if you need to define more. 220 */ 221 void __init 222 reserve_memory (void) 223 { 224 int n = 0; 225 226 /* 227 * none of the entries in this table overlap 228 */ 229 rsvd_region[n].start = (unsigned long) ia64_boot_param; 230 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 231 n++; 232 233 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 234 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 235 n++; 236 237 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 238 rsvd_region[n].end = (rsvd_region[n].start 239 + strlen(__va(ia64_boot_param->command_line)) + 1); 240 n++; 241 242 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 243 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 244 n++; 245 246 #ifdef CONFIG_BLK_DEV_INITRD 247 if (ia64_boot_param->initrd_start) { 248 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 249 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 250 n++; 251 } 252 #endif 253 254 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 255 n++; 256 257 #ifdef CONFIG_KEXEC 258 /* crashkernel=size@offset specifies the size to reserve for a crash 259 * kernel. If offset is 0, then it is determined automatically. 260 * By reserving this memory we guarantee that linux never set's it 261 * up as a DMA target.Useful for holding code to do something 262 * appropriate after a kernel panic. 263 */ 264 { 265 char *from = strstr(saved_command_line, "crashkernel="); 266 unsigned long base, size; 267 if (from) { 268 size = memparse(from + 12, &from); 269 if (*from == '@') 270 base = memparse(from+1, &from); 271 else 272 base = 0; 273 if (size) { 274 if (!base) { 275 sort_regions(rsvd_region, n); 276 base = kdump_find_rsvd_region(size, 277 rsvd_region, n); 278 } 279 if (base != ~0UL) { 280 rsvd_region[n].start = 281 (unsigned long)__va(base); 282 rsvd_region[n].end = 283 (unsigned long)__va(base + size); 284 n++; 285 crashk_res.start = base; 286 crashk_res.end = base + size - 1; 287 } 288 } 289 } 290 efi_memmap_res.start = ia64_boot_param->efi_memmap; 291 efi_memmap_res.end = efi_memmap_res.start + 292 ia64_boot_param->efi_memmap_size; 293 boot_param_res.start = __pa(ia64_boot_param); 294 boot_param_res.end = boot_param_res.start + 295 sizeof(*ia64_boot_param); 296 } 297 #endif 298 /* end of memory marker */ 299 rsvd_region[n].start = ~0UL; 300 rsvd_region[n].end = ~0UL; 301 n++; 302 303 num_rsvd_regions = n; 304 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 305 306 sort_regions(rsvd_region, num_rsvd_regions); 307 } 308 309 310 /** 311 * find_initrd - get initrd parameters from the boot parameter structure 312 * 313 * Grab the initrd start and end from the boot parameter struct given us by 314 * the boot loader. 315 */ 316 void __init 317 find_initrd (void) 318 { 319 #ifdef CONFIG_BLK_DEV_INITRD 320 if (ia64_boot_param->initrd_start) { 321 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 322 initrd_end = initrd_start+ia64_boot_param->initrd_size; 323 324 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 325 initrd_start, ia64_boot_param->initrd_size); 326 } 327 #endif 328 } 329 330 static void __init 331 io_port_init (void) 332 { 333 unsigned long phys_iobase; 334 335 /* 336 * Set `iobase' based on the EFI memory map or, failing that, the 337 * value firmware left in ar.k0. 338 * 339 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 340 * the port's virtual address, so ia32_load_state() loads it with a 341 * user virtual address. But in ia64 mode, glibc uses the 342 * *physical* address in ar.k0 to mmap the appropriate area from 343 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 344 * cases, user-mode can only use the legacy 0-64K I/O port space. 345 * 346 * ar.k0 is not involved in kernel I/O port accesses, which can use 347 * any of the I/O port spaces and are done via MMIO using the 348 * virtual mmio_base from the appropriate io_space[]. 349 */ 350 phys_iobase = efi_get_iobase(); 351 if (!phys_iobase) { 352 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 353 printk(KERN_INFO "No I/O port range found in EFI memory map, " 354 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 355 } 356 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 357 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 358 359 /* setup legacy IO port space */ 360 io_space[0].mmio_base = ia64_iobase; 361 io_space[0].sparse = 1; 362 num_io_spaces = 1; 363 } 364 365 /** 366 * early_console_setup - setup debugging console 367 * 368 * Consoles started here require little enough setup that we can start using 369 * them very early in the boot process, either right after the machine 370 * vector initialization, or even before if the drivers can detect their hw. 371 * 372 * Returns non-zero if a console couldn't be setup. 373 */ 374 static inline int __init 375 early_console_setup (char *cmdline) 376 { 377 int earlycons = 0; 378 379 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 380 { 381 extern int sn_serial_console_early_setup(void); 382 if (!sn_serial_console_early_setup()) 383 earlycons++; 384 } 385 #endif 386 #ifdef CONFIG_EFI_PCDP 387 if (!efi_setup_pcdp_console(cmdline)) 388 earlycons++; 389 #endif 390 #ifdef CONFIG_SERIAL_8250_CONSOLE 391 if (!early_serial_console_init(cmdline)) 392 earlycons++; 393 #endif 394 395 return (earlycons) ? 0 : -1; 396 } 397 398 static inline void 399 mark_bsp_online (void) 400 { 401 #ifdef CONFIG_SMP 402 /* If we register an early console, allow CPU 0 to printk */ 403 cpu_set(smp_processor_id(), cpu_online_map); 404 #endif 405 } 406 407 #ifdef CONFIG_SMP 408 static void __init 409 check_for_logical_procs (void) 410 { 411 pal_logical_to_physical_t info; 412 s64 status; 413 414 status = ia64_pal_logical_to_phys(0, &info); 415 if (status == -1) { 416 printk(KERN_INFO "No logical to physical processor mapping " 417 "available\n"); 418 return; 419 } 420 if (status) { 421 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 422 status); 423 return; 424 } 425 /* 426 * Total number of siblings that BSP has. Though not all of them 427 * may have booted successfully. The correct number of siblings 428 * booted is in info.overview_num_log. 429 */ 430 smp_num_siblings = info.overview_tpc; 431 smp_num_cpucores = info.overview_cpp; 432 } 433 #endif 434 435 static __initdata int nomca; 436 static __init int setup_nomca(char *s) 437 { 438 nomca = 1; 439 return 0; 440 } 441 early_param("nomca", setup_nomca); 442 443 #ifdef CONFIG_PROC_VMCORE 444 /* elfcorehdr= specifies the location of elf core header 445 * stored by the crashed kernel. 446 */ 447 static int __init parse_elfcorehdr(char *arg) 448 { 449 if (!arg) 450 return -EINVAL; 451 452 elfcorehdr_addr = memparse(arg, &arg); 453 return 0; 454 } 455 early_param("elfcorehdr", parse_elfcorehdr); 456 #endif /* CONFIG_PROC_VMCORE */ 457 458 void __init 459 setup_arch (char **cmdline_p) 460 { 461 unw_init(); 462 463 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 464 465 *cmdline_p = __va(ia64_boot_param->command_line); 466 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 467 468 efi_init(); 469 io_port_init(); 470 471 parse_early_param(); 472 473 #ifdef CONFIG_IA64_GENERIC 474 machvec_init(NULL); 475 #endif 476 477 if (early_console_setup(*cmdline_p) == 0) 478 mark_bsp_online(); 479 480 #ifdef CONFIG_ACPI 481 /* Initialize the ACPI boot-time table parser */ 482 acpi_table_init(); 483 # ifdef CONFIG_ACPI_NUMA 484 acpi_numa_init(); 485 # endif 486 #else 487 # ifdef CONFIG_SMP 488 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 489 # endif 490 #endif /* CONFIG_APCI_BOOT */ 491 492 find_memory(); 493 494 /* process SAL system table: */ 495 ia64_sal_init(__va(efi.sal_systab)); 496 497 ia64_setup_printk_clock(); 498 499 #ifdef CONFIG_SMP 500 cpu_physical_id(0) = hard_smp_processor_id(); 501 502 cpu_set(0, cpu_sibling_map[0]); 503 cpu_set(0, cpu_core_map[0]); 504 505 check_for_logical_procs(); 506 if (smp_num_cpucores > 1) 507 printk(KERN_INFO 508 "cpu package is Multi-Core capable: number of cores=%d\n", 509 smp_num_cpucores); 510 if (smp_num_siblings > 1) 511 printk(KERN_INFO 512 "cpu package is Multi-Threading capable: number of siblings=%d\n", 513 smp_num_siblings); 514 #endif 515 516 cpu_init(); /* initialize the bootstrap CPU */ 517 mmu_context_init(); /* initialize context_id bitmap */ 518 519 check_sal_cache_flush(); 520 521 #ifdef CONFIG_ACPI 522 acpi_boot_init(); 523 #endif 524 525 #ifdef CONFIG_VT 526 if (!conswitchp) { 527 # if defined(CONFIG_DUMMY_CONSOLE) 528 conswitchp = &dummy_con; 529 # endif 530 # if defined(CONFIG_VGA_CONSOLE) 531 /* 532 * Non-legacy systems may route legacy VGA MMIO range to system 533 * memory. vga_con probes the MMIO hole, so memory looks like 534 * a VGA device to it. The EFI memory map can tell us if it's 535 * memory so we can avoid this problem. 536 */ 537 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 538 conswitchp = &vga_con; 539 # endif 540 } 541 #endif 542 543 /* enable IA-64 Machine Check Abort Handling unless disabled */ 544 if (!nomca) 545 ia64_mca_init(); 546 547 platform_setup(cmdline_p); 548 paging_init(); 549 } 550 551 /* 552 * Display cpu info for all cpu's. 553 */ 554 static int 555 show_cpuinfo (struct seq_file *m, void *v) 556 { 557 #ifdef CONFIG_SMP 558 # define lpj c->loops_per_jiffy 559 # define cpunum c->cpu 560 #else 561 # define lpj loops_per_jiffy 562 # define cpunum 0 563 #endif 564 static struct { 565 unsigned long mask; 566 const char *feature_name; 567 } feature_bits[] = { 568 { 1UL << 0, "branchlong" }, 569 { 1UL << 1, "spontaneous deferral"}, 570 { 1UL << 2, "16-byte atomic ops" } 571 }; 572 char features[128], *cp, *sep; 573 struct cpuinfo_ia64 *c = v; 574 unsigned long mask; 575 unsigned long proc_freq; 576 int i, size; 577 578 mask = c->features; 579 580 /* build the feature string: */ 581 memcpy(features, "standard", 9); 582 cp = features; 583 size = sizeof(features); 584 sep = ""; 585 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 586 if (mask & feature_bits[i].mask) { 587 cp += snprintf(cp, size, "%s%s", sep, 588 feature_bits[i].feature_name), 589 sep = ", "; 590 mask &= ~feature_bits[i].mask; 591 size = sizeof(features) - (cp - features); 592 } 593 } 594 if (mask && size > 1) { 595 /* print unknown features as a hex value */ 596 snprintf(cp, size, "%s0x%lx", sep, mask); 597 } 598 599 proc_freq = cpufreq_quick_get(cpunum); 600 if (!proc_freq) 601 proc_freq = c->proc_freq / 1000; 602 603 seq_printf(m, 604 "processor : %d\n" 605 "vendor : %s\n" 606 "arch : IA-64\n" 607 "family : %u\n" 608 "model : %u\n" 609 "model name : %s\n" 610 "revision : %u\n" 611 "archrev : %u\n" 612 "features : %s\n" 613 "cpu number : %lu\n" 614 "cpu regs : %u\n" 615 "cpu MHz : %lu.%06lu\n" 616 "itc MHz : %lu.%06lu\n" 617 "BogoMIPS : %lu.%02lu\n", 618 cpunum, c->vendor, c->family, c->model, 619 c->model_name, c->revision, c->archrev, 620 features, c->ppn, c->number, 621 proc_freq / 1000, proc_freq % 1000, 622 c->itc_freq / 1000000, c->itc_freq % 1000000, 623 lpj*HZ/500000, (lpj*HZ/5000) % 100); 624 #ifdef CONFIG_SMP 625 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 626 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 627 seq_printf(m, 628 "physical id: %u\n" 629 "core id : %u\n" 630 "thread id : %u\n", 631 c->socket_id, c->core_id, c->thread_id); 632 #endif 633 seq_printf(m,"\n"); 634 635 return 0; 636 } 637 638 static void * 639 c_start (struct seq_file *m, loff_t *pos) 640 { 641 #ifdef CONFIG_SMP 642 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 643 ++*pos; 644 #endif 645 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 646 } 647 648 static void * 649 c_next (struct seq_file *m, void *v, loff_t *pos) 650 { 651 ++*pos; 652 return c_start(m, pos); 653 } 654 655 static void 656 c_stop (struct seq_file *m, void *v) 657 { 658 } 659 660 struct seq_operations cpuinfo_op = { 661 .start = c_start, 662 .next = c_next, 663 .stop = c_stop, 664 .show = show_cpuinfo 665 }; 666 667 static char brandname[128]; 668 669 static char * __cpuinit 670 get_model_name(__u8 family, __u8 model) 671 { 672 char brand[128]; 673 674 memcpy(brand, "Unknown", 8); 675 if (ia64_pal_get_brand_info(brand)) { 676 if (family == 0x7) 677 memcpy(brand, "Merced", 7); 678 else if (family == 0x1f) switch (model) { 679 case 0: memcpy(brand, "McKinley", 9); break; 680 case 1: memcpy(brand, "Madison", 8); break; 681 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 682 } 683 } 684 if (brandname[0] == '\0') 685 return strcpy(brandname, brand); 686 else if (strcmp(brandname, brand) == 0) 687 return brandname; 688 else 689 return kstrdup(brand, GFP_KERNEL); 690 } 691 692 static void __cpuinit 693 identify_cpu (struct cpuinfo_ia64 *c) 694 { 695 union { 696 unsigned long bits[5]; 697 struct { 698 /* id 0 & 1: */ 699 char vendor[16]; 700 701 /* id 2 */ 702 u64 ppn; /* processor serial number */ 703 704 /* id 3: */ 705 unsigned number : 8; 706 unsigned revision : 8; 707 unsigned model : 8; 708 unsigned family : 8; 709 unsigned archrev : 8; 710 unsigned reserved : 24; 711 712 /* id 4: */ 713 u64 features; 714 } field; 715 } cpuid; 716 pal_vm_info_1_u_t vm1; 717 pal_vm_info_2_u_t vm2; 718 pal_status_t status; 719 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 720 int i; 721 for (i = 0; i < 5; ++i) 722 cpuid.bits[i] = ia64_get_cpuid(i); 723 724 memcpy(c->vendor, cpuid.field.vendor, 16); 725 #ifdef CONFIG_SMP 726 c->cpu = smp_processor_id(); 727 728 /* below default values will be overwritten by identify_siblings() 729 * for Multi-Threading/Multi-Core capable cpu's 730 */ 731 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 732 c->socket_id = -1; 733 734 identify_siblings(c); 735 #endif 736 c->ppn = cpuid.field.ppn; 737 c->number = cpuid.field.number; 738 c->revision = cpuid.field.revision; 739 c->model = cpuid.field.model; 740 c->family = cpuid.field.family; 741 c->archrev = cpuid.field.archrev; 742 c->features = cpuid.field.features; 743 c->model_name = get_model_name(c->family, c->model); 744 745 status = ia64_pal_vm_summary(&vm1, &vm2); 746 if (status == PAL_STATUS_SUCCESS) { 747 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 748 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 749 } 750 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 751 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 752 } 753 754 void 755 setup_per_cpu_areas (void) 756 { 757 /* start_kernel() requires this... */ 758 #ifdef CONFIG_ACPI_HOTPLUG_CPU 759 prefill_possible_map(); 760 #endif 761 } 762 763 /* 764 * Calculate the max. cache line size. 765 * 766 * In addition, the minimum of the i-cache stride sizes is calculated for 767 * "flush_icache_range()". 768 */ 769 static void __cpuinit 770 get_max_cacheline_size (void) 771 { 772 unsigned long line_size, max = 1; 773 unsigned int cache_size = 0; 774 u64 l, levels, unique_caches; 775 pal_cache_config_info_t cci; 776 s64 status; 777 778 status = ia64_pal_cache_summary(&levels, &unique_caches); 779 if (status != 0) { 780 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 781 __FUNCTION__, status); 782 max = SMP_CACHE_BYTES; 783 /* Safest setup for "flush_icache_range()" */ 784 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 785 goto out; 786 } 787 788 for (l = 0; l < levels; ++l) { 789 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 790 &cci); 791 if (status != 0) { 792 printk(KERN_ERR 793 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 794 __FUNCTION__, l, status); 795 max = SMP_CACHE_BYTES; 796 /* The safest setup for "flush_icache_range()" */ 797 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 798 cci.pcci_unified = 1; 799 } 800 line_size = 1 << cci.pcci_line_size; 801 if (line_size > max) 802 max = line_size; 803 if (cache_size < cci.pcci_cache_size) 804 cache_size = cci.pcci_cache_size; 805 if (!cci.pcci_unified) { 806 status = ia64_pal_cache_config_info(l, 807 /* cache_type (instruction)= */ 1, 808 &cci); 809 if (status != 0) { 810 printk(KERN_ERR 811 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 812 __FUNCTION__, l, status); 813 /* The safest setup for "flush_icache_range()" */ 814 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 815 } 816 } 817 if (cci.pcci_stride < ia64_i_cache_stride_shift) 818 ia64_i_cache_stride_shift = cci.pcci_stride; 819 } 820 out: 821 #ifdef CONFIG_SMP 822 max_cache_size = max(max_cache_size, cache_size); 823 #endif 824 if (max > ia64_max_cacheline_size) 825 ia64_max_cacheline_size = max; 826 } 827 828 /* 829 * cpu_init() initializes state that is per-CPU. This function acts 830 * as a 'CPU state barrier', nothing should get across. 831 */ 832 void __cpuinit 833 cpu_init (void) 834 { 835 extern void __cpuinit ia64_mmu_init (void *); 836 unsigned long num_phys_stacked; 837 pal_vm_info_2_u_t vmi; 838 unsigned int max_ctx; 839 struct cpuinfo_ia64 *cpu_info; 840 void *cpu_data; 841 842 cpu_data = per_cpu_init(); 843 844 /* 845 * We set ar.k3 so that assembly code in MCA handler can compute 846 * physical addresses of per cpu variables with a simple: 847 * phys = ar.k3 + &per_cpu_var 848 */ 849 ia64_set_kr(IA64_KR_PER_CPU_DATA, 850 ia64_tpa(cpu_data) - (long) __per_cpu_start); 851 852 get_max_cacheline_size(); 853 854 /* 855 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 856 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 857 * depends on the data returned by identify_cpu(). We break the dependency by 858 * accessing cpu_data() through the canonical per-CPU address. 859 */ 860 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 861 identify_cpu(cpu_info); 862 863 #ifdef CONFIG_MCKINLEY 864 { 865 # define FEATURE_SET 16 866 struct ia64_pal_retval iprv; 867 868 if (cpu_info->family == 0x1f) { 869 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 870 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 871 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 872 (iprv.v1 | 0x80), FEATURE_SET, 0); 873 } 874 } 875 #endif 876 877 /* Clear the stack memory reserved for pt_regs: */ 878 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 879 880 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 881 882 /* 883 * Initialize the page-table base register to a global 884 * directory with all zeroes. This ensure that we can handle 885 * TLB-misses to user address-space even before we created the 886 * first user address-space. This may happen, e.g., due to 887 * aggressive use of lfetch.fault. 888 */ 889 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 890 891 /* 892 * Initialize default control register to defer speculative faults except 893 * for those arising from TLB misses, which are not deferred. The 894 * kernel MUST NOT depend on a particular setting of these bits (in other words, 895 * the kernel must have recovery code for all speculative accesses). Turn on 896 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 897 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 898 * be fine). 899 */ 900 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 901 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 902 atomic_inc(&init_mm.mm_count); 903 current->active_mm = &init_mm; 904 if (current->mm) 905 BUG(); 906 907 ia64_mmu_init(ia64_imva(cpu_data)); 908 ia64_mca_cpu_init(ia64_imva(cpu_data)); 909 910 #ifdef CONFIG_IA32_SUPPORT 911 ia32_cpu_init(); 912 #endif 913 914 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 915 ia64_set_itc(0); 916 917 /* disable all local interrupt sources: */ 918 ia64_set_itv(1 << 16); 919 ia64_set_lrr0(1 << 16); 920 ia64_set_lrr1(1 << 16); 921 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 922 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 923 924 /* clear TPR & XTP to enable all interrupt classes: */ 925 ia64_setreg(_IA64_REG_CR_TPR, 0); 926 #ifdef CONFIG_SMP 927 normal_xtp(); 928 #endif 929 930 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 931 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 932 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 933 else { 934 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 935 max_ctx = (1U << 15) - 1; /* use architected minimum */ 936 } 937 while (max_ctx < ia64_ctx.max_ctx) { 938 unsigned int old = ia64_ctx.max_ctx; 939 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 940 break; 941 } 942 943 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 944 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 945 "stacked regs\n"); 946 num_phys_stacked = 96; 947 } 948 /* size of physical stacked register partition plus 8 bytes: */ 949 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 950 platform_cpu_init(); 951 pm_idle = default_idle; 952 } 953 954 /* 955 * On SMP systems, when the scheduler does migration-cost autodetection, 956 * it needs a way to flush as much of the CPU's caches as possible. 957 */ 958 void sched_cacheflush(void) 959 { 960 ia64_sal_cache_flush(3); 961 } 962 963 void __init 964 check_bugs (void) 965 { 966 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 967 (unsigned long) __end___mckinley_e9_bundles); 968 } 969 970 static int __init run_dmi_scan(void) 971 { 972 dmi_scan_machine(); 973 return 0; 974 } 975 core_initcall(run_dmi_scan); 976