1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/config.h> 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/bootmem.h> 31 #include <linux/console.h> 32 #include <linux/delay.h> 33 #include <linux/kernel.h> 34 #include <linux/reboot.h> 35 #include <linux/sched.h> 36 #include <linux/seq_file.h> 37 #include <linux/string.h> 38 #include <linux/threads.h> 39 #include <linux/tty.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/platform.h> 45 #include <linux/pm.h> 46 #include <linux/cpufreq.h> 47 48 #include <asm/ia32.h> 49 #include <asm/machvec.h> 50 #include <asm/mca.h> 51 #include <asm/meminit.h> 52 #include <asm/page.h> 53 #include <asm/patch.h> 54 #include <asm/pgtable.h> 55 #include <asm/processor.h> 56 #include <asm/sal.h> 57 #include <asm/sections.h> 58 #include <asm/serial.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 64 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 65 # error "struct cpuinfo_ia64 too big!" 66 #endif 67 68 #ifdef CONFIG_SMP 69 unsigned long __per_cpu_offset[NR_CPUS]; 70 EXPORT_SYMBOL(__per_cpu_offset); 71 #endif 72 73 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 74 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 75 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 76 unsigned long ia64_cycles_per_usec; 77 struct ia64_boot_param *ia64_boot_param; 78 struct screen_info screen_info; 79 unsigned long vga_console_iobase; 80 unsigned long vga_console_membase; 81 82 static struct resource data_resource = { 83 .name = "Kernel data", 84 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 85 }; 86 87 static struct resource code_resource = { 88 .name = "Kernel code", 89 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 90 }; 91 extern void efi_initialize_iomem_resources(struct resource *, 92 struct resource *); 93 extern char _text[], _end[], _etext[]; 94 95 unsigned long ia64_max_cacheline_size; 96 97 int dma_get_cache_alignment(void) 98 { 99 return ia64_max_cacheline_size; 100 } 101 EXPORT_SYMBOL(dma_get_cache_alignment); 102 103 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 104 EXPORT_SYMBOL(ia64_iobase); 105 struct io_space io_space[MAX_IO_SPACES]; 106 EXPORT_SYMBOL(io_space); 107 unsigned int num_io_spaces; 108 109 /* 110 * "flush_icache_range()" needs to know what processor dependent stride size to use 111 * when it makes i-cache(s) coherent with d-caches. 112 */ 113 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 114 unsigned long ia64_i_cache_stride_shift = ~0; 115 116 /* 117 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 118 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 119 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 120 * address of the second buffer must be aligned to (merge_mask+1) in order to be 121 * mergeable). By default, we assume there is no I/O MMU which can merge physically 122 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 123 * page-size of 2^64. 124 */ 125 unsigned long ia64_max_iommu_merge_mask = ~0UL; 126 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 127 128 /* 129 * We use a special marker for the end of memory and it uses the extra (+1) slot 130 */ 131 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1]; 132 int num_rsvd_regions; 133 134 135 /* 136 * Filter incoming memory segments based on the primitive map created from the boot 137 * parameters. Segments contained in the map are removed from the memory ranges. A 138 * caller-specified function is called with the memory ranges that remain after filtering. 139 * This routine does not assume the incoming segments are sorted. 140 */ 141 int 142 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 143 { 144 unsigned long range_start, range_end, prev_start; 145 void (*func)(unsigned long, unsigned long, int); 146 int i; 147 148 #if IGNORE_PFN0 149 if (start == PAGE_OFFSET) { 150 printk(KERN_WARNING "warning: skipping physical page 0\n"); 151 start += PAGE_SIZE; 152 if (start >= end) return 0; 153 } 154 #endif 155 /* 156 * lowest possible address(walker uses virtual) 157 */ 158 prev_start = PAGE_OFFSET; 159 func = arg; 160 161 for (i = 0; i < num_rsvd_regions; ++i) { 162 range_start = max(start, prev_start); 163 range_end = min(end, rsvd_region[i].start); 164 165 if (range_start < range_end) 166 call_pernode_memory(__pa(range_start), range_end - range_start, func); 167 168 /* nothing more available in this segment */ 169 if (range_end == end) return 0; 170 171 prev_start = rsvd_region[i].end; 172 } 173 /* end of memory marker allows full processing inside loop body */ 174 return 0; 175 } 176 177 static void 178 sort_regions (struct rsvd_region *rsvd_region, int max) 179 { 180 int j; 181 182 /* simple bubble sorting */ 183 while (max--) { 184 for (j = 0; j < max; ++j) { 185 if (rsvd_region[j].start > rsvd_region[j+1].start) { 186 struct rsvd_region tmp; 187 tmp = rsvd_region[j]; 188 rsvd_region[j] = rsvd_region[j + 1]; 189 rsvd_region[j + 1] = tmp; 190 } 191 } 192 } 193 } 194 195 /* 196 * Request address space for all standard resources 197 */ 198 static int __init register_memory(void) 199 { 200 code_resource.start = ia64_tpa(_text); 201 code_resource.end = ia64_tpa(_etext) - 1; 202 data_resource.start = ia64_tpa(_etext); 203 data_resource.end = ia64_tpa(_end) - 1; 204 efi_initialize_iomem_resources(&code_resource, &data_resource); 205 206 return 0; 207 } 208 209 __initcall(register_memory); 210 211 /** 212 * reserve_memory - setup reserved memory areas 213 * 214 * Setup the reserved memory areas set aside for the boot parameters, 215 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 216 * see include/asm-ia64/meminit.h if you need to define more. 217 */ 218 void 219 reserve_memory (void) 220 { 221 int n = 0; 222 223 /* 224 * none of the entries in this table overlap 225 */ 226 rsvd_region[n].start = (unsigned long) ia64_boot_param; 227 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 228 n++; 229 230 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 231 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 232 n++; 233 234 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 235 rsvd_region[n].end = (rsvd_region[n].start 236 + strlen(__va(ia64_boot_param->command_line)) + 1); 237 n++; 238 239 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 240 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 241 n++; 242 243 #ifdef CONFIG_BLK_DEV_INITRD 244 if (ia64_boot_param->initrd_start) { 245 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 246 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 247 n++; 248 } 249 #endif 250 251 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 252 n++; 253 254 /* end of memory marker */ 255 rsvd_region[n].start = ~0UL; 256 rsvd_region[n].end = ~0UL; 257 n++; 258 259 num_rsvd_regions = n; 260 261 sort_regions(rsvd_region, num_rsvd_regions); 262 } 263 264 /** 265 * find_initrd - get initrd parameters from the boot parameter structure 266 * 267 * Grab the initrd start and end from the boot parameter struct given us by 268 * the boot loader. 269 */ 270 void 271 find_initrd (void) 272 { 273 #ifdef CONFIG_BLK_DEV_INITRD 274 if (ia64_boot_param->initrd_start) { 275 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 276 initrd_end = initrd_start+ia64_boot_param->initrd_size; 277 278 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 279 initrd_start, ia64_boot_param->initrd_size); 280 } 281 #endif 282 } 283 284 static void __init 285 io_port_init (void) 286 { 287 unsigned long phys_iobase; 288 289 /* 290 * Set `iobase' based on the EFI memory map or, failing that, the 291 * value firmware left in ar.k0. 292 * 293 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 294 * the port's virtual address, so ia32_load_state() loads it with a 295 * user virtual address. But in ia64 mode, glibc uses the 296 * *physical* address in ar.k0 to mmap the appropriate area from 297 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 298 * cases, user-mode can only use the legacy 0-64K I/O port space. 299 * 300 * ar.k0 is not involved in kernel I/O port accesses, which can use 301 * any of the I/O port spaces and are done via MMIO using the 302 * virtual mmio_base from the appropriate io_space[]. 303 */ 304 phys_iobase = efi_get_iobase(); 305 if (!phys_iobase) { 306 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 307 printk(KERN_INFO "No I/O port range found in EFI memory map, " 308 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 309 } 310 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 311 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 312 313 /* setup legacy IO port space */ 314 io_space[0].mmio_base = ia64_iobase; 315 io_space[0].sparse = 1; 316 num_io_spaces = 1; 317 } 318 319 /** 320 * early_console_setup - setup debugging console 321 * 322 * Consoles started here require little enough setup that we can start using 323 * them very early in the boot process, either right after the machine 324 * vector initialization, or even before if the drivers can detect their hw. 325 * 326 * Returns non-zero if a console couldn't be setup. 327 */ 328 static inline int __init 329 early_console_setup (char *cmdline) 330 { 331 int earlycons = 0; 332 333 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 334 { 335 extern int sn_serial_console_early_setup(void); 336 if (!sn_serial_console_early_setup()) 337 earlycons++; 338 } 339 #endif 340 #ifdef CONFIG_EFI_PCDP 341 if (!efi_setup_pcdp_console(cmdline)) 342 earlycons++; 343 #endif 344 #ifdef CONFIG_SERIAL_8250_CONSOLE 345 if (!early_serial_console_init(cmdline)) 346 earlycons++; 347 #endif 348 349 return (earlycons) ? 0 : -1; 350 } 351 352 static inline void 353 mark_bsp_online (void) 354 { 355 #ifdef CONFIG_SMP 356 /* If we register an early console, allow CPU 0 to printk */ 357 cpu_set(smp_processor_id(), cpu_online_map); 358 #endif 359 } 360 361 #ifdef CONFIG_SMP 362 static void 363 check_for_logical_procs (void) 364 { 365 pal_logical_to_physical_t info; 366 s64 status; 367 368 status = ia64_pal_logical_to_phys(0, &info); 369 if (status == -1) { 370 printk(KERN_INFO "No logical to physical processor mapping " 371 "available\n"); 372 return; 373 } 374 if (status) { 375 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 376 status); 377 return; 378 } 379 /* 380 * Total number of siblings that BSP has. Though not all of them 381 * may have booted successfully. The correct number of siblings 382 * booted is in info.overview_num_log. 383 */ 384 smp_num_siblings = info.overview_tpc; 385 smp_num_cpucores = info.overview_cpp; 386 } 387 #endif 388 389 void __init 390 setup_arch (char **cmdline_p) 391 { 392 unw_init(); 393 394 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 395 396 *cmdline_p = __va(ia64_boot_param->command_line); 397 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 398 399 efi_init(); 400 io_port_init(); 401 402 #ifdef CONFIG_IA64_GENERIC 403 { 404 const char *mvec_name = strstr (*cmdline_p, "machvec="); 405 char str[64]; 406 407 if (mvec_name) { 408 const char *end; 409 size_t len; 410 411 mvec_name += 8; 412 end = strchr (mvec_name, ' '); 413 if (end) 414 len = end - mvec_name; 415 else 416 len = strlen (mvec_name); 417 len = min(len, sizeof (str) - 1); 418 strncpy (str, mvec_name, len); 419 str[len] = '\0'; 420 mvec_name = str; 421 } else 422 mvec_name = acpi_get_sysname(); 423 machvec_init(mvec_name); 424 } 425 #endif 426 427 if (early_console_setup(*cmdline_p) == 0) 428 mark_bsp_online(); 429 430 #ifdef CONFIG_ACPI 431 /* Initialize the ACPI boot-time table parser */ 432 acpi_table_init(); 433 # ifdef CONFIG_ACPI_NUMA 434 acpi_numa_init(); 435 # endif 436 #else 437 # ifdef CONFIG_SMP 438 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 439 # endif 440 #endif /* CONFIG_APCI_BOOT */ 441 442 find_memory(); 443 444 /* process SAL system table: */ 445 ia64_sal_init(efi.sal_systab); 446 447 #ifdef CONFIG_SMP 448 cpu_physical_id(0) = hard_smp_processor_id(); 449 450 cpu_set(0, cpu_sibling_map[0]); 451 cpu_set(0, cpu_core_map[0]); 452 453 check_for_logical_procs(); 454 if (smp_num_cpucores > 1) 455 printk(KERN_INFO 456 "cpu package is Multi-Core capable: number of cores=%d\n", 457 smp_num_cpucores); 458 if (smp_num_siblings > 1) 459 printk(KERN_INFO 460 "cpu package is Multi-Threading capable: number of siblings=%d\n", 461 smp_num_siblings); 462 #endif 463 464 cpu_init(); /* initialize the bootstrap CPU */ 465 mmu_context_init(); /* initialize context_id bitmap */ 466 467 #ifdef CONFIG_ACPI 468 acpi_boot_init(); 469 #endif 470 471 #ifdef CONFIG_VT 472 if (!conswitchp) { 473 # if defined(CONFIG_DUMMY_CONSOLE) 474 conswitchp = &dummy_con; 475 # endif 476 # if defined(CONFIG_VGA_CONSOLE) 477 /* 478 * Non-legacy systems may route legacy VGA MMIO range to system 479 * memory. vga_con probes the MMIO hole, so memory looks like 480 * a VGA device to it. The EFI memory map can tell us if it's 481 * memory so we can avoid this problem. 482 */ 483 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 484 conswitchp = &vga_con; 485 # endif 486 } 487 #endif 488 489 /* enable IA-64 Machine Check Abort Handling unless disabled */ 490 if (!strstr(saved_command_line, "nomca")) 491 ia64_mca_init(); 492 493 platform_setup(cmdline_p); 494 paging_init(); 495 } 496 497 /* 498 * Display cpu info for all cpu's. 499 */ 500 static int 501 show_cpuinfo (struct seq_file *m, void *v) 502 { 503 #ifdef CONFIG_SMP 504 # define lpj c->loops_per_jiffy 505 # define cpunum c->cpu 506 #else 507 # define lpj loops_per_jiffy 508 # define cpunum 0 509 #endif 510 static struct { 511 unsigned long mask; 512 const char *feature_name; 513 } feature_bits[] = { 514 { 1UL << 0, "branchlong" }, 515 { 1UL << 1, "spontaneous deferral"}, 516 { 1UL << 2, "16-byte atomic ops" } 517 }; 518 char family[32], features[128], *cp, sep; 519 struct cpuinfo_ia64 *c = v; 520 unsigned long mask; 521 unsigned int proc_freq; 522 int i; 523 524 mask = c->features; 525 526 switch (c->family) { 527 case 0x07: memcpy(family, "Itanium", 8); break; 528 case 0x1f: memcpy(family, "Itanium 2", 10); break; 529 default: sprintf(family, "%u", c->family); break; 530 } 531 532 /* build the feature string: */ 533 memcpy(features, " standard", 10); 534 cp = features; 535 sep = 0; 536 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 537 if (mask & feature_bits[i].mask) { 538 if (sep) 539 *cp++ = sep; 540 sep = ','; 541 *cp++ = ' '; 542 strcpy(cp, feature_bits[i].feature_name); 543 cp += strlen(feature_bits[i].feature_name); 544 mask &= ~feature_bits[i].mask; 545 } 546 } 547 if (mask) { 548 /* print unknown features as a hex value: */ 549 if (sep) 550 *cp++ = sep; 551 sprintf(cp, " 0x%lx", mask); 552 } 553 554 proc_freq = cpufreq_quick_get(cpunum); 555 if (!proc_freq) 556 proc_freq = c->proc_freq / 1000; 557 558 seq_printf(m, 559 "processor : %d\n" 560 "vendor : %s\n" 561 "arch : IA-64\n" 562 "family : %s\n" 563 "model : %u\n" 564 "revision : %u\n" 565 "archrev : %u\n" 566 "features :%s\n" /* don't change this---it _is_ right! */ 567 "cpu number : %lu\n" 568 "cpu regs : %u\n" 569 "cpu MHz : %lu.%06lu\n" 570 "itc MHz : %lu.%06lu\n" 571 "BogoMIPS : %lu.%02lu\n", 572 cpunum, c->vendor, family, c->model, c->revision, c->archrev, 573 features, c->ppn, c->number, 574 proc_freq / 1000, proc_freq % 1000, 575 c->itc_freq / 1000000, c->itc_freq % 1000000, 576 lpj*HZ/500000, (lpj*HZ/5000) % 100); 577 #ifdef CONFIG_SMP 578 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 579 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 580 seq_printf(m, 581 "physical id: %u\n" 582 "core id : %u\n" 583 "thread id : %u\n", 584 c->socket_id, c->core_id, c->thread_id); 585 #endif 586 seq_printf(m,"\n"); 587 588 return 0; 589 } 590 591 static void * 592 c_start (struct seq_file *m, loff_t *pos) 593 { 594 #ifdef CONFIG_SMP 595 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 596 ++*pos; 597 #endif 598 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 599 } 600 601 static void * 602 c_next (struct seq_file *m, void *v, loff_t *pos) 603 { 604 ++*pos; 605 return c_start(m, pos); 606 } 607 608 static void 609 c_stop (struct seq_file *m, void *v) 610 { 611 } 612 613 struct seq_operations cpuinfo_op = { 614 .start = c_start, 615 .next = c_next, 616 .stop = c_stop, 617 .show = show_cpuinfo 618 }; 619 620 void 621 identify_cpu (struct cpuinfo_ia64 *c) 622 { 623 union { 624 unsigned long bits[5]; 625 struct { 626 /* id 0 & 1: */ 627 char vendor[16]; 628 629 /* id 2 */ 630 u64 ppn; /* processor serial number */ 631 632 /* id 3: */ 633 unsigned number : 8; 634 unsigned revision : 8; 635 unsigned model : 8; 636 unsigned family : 8; 637 unsigned archrev : 8; 638 unsigned reserved : 24; 639 640 /* id 4: */ 641 u64 features; 642 } field; 643 } cpuid; 644 pal_vm_info_1_u_t vm1; 645 pal_vm_info_2_u_t vm2; 646 pal_status_t status; 647 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 648 int i; 649 650 for (i = 0; i < 5; ++i) 651 cpuid.bits[i] = ia64_get_cpuid(i); 652 653 memcpy(c->vendor, cpuid.field.vendor, 16); 654 #ifdef CONFIG_SMP 655 c->cpu = smp_processor_id(); 656 657 /* below default values will be overwritten by identify_siblings() 658 * for Multi-Threading/Multi-Core capable cpu's 659 */ 660 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 661 c->socket_id = -1; 662 663 identify_siblings(c); 664 #endif 665 c->ppn = cpuid.field.ppn; 666 c->number = cpuid.field.number; 667 c->revision = cpuid.field.revision; 668 c->model = cpuid.field.model; 669 c->family = cpuid.field.family; 670 c->archrev = cpuid.field.archrev; 671 c->features = cpuid.field.features; 672 673 status = ia64_pal_vm_summary(&vm1, &vm2); 674 if (status == PAL_STATUS_SUCCESS) { 675 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 676 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 677 } 678 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 679 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 680 } 681 682 void 683 setup_per_cpu_areas (void) 684 { 685 /* start_kernel() requires this... */ 686 } 687 688 /* 689 * Calculate the max. cache line size. 690 * 691 * In addition, the minimum of the i-cache stride sizes is calculated for 692 * "flush_icache_range()". 693 */ 694 static void 695 get_max_cacheline_size (void) 696 { 697 unsigned long line_size, max = 1; 698 u64 l, levels, unique_caches; 699 pal_cache_config_info_t cci; 700 s64 status; 701 702 status = ia64_pal_cache_summary(&levels, &unique_caches); 703 if (status != 0) { 704 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 705 __FUNCTION__, status); 706 max = SMP_CACHE_BYTES; 707 /* Safest setup for "flush_icache_range()" */ 708 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 709 goto out; 710 } 711 712 for (l = 0; l < levels; ++l) { 713 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 714 &cci); 715 if (status != 0) { 716 printk(KERN_ERR 717 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 718 __FUNCTION__, l, status); 719 max = SMP_CACHE_BYTES; 720 /* The safest setup for "flush_icache_range()" */ 721 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 722 cci.pcci_unified = 1; 723 } 724 line_size = 1 << cci.pcci_line_size; 725 if (line_size > max) 726 max = line_size; 727 if (!cci.pcci_unified) { 728 status = ia64_pal_cache_config_info(l, 729 /* cache_type (instruction)= */ 1, 730 &cci); 731 if (status != 0) { 732 printk(KERN_ERR 733 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 734 __FUNCTION__, l, status); 735 /* The safest setup for "flush_icache_range()" */ 736 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 737 } 738 } 739 if (cci.pcci_stride < ia64_i_cache_stride_shift) 740 ia64_i_cache_stride_shift = cci.pcci_stride; 741 } 742 out: 743 if (max > ia64_max_cacheline_size) 744 ia64_max_cacheline_size = max; 745 } 746 747 /* 748 * cpu_init() initializes state that is per-CPU. This function acts 749 * as a 'CPU state barrier', nothing should get across. 750 */ 751 void 752 cpu_init (void) 753 { 754 extern void __devinit ia64_mmu_init (void *); 755 unsigned long num_phys_stacked; 756 pal_vm_info_2_u_t vmi; 757 unsigned int max_ctx; 758 struct cpuinfo_ia64 *cpu_info; 759 void *cpu_data; 760 761 cpu_data = per_cpu_init(); 762 763 /* 764 * We set ar.k3 so that assembly code in MCA handler can compute 765 * physical addresses of per cpu variables with a simple: 766 * phys = ar.k3 + &per_cpu_var 767 */ 768 ia64_set_kr(IA64_KR_PER_CPU_DATA, 769 ia64_tpa(cpu_data) - (long) __per_cpu_start); 770 771 get_max_cacheline_size(); 772 773 /* 774 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 775 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 776 * depends on the data returned by identify_cpu(). We break the dependency by 777 * accessing cpu_data() through the canonical per-CPU address. 778 */ 779 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 780 identify_cpu(cpu_info); 781 782 #ifdef CONFIG_MCKINLEY 783 { 784 # define FEATURE_SET 16 785 struct ia64_pal_retval iprv; 786 787 if (cpu_info->family == 0x1f) { 788 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 789 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 790 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 791 (iprv.v1 | 0x80), FEATURE_SET, 0); 792 } 793 } 794 #endif 795 796 /* Clear the stack memory reserved for pt_regs: */ 797 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs)); 798 799 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 800 801 /* 802 * Initialize the page-table base register to a global 803 * directory with all zeroes. This ensure that we can handle 804 * TLB-misses to user address-space even before we created the 805 * first user address-space. This may happen, e.g., due to 806 * aggressive use of lfetch.fault. 807 */ 808 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 809 810 /* 811 * Initialize default control register to defer speculative faults except 812 * for those arising from TLB misses, which are not deferred. The 813 * kernel MUST NOT depend on a particular setting of these bits (in other words, 814 * the kernel must have recovery code for all speculative accesses). Turn on 815 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 816 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 817 * be fine). 818 */ 819 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 820 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 821 atomic_inc(&init_mm.mm_count); 822 current->active_mm = &init_mm; 823 if (current->mm) 824 BUG(); 825 826 ia64_mmu_init(ia64_imva(cpu_data)); 827 ia64_mca_cpu_init(ia64_imva(cpu_data)); 828 829 #ifdef CONFIG_IA32_SUPPORT 830 ia32_cpu_init(); 831 #endif 832 833 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 834 ia64_set_itc(0); 835 836 /* disable all local interrupt sources: */ 837 ia64_set_itv(1 << 16); 838 ia64_set_lrr0(1 << 16); 839 ia64_set_lrr1(1 << 16); 840 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 841 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 842 843 /* clear TPR & XTP to enable all interrupt classes: */ 844 ia64_setreg(_IA64_REG_CR_TPR, 0); 845 #ifdef CONFIG_SMP 846 normal_xtp(); 847 #endif 848 849 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 850 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 851 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 852 else { 853 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 854 max_ctx = (1U << 15) - 1; /* use architected minimum */ 855 } 856 while (max_ctx < ia64_ctx.max_ctx) { 857 unsigned int old = ia64_ctx.max_ctx; 858 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 859 break; 860 } 861 862 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 863 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 864 "stacked regs\n"); 865 num_phys_stacked = 96; 866 } 867 /* size of physical stacked register partition plus 8 bytes: */ 868 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 869 platform_cpu_init(); 870 pm_idle = default_idle; 871 } 872 873 void 874 check_bugs (void) 875 { 876 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 877 (unsigned long) __end___mckinley_e9_bundles); 878 } 879