1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/hpsim.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 extern void ia64_setup_printk_clock(void); 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 extern char _text[], _end[], _etext[]; 94 95 unsigned long ia64_max_cacheline_size; 96 97 int dma_get_cache_alignment(void) 98 { 99 return ia64_max_cacheline_size; 100 } 101 EXPORT_SYMBOL(dma_get_cache_alignment); 102 103 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 104 EXPORT_SYMBOL(ia64_iobase); 105 struct io_space io_space[MAX_IO_SPACES]; 106 EXPORT_SYMBOL(io_space); 107 unsigned int num_io_spaces; 108 109 /* 110 * "flush_icache_range()" needs to know what processor dependent stride size to use 111 * when it makes i-cache(s) coherent with d-caches. 112 */ 113 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 114 unsigned long ia64_i_cache_stride_shift = ~0; 115 116 /* 117 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 118 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 119 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 120 * address of the second buffer must be aligned to (merge_mask+1) in order to be 121 * mergeable). By default, we assume there is no I/O MMU which can merge physically 122 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 123 * page-size of 2^64. 124 */ 125 unsigned long ia64_max_iommu_merge_mask = ~0UL; 126 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 127 128 /* 129 * We use a special marker for the end of memory and it uses the extra (+1) slot 130 */ 131 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 132 int num_rsvd_regions __initdata; 133 134 135 /* 136 * Filter incoming memory segments based on the primitive map created from the boot 137 * parameters. Segments contained in the map are removed from the memory ranges. A 138 * caller-specified function is called with the memory ranges that remain after filtering. 139 * This routine does not assume the incoming segments are sorted. 140 */ 141 int __init 142 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 143 { 144 unsigned long range_start, range_end, prev_start; 145 void (*func)(unsigned long, unsigned long, int); 146 int i; 147 148 #if IGNORE_PFN0 149 if (start == PAGE_OFFSET) { 150 printk(KERN_WARNING "warning: skipping physical page 0\n"); 151 start += PAGE_SIZE; 152 if (start >= end) return 0; 153 } 154 #endif 155 /* 156 * lowest possible address(walker uses virtual) 157 */ 158 prev_start = PAGE_OFFSET; 159 func = arg; 160 161 for (i = 0; i < num_rsvd_regions; ++i) { 162 range_start = max(start, prev_start); 163 range_end = min(end, rsvd_region[i].start); 164 165 if (range_start < range_end) 166 call_pernode_memory(__pa(range_start), range_end - range_start, func); 167 168 /* nothing more available in this segment */ 169 if (range_end == end) return 0; 170 171 prev_start = rsvd_region[i].end; 172 } 173 /* end of memory marker allows full processing inside loop body */ 174 return 0; 175 } 176 177 static void __init 178 sort_regions (struct rsvd_region *rsvd_region, int max) 179 { 180 int j; 181 182 /* simple bubble sorting */ 183 while (max--) { 184 for (j = 0; j < max; ++j) { 185 if (rsvd_region[j].start > rsvd_region[j+1].start) { 186 struct rsvd_region tmp; 187 tmp = rsvd_region[j]; 188 rsvd_region[j] = rsvd_region[j + 1]; 189 rsvd_region[j + 1] = tmp; 190 } 191 } 192 } 193 } 194 195 /* 196 * Request address space for all standard resources 197 */ 198 static int __init register_memory(void) 199 { 200 code_resource.start = ia64_tpa(_text); 201 code_resource.end = ia64_tpa(_etext) - 1; 202 data_resource.start = ia64_tpa(_etext); 203 data_resource.end = ia64_tpa(_end) - 1; 204 efi_initialize_iomem_resources(&code_resource, &data_resource); 205 206 return 0; 207 } 208 209 __initcall(register_memory); 210 211 /** 212 * reserve_memory - setup reserved memory areas 213 * 214 * Setup the reserved memory areas set aside for the boot parameters, 215 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 216 * see include/asm-ia64/meminit.h if you need to define more. 217 */ 218 void __init 219 reserve_memory (void) 220 { 221 int n = 0; 222 223 /* 224 * none of the entries in this table overlap 225 */ 226 rsvd_region[n].start = (unsigned long) ia64_boot_param; 227 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 228 n++; 229 230 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 231 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 232 n++; 233 234 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 235 rsvd_region[n].end = (rsvd_region[n].start 236 + strlen(__va(ia64_boot_param->command_line)) + 1); 237 n++; 238 239 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 240 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 241 n++; 242 243 #ifdef CONFIG_BLK_DEV_INITRD 244 if (ia64_boot_param->initrd_start) { 245 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 246 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 247 n++; 248 } 249 #endif 250 251 #ifdef CONFIG_PROC_VMCORE 252 if (reserve_elfcorehdr(&rsvd_region[n].start, 253 &rsvd_region[n].end) == 0) 254 n++; 255 #endif 256 257 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 258 n++; 259 260 #ifdef CONFIG_KEXEC 261 /* crashkernel=size@offset specifies the size to reserve for a crash 262 * kernel. If offset is 0, then it is determined automatically. 263 * By reserving this memory we guarantee that linux never set's it 264 * up as a DMA target.Useful for holding code to do something 265 * appropriate after a kernel panic. 266 */ 267 { 268 char *from = strstr(boot_command_line, "crashkernel="); 269 unsigned long base, size; 270 if (from) { 271 size = memparse(from + 12, &from); 272 if (*from == '@') 273 base = memparse(from+1, &from); 274 else 275 base = 0; 276 if (size) { 277 if (!base) { 278 sort_regions(rsvd_region, n); 279 base = kdump_find_rsvd_region(size, 280 rsvd_region, n); 281 } 282 if (base != ~0UL) { 283 rsvd_region[n].start = 284 (unsigned long)__va(base); 285 rsvd_region[n].end = 286 (unsigned long)__va(base + size); 287 n++; 288 crashk_res.start = base; 289 crashk_res.end = base + size - 1; 290 } 291 } 292 } 293 efi_memmap_res.start = ia64_boot_param->efi_memmap; 294 efi_memmap_res.end = efi_memmap_res.start + 295 ia64_boot_param->efi_memmap_size; 296 boot_param_res.start = __pa(ia64_boot_param); 297 boot_param_res.end = boot_param_res.start + 298 sizeof(*ia64_boot_param); 299 } 300 #endif 301 /* end of memory marker */ 302 rsvd_region[n].start = ~0UL; 303 rsvd_region[n].end = ~0UL; 304 n++; 305 306 num_rsvd_regions = n; 307 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 308 309 sort_regions(rsvd_region, num_rsvd_regions); 310 } 311 312 313 /** 314 * find_initrd - get initrd parameters from the boot parameter structure 315 * 316 * Grab the initrd start and end from the boot parameter struct given us by 317 * the boot loader. 318 */ 319 void __init 320 find_initrd (void) 321 { 322 #ifdef CONFIG_BLK_DEV_INITRD 323 if (ia64_boot_param->initrd_start) { 324 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 325 initrd_end = initrd_start+ia64_boot_param->initrd_size; 326 327 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 328 initrd_start, ia64_boot_param->initrd_size); 329 } 330 #endif 331 } 332 333 static void __init 334 io_port_init (void) 335 { 336 unsigned long phys_iobase; 337 338 /* 339 * Set `iobase' based on the EFI memory map or, failing that, the 340 * value firmware left in ar.k0. 341 * 342 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 343 * the port's virtual address, so ia32_load_state() loads it with a 344 * user virtual address. But in ia64 mode, glibc uses the 345 * *physical* address in ar.k0 to mmap the appropriate area from 346 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 347 * cases, user-mode can only use the legacy 0-64K I/O port space. 348 * 349 * ar.k0 is not involved in kernel I/O port accesses, which can use 350 * any of the I/O port spaces and are done via MMIO using the 351 * virtual mmio_base from the appropriate io_space[]. 352 */ 353 phys_iobase = efi_get_iobase(); 354 if (!phys_iobase) { 355 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 356 printk(KERN_INFO "No I/O port range found in EFI memory map, " 357 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 358 } 359 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 360 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 361 362 /* setup legacy IO port space */ 363 io_space[0].mmio_base = ia64_iobase; 364 io_space[0].sparse = 1; 365 num_io_spaces = 1; 366 } 367 368 /** 369 * early_console_setup - setup debugging console 370 * 371 * Consoles started here require little enough setup that we can start using 372 * them very early in the boot process, either right after the machine 373 * vector initialization, or even before if the drivers can detect their hw. 374 * 375 * Returns non-zero if a console couldn't be setup. 376 */ 377 static inline int __init 378 early_console_setup (char *cmdline) 379 { 380 int earlycons = 0; 381 382 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 383 { 384 extern int sn_serial_console_early_setup(void); 385 if (!sn_serial_console_early_setup()) 386 earlycons++; 387 } 388 #endif 389 #ifdef CONFIG_EFI_PCDP 390 if (!efi_setup_pcdp_console(cmdline)) 391 earlycons++; 392 #endif 393 if (!simcons_register()) 394 earlycons++; 395 396 return (earlycons) ? 0 : -1; 397 } 398 399 static inline void 400 mark_bsp_online (void) 401 { 402 #ifdef CONFIG_SMP 403 /* If we register an early console, allow CPU 0 to printk */ 404 cpu_set(smp_processor_id(), cpu_online_map); 405 #endif 406 } 407 408 #ifdef CONFIG_SMP 409 static void __init 410 check_for_logical_procs (void) 411 { 412 pal_logical_to_physical_t info; 413 s64 status; 414 415 status = ia64_pal_logical_to_phys(0, &info); 416 if (status == -1) { 417 printk(KERN_INFO "No logical to physical processor mapping " 418 "available\n"); 419 return; 420 } 421 if (status) { 422 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 423 status); 424 return; 425 } 426 /* 427 * Total number of siblings that BSP has. Though not all of them 428 * may have booted successfully. The correct number of siblings 429 * booted is in info.overview_num_log. 430 */ 431 smp_num_siblings = info.overview_tpc; 432 smp_num_cpucores = info.overview_cpp; 433 } 434 #endif 435 436 static __initdata int nomca; 437 static __init int setup_nomca(char *s) 438 { 439 nomca = 1; 440 return 0; 441 } 442 early_param("nomca", setup_nomca); 443 444 #ifdef CONFIG_PROC_VMCORE 445 /* elfcorehdr= specifies the location of elf core header 446 * stored by the crashed kernel. 447 */ 448 static int __init parse_elfcorehdr(char *arg) 449 { 450 if (!arg) 451 return -EINVAL; 452 453 elfcorehdr_addr = memparse(arg, &arg); 454 return 0; 455 } 456 early_param("elfcorehdr", parse_elfcorehdr); 457 458 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 459 { 460 unsigned long length; 461 462 /* We get the address using the kernel command line, 463 * but the size is extracted from the EFI tables. 464 * Both address and size are required for reservation 465 * to work properly. 466 */ 467 468 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) 469 return -EINVAL; 470 471 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 472 elfcorehdr_addr = ELFCORE_ADDR_MAX; 473 return -EINVAL; 474 } 475 476 *start = (unsigned long)__va(elfcorehdr_addr); 477 *end = *start + length; 478 return 0; 479 } 480 481 #endif /* CONFIG_PROC_VMCORE */ 482 483 void __init 484 setup_arch (char **cmdline_p) 485 { 486 unw_init(); 487 488 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 489 490 *cmdline_p = __va(ia64_boot_param->command_line); 491 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 492 493 efi_init(); 494 io_port_init(); 495 496 #ifdef CONFIG_IA64_GENERIC 497 /* machvec needs to be parsed from the command line 498 * before parse_early_param() is called to ensure 499 * that ia64_mv is initialised before any command line 500 * settings may cause console setup to occur 501 */ 502 machvec_init_from_cmdline(*cmdline_p); 503 #endif 504 505 parse_early_param(); 506 507 if (early_console_setup(*cmdline_p) == 0) 508 mark_bsp_online(); 509 510 #ifdef CONFIG_ACPI 511 /* Initialize the ACPI boot-time table parser */ 512 acpi_table_init(); 513 # ifdef CONFIG_ACPI_NUMA 514 acpi_numa_init(); 515 # endif 516 #else 517 # ifdef CONFIG_SMP 518 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 519 # endif 520 #endif /* CONFIG_APCI_BOOT */ 521 522 find_memory(); 523 524 /* process SAL system table: */ 525 ia64_sal_init(__va(efi.sal_systab)); 526 527 ia64_setup_printk_clock(); 528 529 #ifdef CONFIG_SMP 530 cpu_physical_id(0) = hard_smp_processor_id(); 531 532 cpu_set(0, cpu_sibling_map[0]); 533 cpu_set(0, cpu_core_map[0]); 534 535 check_for_logical_procs(); 536 if (smp_num_cpucores > 1) 537 printk(KERN_INFO 538 "cpu package is Multi-Core capable: number of cores=%d\n", 539 smp_num_cpucores); 540 if (smp_num_siblings > 1) 541 printk(KERN_INFO 542 "cpu package is Multi-Threading capable: number of siblings=%d\n", 543 smp_num_siblings); 544 #endif 545 546 cpu_init(); /* initialize the bootstrap CPU */ 547 mmu_context_init(); /* initialize context_id bitmap */ 548 549 check_sal_cache_flush(); 550 551 #ifdef CONFIG_ACPI 552 acpi_boot_init(); 553 #endif 554 555 #ifdef CONFIG_VT 556 if (!conswitchp) { 557 # if defined(CONFIG_DUMMY_CONSOLE) 558 conswitchp = &dummy_con; 559 # endif 560 # if defined(CONFIG_VGA_CONSOLE) 561 /* 562 * Non-legacy systems may route legacy VGA MMIO range to system 563 * memory. vga_con probes the MMIO hole, so memory looks like 564 * a VGA device to it. The EFI memory map can tell us if it's 565 * memory so we can avoid this problem. 566 */ 567 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 568 conswitchp = &vga_con; 569 # endif 570 } 571 #endif 572 573 /* enable IA-64 Machine Check Abort Handling unless disabled */ 574 if (!nomca) 575 ia64_mca_init(); 576 577 platform_setup(cmdline_p); 578 paging_init(); 579 } 580 581 /* 582 * Display cpu info for all CPUs. 583 */ 584 static int 585 show_cpuinfo (struct seq_file *m, void *v) 586 { 587 #ifdef CONFIG_SMP 588 # define lpj c->loops_per_jiffy 589 # define cpunum c->cpu 590 #else 591 # define lpj loops_per_jiffy 592 # define cpunum 0 593 #endif 594 static struct { 595 unsigned long mask; 596 const char *feature_name; 597 } feature_bits[] = { 598 { 1UL << 0, "branchlong" }, 599 { 1UL << 1, "spontaneous deferral"}, 600 { 1UL << 2, "16-byte atomic ops" } 601 }; 602 char features[128], *cp, *sep; 603 struct cpuinfo_ia64 *c = v; 604 unsigned long mask; 605 unsigned long proc_freq; 606 int i, size; 607 608 mask = c->features; 609 610 /* build the feature string: */ 611 memcpy(features, "standard", 9); 612 cp = features; 613 size = sizeof(features); 614 sep = ""; 615 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 616 if (mask & feature_bits[i].mask) { 617 cp += snprintf(cp, size, "%s%s", sep, 618 feature_bits[i].feature_name), 619 sep = ", "; 620 mask &= ~feature_bits[i].mask; 621 size = sizeof(features) - (cp - features); 622 } 623 } 624 if (mask && size > 1) { 625 /* print unknown features as a hex value */ 626 snprintf(cp, size, "%s0x%lx", sep, mask); 627 } 628 629 proc_freq = cpufreq_quick_get(cpunum); 630 if (!proc_freq) 631 proc_freq = c->proc_freq / 1000; 632 633 seq_printf(m, 634 "processor : %d\n" 635 "vendor : %s\n" 636 "arch : IA-64\n" 637 "family : %u\n" 638 "model : %u\n" 639 "model name : %s\n" 640 "revision : %u\n" 641 "archrev : %u\n" 642 "features : %s\n" 643 "cpu number : %lu\n" 644 "cpu regs : %u\n" 645 "cpu MHz : %lu.%03lu\n" 646 "itc MHz : %lu.%06lu\n" 647 "BogoMIPS : %lu.%02lu\n", 648 cpunum, c->vendor, c->family, c->model, 649 c->model_name, c->revision, c->archrev, 650 features, c->ppn, c->number, 651 proc_freq / 1000, proc_freq % 1000, 652 c->itc_freq / 1000000, c->itc_freq % 1000000, 653 lpj*HZ/500000, (lpj*HZ/5000) % 100); 654 #ifdef CONFIG_SMP 655 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 656 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 657 seq_printf(m, 658 "physical id: %u\n" 659 "core id : %u\n" 660 "thread id : %u\n", 661 c->socket_id, c->core_id, c->thread_id); 662 #endif 663 seq_printf(m,"\n"); 664 665 return 0; 666 } 667 668 static void * 669 c_start (struct seq_file *m, loff_t *pos) 670 { 671 #ifdef CONFIG_SMP 672 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 673 ++*pos; 674 #endif 675 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 676 } 677 678 static void * 679 c_next (struct seq_file *m, void *v, loff_t *pos) 680 { 681 ++*pos; 682 return c_start(m, pos); 683 } 684 685 static void 686 c_stop (struct seq_file *m, void *v) 687 { 688 } 689 690 struct seq_operations cpuinfo_op = { 691 .start = c_start, 692 .next = c_next, 693 .stop = c_stop, 694 .show = show_cpuinfo 695 }; 696 697 #define MAX_BRANDS 8 698 static char brandname[MAX_BRANDS][128]; 699 700 static char * __cpuinit 701 get_model_name(__u8 family, __u8 model) 702 { 703 static int overflow; 704 char brand[128]; 705 int i; 706 707 memcpy(brand, "Unknown", 8); 708 if (ia64_pal_get_brand_info(brand)) { 709 if (family == 0x7) 710 memcpy(brand, "Merced", 7); 711 else if (family == 0x1f) switch (model) { 712 case 0: memcpy(brand, "McKinley", 9); break; 713 case 1: memcpy(brand, "Madison", 8); break; 714 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 715 } 716 } 717 for (i = 0; i < MAX_BRANDS; i++) 718 if (strcmp(brandname[i], brand) == 0) 719 return brandname[i]; 720 for (i = 0; i < MAX_BRANDS; i++) 721 if (brandname[i][0] == '\0') 722 return strcpy(brandname[i], brand); 723 if (overflow++ == 0) 724 printk(KERN_ERR 725 "%s: Table overflow. Some processor model information will be missing\n", 726 __FUNCTION__); 727 return "Unknown"; 728 } 729 730 static void __cpuinit 731 identify_cpu (struct cpuinfo_ia64 *c) 732 { 733 union { 734 unsigned long bits[5]; 735 struct { 736 /* id 0 & 1: */ 737 char vendor[16]; 738 739 /* id 2 */ 740 u64 ppn; /* processor serial number */ 741 742 /* id 3: */ 743 unsigned number : 8; 744 unsigned revision : 8; 745 unsigned model : 8; 746 unsigned family : 8; 747 unsigned archrev : 8; 748 unsigned reserved : 24; 749 750 /* id 4: */ 751 u64 features; 752 } field; 753 } cpuid; 754 pal_vm_info_1_u_t vm1; 755 pal_vm_info_2_u_t vm2; 756 pal_status_t status; 757 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 758 int i; 759 for (i = 0; i < 5; ++i) 760 cpuid.bits[i] = ia64_get_cpuid(i); 761 762 memcpy(c->vendor, cpuid.field.vendor, 16); 763 #ifdef CONFIG_SMP 764 c->cpu = smp_processor_id(); 765 766 /* below default values will be overwritten by identify_siblings() 767 * for Multi-Threading/Multi-Core capable CPUs 768 */ 769 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 770 c->socket_id = -1; 771 772 identify_siblings(c); 773 #endif 774 c->ppn = cpuid.field.ppn; 775 c->number = cpuid.field.number; 776 c->revision = cpuid.field.revision; 777 c->model = cpuid.field.model; 778 c->family = cpuid.field.family; 779 c->archrev = cpuid.field.archrev; 780 c->features = cpuid.field.features; 781 c->model_name = get_model_name(c->family, c->model); 782 783 status = ia64_pal_vm_summary(&vm1, &vm2); 784 if (status == PAL_STATUS_SUCCESS) { 785 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 786 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 787 } 788 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 789 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 790 } 791 792 void __init 793 setup_per_cpu_areas (void) 794 { 795 /* start_kernel() requires this... */ 796 #ifdef CONFIG_ACPI_HOTPLUG_CPU 797 prefill_possible_map(); 798 #endif 799 } 800 801 /* 802 * Calculate the max. cache line size. 803 * 804 * In addition, the minimum of the i-cache stride sizes is calculated for 805 * "flush_icache_range()". 806 */ 807 static void __cpuinit 808 get_max_cacheline_size (void) 809 { 810 unsigned long line_size, max = 1; 811 u64 l, levels, unique_caches; 812 pal_cache_config_info_t cci; 813 s64 status; 814 815 status = ia64_pal_cache_summary(&levels, &unique_caches); 816 if (status != 0) { 817 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 818 __FUNCTION__, status); 819 max = SMP_CACHE_BYTES; 820 /* Safest setup for "flush_icache_range()" */ 821 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 822 goto out; 823 } 824 825 for (l = 0; l < levels; ++l) { 826 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 827 &cci); 828 if (status != 0) { 829 printk(KERN_ERR 830 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 831 __FUNCTION__, l, status); 832 max = SMP_CACHE_BYTES; 833 /* The safest setup for "flush_icache_range()" */ 834 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 835 cci.pcci_unified = 1; 836 } 837 line_size = 1 << cci.pcci_line_size; 838 if (line_size > max) 839 max = line_size; 840 if (!cci.pcci_unified) { 841 status = ia64_pal_cache_config_info(l, 842 /* cache_type (instruction)= */ 1, 843 &cci); 844 if (status != 0) { 845 printk(KERN_ERR 846 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 847 __FUNCTION__, l, status); 848 /* The safest setup for "flush_icache_range()" */ 849 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 850 } 851 } 852 if (cci.pcci_stride < ia64_i_cache_stride_shift) 853 ia64_i_cache_stride_shift = cci.pcci_stride; 854 } 855 out: 856 if (max > ia64_max_cacheline_size) 857 ia64_max_cacheline_size = max; 858 } 859 860 /* 861 * cpu_init() initializes state that is per-CPU. This function acts 862 * as a 'CPU state barrier', nothing should get across. 863 */ 864 void __cpuinit 865 cpu_init (void) 866 { 867 extern void __cpuinit ia64_mmu_init (void *); 868 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 869 unsigned long num_phys_stacked; 870 pal_vm_info_2_u_t vmi; 871 unsigned int max_ctx; 872 struct cpuinfo_ia64 *cpu_info; 873 void *cpu_data; 874 875 cpu_data = per_cpu_init(); 876 877 /* 878 * We set ar.k3 so that assembly code in MCA handler can compute 879 * physical addresses of per cpu variables with a simple: 880 * phys = ar.k3 + &per_cpu_var 881 */ 882 ia64_set_kr(IA64_KR_PER_CPU_DATA, 883 ia64_tpa(cpu_data) - (long) __per_cpu_start); 884 885 get_max_cacheline_size(); 886 887 /* 888 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 889 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 890 * depends on the data returned by identify_cpu(). We break the dependency by 891 * accessing cpu_data() through the canonical per-CPU address. 892 */ 893 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 894 identify_cpu(cpu_info); 895 896 #ifdef CONFIG_MCKINLEY 897 { 898 # define FEATURE_SET 16 899 struct ia64_pal_retval iprv; 900 901 if (cpu_info->family == 0x1f) { 902 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 903 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 904 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 905 (iprv.v1 | 0x80), FEATURE_SET, 0); 906 } 907 } 908 #endif 909 910 /* Clear the stack memory reserved for pt_regs: */ 911 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 912 913 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 914 915 /* 916 * Initialize the page-table base register to a global 917 * directory with all zeroes. This ensure that we can handle 918 * TLB-misses to user address-space even before we created the 919 * first user address-space. This may happen, e.g., due to 920 * aggressive use of lfetch.fault. 921 */ 922 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 923 924 /* 925 * Initialize default control register to defer speculative faults except 926 * for those arising from TLB misses, which are not deferred. The 927 * kernel MUST NOT depend on a particular setting of these bits (in other words, 928 * the kernel must have recovery code for all speculative accesses). Turn on 929 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 930 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 931 * be fine). 932 */ 933 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 934 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 935 atomic_inc(&init_mm.mm_count); 936 current->active_mm = &init_mm; 937 if (current->mm) 938 BUG(); 939 940 ia64_mmu_init(ia64_imva(cpu_data)); 941 ia64_mca_cpu_init(ia64_imva(cpu_data)); 942 943 #ifdef CONFIG_IA32_SUPPORT 944 ia32_cpu_init(); 945 #endif 946 947 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 948 ia64_set_itc(0); 949 950 /* disable all local interrupt sources: */ 951 ia64_set_itv(1 << 16); 952 ia64_set_lrr0(1 << 16); 953 ia64_set_lrr1(1 << 16); 954 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 955 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 956 957 /* clear TPR & XTP to enable all interrupt classes: */ 958 ia64_setreg(_IA64_REG_CR_TPR, 0); 959 960 /* Clear any pending interrupts left by SAL/EFI */ 961 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 962 ia64_eoi(); 963 964 #ifdef CONFIG_SMP 965 normal_xtp(); 966 #endif 967 968 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 969 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 970 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 971 else { 972 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 973 max_ctx = (1U << 15) - 1; /* use architected minimum */ 974 } 975 while (max_ctx < ia64_ctx.max_ctx) { 976 unsigned int old = ia64_ctx.max_ctx; 977 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 978 break; 979 } 980 981 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 982 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 983 "stacked regs\n"); 984 num_phys_stacked = 96; 985 } 986 /* size of physical stacked register partition plus 8 bytes: */ 987 if (num_phys_stacked > max_num_phys_stacked) { 988 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 989 max_num_phys_stacked = num_phys_stacked; 990 } 991 platform_cpu_init(); 992 pm_idle = default_idle; 993 } 994 995 void __init 996 check_bugs (void) 997 { 998 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 999 (unsigned long) __end___mckinley_e9_bundles); 1000 } 1001 1002 static int __init run_dmi_scan(void) 1003 { 1004 dmi_scan_machine(); 1005 return 0; 1006 } 1007 core_initcall(run_dmi_scan); 1008