1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/paravirt.h> 55 #include <asm/paravirt_patch.h> 56 #include <asm/patch.h> 57 #include <asm/pgtable.h> 58 #include <asm/processor.h> 59 #include <asm/sal.h> 60 #include <asm/sections.h> 61 #include <asm/setup.h> 62 #include <asm/smp.h> 63 #include <asm/system.h> 64 #include <asm/tlbflush.h> 65 #include <asm/unistd.h> 66 #include <asm/hpsim.h> 67 68 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 69 # error "struct cpuinfo_ia64 too big!" 70 #endif 71 72 #ifdef CONFIG_SMP 73 unsigned long __per_cpu_offset[NR_CPUS]; 74 EXPORT_SYMBOL(__per_cpu_offset); 75 #endif 76 77 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 78 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 79 unsigned long ia64_cycles_per_usec; 80 struct ia64_boot_param *ia64_boot_param; 81 struct screen_info screen_info; 82 unsigned long vga_console_iobase; 83 unsigned long vga_console_membase; 84 85 static struct resource data_resource = { 86 .name = "Kernel data", 87 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 88 }; 89 90 static struct resource code_resource = { 91 .name = "Kernel code", 92 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 93 }; 94 95 static struct resource bss_resource = { 96 .name = "Kernel bss", 97 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 98 }; 99 100 unsigned long ia64_max_cacheline_size; 101 102 int dma_get_cache_alignment(void) 103 { 104 return ia64_max_cacheline_size; 105 } 106 EXPORT_SYMBOL(dma_get_cache_alignment); 107 108 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 109 EXPORT_SYMBOL(ia64_iobase); 110 struct io_space io_space[MAX_IO_SPACES]; 111 EXPORT_SYMBOL(io_space); 112 unsigned int num_io_spaces; 113 114 /* 115 * "flush_icache_range()" needs to know what processor dependent stride size to use 116 * when it makes i-cache(s) coherent with d-caches. 117 */ 118 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 119 unsigned long ia64_i_cache_stride_shift = ~0; 120 /* 121 * "clflush_cache_range()" needs to know what processor dependent stride size to 122 * use when it flushes cache lines including both d-cache and i-cache. 123 */ 124 /* Safest way to go: 32 bytes by 32 bytes */ 125 #define CACHE_STRIDE_SHIFT 5 126 unsigned long ia64_cache_stride_shift = ~0; 127 128 /* 129 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 130 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 131 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 132 * address of the second buffer must be aligned to (merge_mask+1) in order to be 133 * mergeable). By default, we assume there is no I/O MMU which can merge physically 134 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 135 * page-size of 2^64. 136 */ 137 unsigned long ia64_max_iommu_merge_mask = ~0UL; 138 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 139 140 /* 141 * We use a special marker for the end of memory and it uses the extra (+1) slot 142 */ 143 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 144 int num_rsvd_regions __initdata; 145 146 147 /* 148 * Filter incoming memory segments based on the primitive map created from the boot 149 * parameters. Segments contained in the map are removed from the memory ranges. A 150 * caller-specified function is called with the memory ranges that remain after filtering. 151 * This routine does not assume the incoming segments are sorted. 152 */ 153 int __init 154 filter_rsvd_memory (u64 start, u64 end, void *arg) 155 { 156 u64 range_start, range_end, prev_start; 157 void (*func)(unsigned long, unsigned long, int); 158 int i; 159 160 #if IGNORE_PFN0 161 if (start == PAGE_OFFSET) { 162 printk(KERN_WARNING "warning: skipping physical page 0\n"); 163 start += PAGE_SIZE; 164 if (start >= end) return 0; 165 } 166 #endif 167 /* 168 * lowest possible address(walker uses virtual) 169 */ 170 prev_start = PAGE_OFFSET; 171 func = arg; 172 173 for (i = 0; i < num_rsvd_regions; ++i) { 174 range_start = max(start, prev_start); 175 range_end = min(end, rsvd_region[i].start); 176 177 if (range_start < range_end) 178 call_pernode_memory(__pa(range_start), range_end - range_start, func); 179 180 /* nothing more available in this segment */ 181 if (range_end == end) return 0; 182 183 prev_start = rsvd_region[i].end; 184 } 185 /* end of memory marker allows full processing inside loop body */ 186 return 0; 187 } 188 189 /* 190 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 191 * are not filtered out. 192 */ 193 int __init 194 filter_memory(u64 start, u64 end, void *arg) 195 { 196 void (*func)(unsigned long, unsigned long, int); 197 198 #if IGNORE_PFN0 199 if (start == PAGE_OFFSET) { 200 printk(KERN_WARNING "warning: skipping physical page 0\n"); 201 start += PAGE_SIZE; 202 if (start >= end) 203 return 0; 204 } 205 #endif 206 func = arg; 207 if (start < end) 208 call_pernode_memory(__pa(start), end - start, func); 209 return 0; 210 } 211 212 static void __init 213 sort_regions (struct rsvd_region *rsvd_region, int max) 214 { 215 int j; 216 217 /* simple bubble sorting */ 218 while (max--) { 219 for (j = 0; j < max; ++j) { 220 if (rsvd_region[j].start > rsvd_region[j+1].start) { 221 struct rsvd_region tmp; 222 tmp = rsvd_region[j]; 223 rsvd_region[j] = rsvd_region[j + 1]; 224 rsvd_region[j + 1] = tmp; 225 } 226 } 227 } 228 } 229 230 /* 231 * Request address space for all standard resources 232 */ 233 static int __init register_memory(void) 234 { 235 code_resource.start = ia64_tpa(_text); 236 code_resource.end = ia64_tpa(_etext) - 1; 237 data_resource.start = ia64_tpa(_etext); 238 data_resource.end = ia64_tpa(_edata) - 1; 239 bss_resource.start = ia64_tpa(__bss_start); 240 bss_resource.end = ia64_tpa(_end) - 1; 241 efi_initialize_iomem_resources(&code_resource, &data_resource, 242 &bss_resource); 243 244 return 0; 245 } 246 247 __initcall(register_memory); 248 249 250 #ifdef CONFIG_KEXEC 251 252 /* 253 * This function checks if the reserved crashkernel is allowed on the specific 254 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 255 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 256 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 257 * in kdump case. See the comment in sba_init() in sba_iommu.c. 258 * 259 * So, the only machvec that really supports loading the kdump kernel 260 * over 4 GB is "sn2". 261 */ 262 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 263 { 264 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 265 return 1; 266 else 267 return pbase < (1UL << 32); 268 } 269 270 static void __init setup_crashkernel(unsigned long total, int *n) 271 { 272 unsigned long long base = 0, size = 0; 273 int ret; 274 275 ret = parse_crashkernel(boot_command_line, total, 276 &size, &base); 277 if (ret == 0 && size > 0) { 278 if (!base) { 279 sort_regions(rsvd_region, *n); 280 base = kdump_find_rsvd_region(size, 281 rsvd_region, *n); 282 } 283 284 if (!check_crashkernel_memory(base, size)) { 285 pr_warning("crashkernel: There would be kdump memory " 286 "at %ld GB but this is unusable because it " 287 "must\nbe below 4 GB. Change the memory " 288 "configuration of the machine.\n", 289 (unsigned long)(base >> 30)); 290 return; 291 } 292 293 if (base != ~0UL) { 294 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 295 "for crashkernel (System RAM: %ldMB)\n", 296 (unsigned long)(size >> 20), 297 (unsigned long)(base >> 20), 298 (unsigned long)(total >> 20)); 299 rsvd_region[*n].start = 300 (unsigned long)__va(base); 301 rsvd_region[*n].end = 302 (unsigned long)__va(base + size); 303 (*n)++; 304 crashk_res.start = base; 305 crashk_res.end = base + size - 1; 306 } 307 } 308 efi_memmap_res.start = ia64_boot_param->efi_memmap; 309 efi_memmap_res.end = efi_memmap_res.start + 310 ia64_boot_param->efi_memmap_size; 311 boot_param_res.start = __pa(ia64_boot_param); 312 boot_param_res.end = boot_param_res.start + 313 sizeof(*ia64_boot_param); 314 } 315 #else 316 static inline void __init setup_crashkernel(unsigned long total, int *n) 317 {} 318 #endif 319 320 /** 321 * reserve_memory - setup reserved memory areas 322 * 323 * Setup the reserved memory areas set aside for the boot parameters, 324 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 325 * see arch/ia64/include/asm/meminit.h if you need to define more. 326 */ 327 void __init 328 reserve_memory (void) 329 { 330 int n = 0; 331 unsigned long total_memory; 332 333 /* 334 * none of the entries in this table overlap 335 */ 336 rsvd_region[n].start = (unsigned long) ia64_boot_param; 337 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 338 n++; 339 340 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 341 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 342 n++; 343 344 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 345 rsvd_region[n].end = (rsvd_region[n].start 346 + strlen(__va(ia64_boot_param->command_line)) + 1); 347 n++; 348 349 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 350 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 351 n++; 352 353 n += paravirt_reserve_memory(&rsvd_region[n]); 354 355 #ifdef CONFIG_BLK_DEV_INITRD 356 if (ia64_boot_param->initrd_start) { 357 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 358 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 359 n++; 360 } 361 #endif 362 363 #ifdef CONFIG_CRASH_DUMP 364 if (reserve_elfcorehdr(&rsvd_region[n].start, 365 &rsvd_region[n].end) == 0) 366 n++; 367 #endif 368 369 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 370 n++; 371 372 setup_crashkernel(total_memory, &n); 373 374 /* end of memory marker */ 375 rsvd_region[n].start = ~0UL; 376 rsvd_region[n].end = ~0UL; 377 n++; 378 379 num_rsvd_regions = n; 380 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 381 382 sort_regions(rsvd_region, num_rsvd_regions); 383 } 384 385 386 /** 387 * find_initrd - get initrd parameters from the boot parameter structure 388 * 389 * Grab the initrd start and end from the boot parameter struct given us by 390 * the boot loader. 391 */ 392 void __init 393 find_initrd (void) 394 { 395 #ifdef CONFIG_BLK_DEV_INITRD 396 if (ia64_boot_param->initrd_start) { 397 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 398 initrd_end = initrd_start+ia64_boot_param->initrd_size; 399 400 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 401 initrd_start, ia64_boot_param->initrd_size); 402 } 403 #endif 404 } 405 406 static void __init 407 io_port_init (void) 408 { 409 unsigned long phys_iobase; 410 411 /* 412 * Set `iobase' based on the EFI memory map or, failing that, the 413 * value firmware left in ar.k0. 414 * 415 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 416 * the port's virtual address, so ia32_load_state() loads it with a 417 * user virtual address. But in ia64 mode, glibc uses the 418 * *physical* address in ar.k0 to mmap the appropriate area from 419 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 420 * cases, user-mode can only use the legacy 0-64K I/O port space. 421 * 422 * ar.k0 is not involved in kernel I/O port accesses, which can use 423 * any of the I/O port spaces and are done via MMIO using the 424 * virtual mmio_base from the appropriate io_space[]. 425 */ 426 phys_iobase = efi_get_iobase(); 427 if (!phys_iobase) { 428 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 429 printk(KERN_INFO "No I/O port range found in EFI memory map, " 430 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 431 } 432 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 433 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 434 435 /* setup legacy IO port space */ 436 io_space[0].mmio_base = ia64_iobase; 437 io_space[0].sparse = 1; 438 num_io_spaces = 1; 439 } 440 441 /** 442 * early_console_setup - setup debugging console 443 * 444 * Consoles started here require little enough setup that we can start using 445 * them very early in the boot process, either right after the machine 446 * vector initialization, or even before if the drivers can detect their hw. 447 * 448 * Returns non-zero if a console couldn't be setup. 449 */ 450 static inline int __init 451 early_console_setup (char *cmdline) 452 { 453 int earlycons = 0; 454 455 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 456 { 457 extern int sn_serial_console_early_setup(void); 458 if (!sn_serial_console_early_setup()) 459 earlycons++; 460 } 461 #endif 462 #ifdef CONFIG_EFI_PCDP 463 if (!efi_setup_pcdp_console(cmdline)) 464 earlycons++; 465 #endif 466 if (!simcons_register()) 467 earlycons++; 468 469 return (earlycons) ? 0 : -1; 470 } 471 472 static inline void 473 mark_bsp_online (void) 474 { 475 #ifdef CONFIG_SMP 476 /* If we register an early console, allow CPU 0 to printk */ 477 cpu_set(smp_processor_id(), cpu_online_map); 478 #endif 479 } 480 481 static __initdata int nomca; 482 static __init int setup_nomca(char *s) 483 { 484 nomca = 1; 485 return 0; 486 } 487 early_param("nomca", setup_nomca); 488 489 /* 490 * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by 491 * is_kdump_kernel() to determine if we are booting after a panic. Hence 492 * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. 493 */ 494 #ifdef CONFIG_CRASH_DUMP 495 /* elfcorehdr= specifies the location of elf core header 496 * stored by the crashed kernel. 497 */ 498 static int __init parse_elfcorehdr(char *arg) 499 { 500 if (!arg) 501 return -EINVAL; 502 503 elfcorehdr_addr = memparse(arg, &arg); 504 return 0; 505 } 506 early_param("elfcorehdr", parse_elfcorehdr); 507 508 int __init reserve_elfcorehdr(u64 *start, u64 *end) 509 { 510 u64 length; 511 512 /* We get the address using the kernel command line, 513 * but the size is extracted from the EFI tables. 514 * Both address and size are required for reservation 515 * to work properly. 516 */ 517 518 if (!is_vmcore_usable()) 519 return -EINVAL; 520 521 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 522 vmcore_unusable(); 523 return -EINVAL; 524 } 525 526 *start = (unsigned long)__va(elfcorehdr_addr); 527 *end = *start + length; 528 return 0; 529 } 530 531 #endif /* CONFIG_PROC_VMCORE */ 532 533 void __init 534 setup_arch (char **cmdline_p) 535 { 536 unw_init(); 537 538 paravirt_arch_setup_early(); 539 540 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 541 paravirt_patch_apply(); 542 543 *cmdline_p = __va(ia64_boot_param->command_line); 544 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 545 546 efi_init(); 547 io_port_init(); 548 549 #ifdef CONFIG_IA64_GENERIC 550 /* machvec needs to be parsed from the command line 551 * before parse_early_param() is called to ensure 552 * that ia64_mv is initialised before any command line 553 * settings may cause console setup to occur 554 */ 555 machvec_init_from_cmdline(*cmdline_p); 556 #endif 557 558 parse_early_param(); 559 560 if (early_console_setup(*cmdline_p) == 0) 561 mark_bsp_online(); 562 563 #ifdef CONFIG_ACPI 564 /* Initialize the ACPI boot-time table parser */ 565 acpi_table_init(); 566 early_acpi_boot_init(); 567 # ifdef CONFIG_ACPI_NUMA 568 acpi_numa_init(); 569 # ifdef CONFIG_ACPI_HOTPLUG_CPU 570 prefill_possible_map(); 571 # endif 572 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? 573 32 : cpus_weight(early_cpu_possible_map)), 574 additional_cpus > 0 ? additional_cpus : 0); 575 # endif 576 #endif /* CONFIG_APCI_BOOT */ 577 578 #ifdef CONFIG_SMP 579 smp_build_cpu_map(); 580 #endif 581 find_memory(); 582 583 /* process SAL system table: */ 584 ia64_sal_init(__va(efi.sal_systab)); 585 586 #ifdef CONFIG_ITANIUM 587 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 588 #else 589 { 590 unsigned long num_phys_stacked; 591 592 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 593 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 594 } 595 #endif 596 597 #ifdef CONFIG_SMP 598 cpu_physical_id(0) = hard_smp_processor_id(); 599 #endif 600 601 cpu_init(); /* initialize the bootstrap CPU */ 602 mmu_context_init(); /* initialize context_id bitmap */ 603 604 #ifdef CONFIG_ACPI 605 acpi_boot_init(); 606 #endif 607 608 paravirt_banner(); 609 paravirt_arch_setup_console(cmdline_p); 610 611 #ifdef CONFIG_VT 612 if (!conswitchp) { 613 # if defined(CONFIG_DUMMY_CONSOLE) 614 conswitchp = &dummy_con; 615 # endif 616 # if defined(CONFIG_VGA_CONSOLE) 617 /* 618 * Non-legacy systems may route legacy VGA MMIO range to system 619 * memory. vga_con probes the MMIO hole, so memory looks like 620 * a VGA device to it. The EFI memory map can tell us if it's 621 * memory so we can avoid this problem. 622 */ 623 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 624 conswitchp = &vga_con; 625 # endif 626 } 627 #endif 628 629 /* enable IA-64 Machine Check Abort Handling unless disabled */ 630 if (paravirt_arch_setup_nomca()) 631 nomca = 1; 632 if (!nomca) 633 ia64_mca_init(); 634 635 platform_setup(cmdline_p); 636 #ifndef CONFIG_IA64_HP_SIM 637 check_sal_cache_flush(); 638 #endif 639 paging_init(); 640 } 641 642 /* 643 * Display cpu info for all CPUs. 644 */ 645 static int 646 show_cpuinfo (struct seq_file *m, void *v) 647 { 648 #ifdef CONFIG_SMP 649 # define lpj c->loops_per_jiffy 650 # define cpunum c->cpu 651 #else 652 # define lpj loops_per_jiffy 653 # define cpunum 0 654 #endif 655 static struct { 656 unsigned long mask; 657 const char *feature_name; 658 } feature_bits[] = { 659 { 1UL << 0, "branchlong" }, 660 { 1UL << 1, "spontaneous deferral"}, 661 { 1UL << 2, "16-byte atomic ops" } 662 }; 663 char features[128], *cp, *sep; 664 struct cpuinfo_ia64 *c = v; 665 unsigned long mask; 666 unsigned long proc_freq; 667 int i, size; 668 669 mask = c->features; 670 671 /* build the feature string: */ 672 memcpy(features, "standard", 9); 673 cp = features; 674 size = sizeof(features); 675 sep = ""; 676 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 677 if (mask & feature_bits[i].mask) { 678 cp += snprintf(cp, size, "%s%s", sep, 679 feature_bits[i].feature_name), 680 sep = ", "; 681 mask &= ~feature_bits[i].mask; 682 size = sizeof(features) - (cp - features); 683 } 684 } 685 if (mask && size > 1) { 686 /* print unknown features as a hex value */ 687 snprintf(cp, size, "%s0x%lx", sep, mask); 688 } 689 690 proc_freq = cpufreq_quick_get(cpunum); 691 if (!proc_freq) 692 proc_freq = c->proc_freq / 1000; 693 694 seq_printf(m, 695 "processor : %d\n" 696 "vendor : %s\n" 697 "arch : IA-64\n" 698 "family : %u\n" 699 "model : %u\n" 700 "model name : %s\n" 701 "revision : %u\n" 702 "archrev : %u\n" 703 "features : %s\n" 704 "cpu number : %lu\n" 705 "cpu regs : %u\n" 706 "cpu MHz : %lu.%03lu\n" 707 "itc MHz : %lu.%06lu\n" 708 "BogoMIPS : %lu.%02lu\n", 709 cpunum, c->vendor, c->family, c->model, 710 c->model_name, c->revision, c->archrev, 711 features, c->ppn, c->number, 712 proc_freq / 1000, proc_freq % 1000, 713 c->itc_freq / 1000000, c->itc_freq % 1000000, 714 lpj*HZ/500000, (lpj*HZ/5000) % 100); 715 #ifdef CONFIG_SMP 716 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 717 if (c->socket_id != -1) 718 seq_printf(m, "physical id: %u\n", c->socket_id); 719 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 720 seq_printf(m, 721 "core id : %u\n" 722 "thread id : %u\n", 723 c->core_id, c->thread_id); 724 #endif 725 seq_printf(m,"\n"); 726 727 return 0; 728 } 729 730 static void * 731 c_start (struct seq_file *m, loff_t *pos) 732 { 733 #ifdef CONFIG_SMP 734 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 735 ++*pos; 736 #endif 737 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 738 } 739 740 static void * 741 c_next (struct seq_file *m, void *v, loff_t *pos) 742 { 743 ++*pos; 744 return c_start(m, pos); 745 } 746 747 static void 748 c_stop (struct seq_file *m, void *v) 749 { 750 } 751 752 const struct seq_operations cpuinfo_op = { 753 .start = c_start, 754 .next = c_next, 755 .stop = c_stop, 756 .show = show_cpuinfo 757 }; 758 759 #define MAX_BRANDS 8 760 static char brandname[MAX_BRANDS][128]; 761 762 static char * __cpuinit 763 get_model_name(__u8 family, __u8 model) 764 { 765 static int overflow; 766 char brand[128]; 767 int i; 768 769 memcpy(brand, "Unknown", 8); 770 if (ia64_pal_get_brand_info(brand)) { 771 if (family == 0x7) 772 memcpy(brand, "Merced", 7); 773 else if (family == 0x1f) switch (model) { 774 case 0: memcpy(brand, "McKinley", 9); break; 775 case 1: memcpy(brand, "Madison", 8); break; 776 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 777 } 778 } 779 for (i = 0; i < MAX_BRANDS; i++) 780 if (strcmp(brandname[i], brand) == 0) 781 return brandname[i]; 782 for (i = 0; i < MAX_BRANDS; i++) 783 if (brandname[i][0] == '\0') 784 return strcpy(brandname[i], brand); 785 if (overflow++ == 0) 786 printk(KERN_ERR 787 "%s: Table overflow. Some processor model information will be missing\n", 788 __func__); 789 return "Unknown"; 790 } 791 792 static void __cpuinit 793 identify_cpu (struct cpuinfo_ia64 *c) 794 { 795 union { 796 unsigned long bits[5]; 797 struct { 798 /* id 0 & 1: */ 799 char vendor[16]; 800 801 /* id 2 */ 802 u64 ppn; /* processor serial number */ 803 804 /* id 3: */ 805 unsigned number : 8; 806 unsigned revision : 8; 807 unsigned model : 8; 808 unsigned family : 8; 809 unsigned archrev : 8; 810 unsigned reserved : 24; 811 812 /* id 4: */ 813 u64 features; 814 } field; 815 } cpuid; 816 pal_vm_info_1_u_t vm1; 817 pal_vm_info_2_u_t vm2; 818 pal_status_t status; 819 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 820 int i; 821 for (i = 0; i < 5; ++i) 822 cpuid.bits[i] = ia64_get_cpuid(i); 823 824 memcpy(c->vendor, cpuid.field.vendor, 16); 825 #ifdef CONFIG_SMP 826 c->cpu = smp_processor_id(); 827 828 /* below default values will be overwritten by identify_siblings() 829 * for Multi-Threading/Multi-Core capable CPUs 830 */ 831 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 832 c->socket_id = -1; 833 834 identify_siblings(c); 835 836 if (c->threads_per_core > smp_num_siblings) 837 smp_num_siblings = c->threads_per_core; 838 #endif 839 c->ppn = cpuid.field.ppn; 840 c->number = cpuid.field.number; 841 c->revision = cpuid.field.revision; 842 c->model = cpuid.field.model; 843 c->family = cpuid.field.family; 844 c->archrev = cpuid.field.archrev; 845 c->features = cpuid.field.features; 846 c->model_name = get_model_name(c->family, c->model); 847 848 status = ia64_pal_vm_summary(&vm1, &vm2); 849 if (status == PAL_STATUS_SUCCESS) { 850 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 851 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 852 } 853 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 854 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 855 } 856 857 /* 858 * Do the following calculations: 859 * 860 * 1. the max. cache line size. 861 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 862 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 863 */ 864 static void __cpuinit 865 get_cache_info(void) 866 { 867 unsigned long line_size, max = 1; 868 unsigned long l, levels, unique_caches; 869 pal_cache_config_info_t cci; 870 long status; 871 872 status = ia64_pal_cache_summary(&levels, &unique_caches); 873 if (status != 0) { 874 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 875 __func__, status); 876 max = SMP_CACHE_BYTES; 877 /* Safest setup for "flush_icache_range()" */ 878 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 879 /* Safest setup for "clflush_cache_range()" */ 880 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 881 goto out; 882 } 883 884 for (l = 0; l < levels; ++l) { 885 /* cache_type (data_or_unified)=2 */ 886 status = ia64_pal_cache_config_info(l, 2, &cci); 887 if (status != 0) { 888 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 889 "(l=%lu, 2) failed (status=%ld)\n", 890 __func__, l, status); 891 max = SMP_CACHE_BYTES; 892 /* The safest setup for "flush_icache_range()" */ 893 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 894 /* The safest setup for "clflush_cache_range()" */ 895 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 896 cci.pcci_unified = 1; 897 } else { 898 if (cci.pcci_stride < ia64_cache_stride_shift) 899 ia64_cache_stride_shift = cci.pcci_stride; 900 901 line_size = 1 << cci.pcci_line_size; 902 if (line_size > max) 903 max = line_size; 904 } 905 906 if (!cci.pcci_unified) { 907 /* cache_type (instruction)=1*/ 908 status = ia64_pal_cache_config_info(l, 1, &cci); 909 if (status != 0) { 910 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 911 "(l=%lu, 1) failed (status=%ld)\n", 912 __func__, l, status); 913 /* The safest setup for flush_icache_range() */ 914 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 915 } 916 } 917 if (cci.pcci_stride < ia64_i_cache_stride_shift) 918 ia64_i_cache_stride_shift = cci.pcci_stride; 919 } 920 out: 921 if (max > ia64_max_cacheline_size) 922 ia64_max_cacheline_size = max; 923 } 924 925 /* 926 * cpu_init() initializes state that is per-CPU. This function acts 927 * as a 'CPU state barrier', nothing should get across. 928 */ 929 void __cpuinit 930 cpu_init (void) 931 { 932 extern void __cpuinit ia64_mmu_init (void *); 933 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 934 unsigned long num_phys_stacked; 935 pal_vm_info_2_u_t vmi; 936 unsigned int max_ctx; 937 struct cpuinfo_ia64 *cpu_info; 938 void *cpu_data; 939 940 cpu_data = per_cpu_init(); 941 #ifdef CONFIG_SMP 942 /* 943 * insert boot cpu into sibling and core mapes 944 * (must be done after per_cpu area is setup) 945 */ 946 if (smp_processor_id() == 0) { 947 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 948 cpu_set(0, cpu_core_map[0]); 949 } else { 950 /* 951 * Set ar.k3 so that assembly code in MCA handler can compute 952 * physical addresses of per cpu variables with a simple: 953 * phys = ar.k3 + &per_cpu_var 954 * and the alt-dtlb-miss handler can set per-cpu mapping into 955 * the TLB when needed. head.S already did this for cpu0. 956 */ 957 ia64_set_kr(IA64_KR_PER_CPU_DATA, 958 ia64_tpa(cpu_data) - (long) __per_cpu_start); 959 } 960 #endif 961 962 get_cache_info(); 963 964 /* 965 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 966 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 967 * depends on the data returned by identify_cpu(). We break the dependency by 968 * accessing cpu_data() through the canonical per-CPU address. 969 */ 970 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 971 identify_cpu(cpu_info); 972 973 #ifdef CONFIG_MCKINLEY 974 { 975 # define FEATURE_SET 16 976 struct ia64_pal_retval iprv; 977 978 if (cpu_info->family == 0x1f) { 979 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 980 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 981 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 982 (iprv.v1 | 0x80), FEATURE_SET, 0); 983 } 984 } 985 #endif 986 987 /* Clear the stack memory reserved for pt_regs: */ 988 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 989 990 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 991 992 /* 993 * Initialize the page-table base register to a global 994 * directory with all zeroes. This ensure that we can handle 995 * TLB-misses to user address-space even before we created the 996 * first user address-space. This may happen, e.g., due to 997 * aggressive use of lfetch.fault. 998 */ 999 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 1000 1001 /* 1002 * Initialize default control register to defer speculative faults except 1003 * for those arising from TLB misses, which are not deferred. The 1004 * kernel MUST NOT depend on a particular setting of these bits (in other words, 1005 * the kernel must have recovery code for all speculative accesses). Turn on 1006 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 1007 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 1008 * be fine). 1009 */ 1010 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 1011 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 1012 atomic_inc(&init_mm.mm_count); 1013 current->active_mm = &init_mm; 1014 BUG_ON(current->mm); 1015 1016 ia64_mmu_init(ia64_imva(cpu_data)); 1017 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1018 1019 #ifdef CONFIG_IA32_SUPPORT 1020 ia32_cpu_init(); 1021 #endif 1022 1023 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1024 ia64_set_itc(0); 1025 1026 /* disable all local interrupt sources: */ 1027 ia64_set_itv(1 << 16); 1028 ia64_set_lrr0(1 << 16); 1029 ia64_set_lrr1(1 << 16); 1030 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1031 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1032 1033 /* clear TPR & XTP to enable all interrupt classes: */ 1034 ia64_setreg(_IA64_REG_CR_TPR, 0); 1035 1036 /* Clear any pending interrupts left by SAL/EFI */ 1037 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1038 ia64_eoi(); 1039 1040 #ifdef CONFIG_SMP 1041 normal_xtp(); 1042 #endif 1043 1044 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1045 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1046 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1047 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1048 } else { 1049 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1050 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1051 } 1052 while (max_ctx < ia64_ctx.max_ctx) { 1053 unsigned int old = ia64_ctx.max_ctx; 1054 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1055 break; 1056 } 1057 1058 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1059 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1060 "stacked regs\n"); 1061 num_phys_stacked = 96; 1062 } 1063 /* size of physical stacked register partition plus 8 bytes: */ 1064 if (num_phys_stacked > max_num_phys_stacked) { 1065 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1066 max_num_phys_stacked = num_phys_stacked; 1067 } 1068 platform_cpu_init(); 1069 pm_idle = default_idle; 1070 } 1071 1072 void __init 1073 check_bugs (void) 1074 { 1075 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1076 (unsigned long) __end___mckinley_e9_bundles); 1077 } 1078 1079 static int __init run_dmi_scan(void) 1080 { 1081 dmi_scan_machine(); 1082 return 0; 1083 } 1084 core_initcall(run_dmi_scan); 1085