1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/machvec.h> 50 #include <asm/mca.h> 51 #include <asm/meminit.h> 52 #include <asm/page.h> 53 #include <asm/paravirt.h> 54 #include <asm/paravirt_patch.h> 55 #include <asm/patch.h> 56 #include <asm/pgtable.h> 57 #include <asm/processor.h> 58 #include <asm/sal.h> 59 #include <asm/sections.h> 60 #include <asm/setup.h> 61 #include <asm/smp.h> 62 #include <asm/system.h> 63 #include <asm/tlbflush.h> 64 #include <asm/unistd.h> 65 #include <asm/hpsim.h> 66 67 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 68 # error "struct cpuinfo_ia64 too big!" 69 #endif 70 71 #ifdef CONFIG_SMP 72 unsigned long __per_cpu_offset[NR_CPUS]; 73 EXPORT_SYMBOL(__per_cpu_offset); 74 #endif 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 94 static struct resource bss_resource = { 95 .name = "Kernel bss", 96 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 97 }; 98 99 unsigned long ia64_max_cacheline_size; 100 101 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 102 EXPORT_SYMBOL(ia64_iobase); 103 struct io_space io_space[MAX_IO_SPACES]; 104 EXPORT_SYMBOL(io_space); 105 unsigned int num_io_spaces; 106 107 /* 108 * "flush_icache_range()" needs to know what processor dependent stride size to use 109 * when it makes i-cache(s) coherent with d-caches. 110 */ 111 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 112 unsigned long ia64_i_cache_stride_shift = ~0; 113 /* 114 * "clflush_cache_range()" needs to know what processor dependent stride size to 115 * use when it flushes cache lines including both d-cache and i-cache. 116 */ 117 /* Safest way to go: 32 bytes by 32 bytes */ 118 #define CACHE_STRIDE_SHIFT 5 119 unsigned long ia64_cache_stride_shift = ~0; 120 121 /* 122 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 123 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 124 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 125 * address of the second buffer must be aligned to (merge_mask+1) in order to be 126 * mergeable). By default, we assume there is no I/O MMU which can merge physically 127 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 128 * page-size of 2^64. 129 */ 130 unsigned long ia64_max_iommu_merge_mask = ~0UL; 131 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 132 133 /* 134 * We use a special marker for the end of memory and it uses the extra (+1) slot 135 */ 136 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 137 int num_rsvd_regions __initdata; 138 139 140 /* 141 * Filter incoming memory segments based on the primitive map created from the boot 142 * parameters. Segments contained in the map are removed from the memory ranges. A 143 * caller-specified function is called with the memory ranges that remain after filtering. 144 * This routine does not assume the incoming segments are sorted. 145 */ 146 int __init 147 filter_rsvd_memory (u64 start, u64 end, void *arg) 148 { 149 u64 range_start, range_end, prev_start; 150 void (*func)(unsigned long, unsigned long, int); 151 int i; 152 153 #if IGNORE_PFN0 154 if (start == PAGE_OFFSET) { 155 printk(KERN_WARNING "warning: skipping physical page 0\n"); 156 start += PAGE_SIZE; 157 if (start >= end) return 0; 158 } 159 #endif 160 /* 161 * lowest possible address(walker uses virtual) 162 */ 163 prev_start = PAGE_OFFSET; 164 func = arg; 165 166 for (i = 0; i < num_rsvd_regions; ++i) { 167 range_start = max(start, prev_start); 168 range_end = min(end, rsvd_region[i].start); 169 170 if (range_start < range_end) 171 call_pernode_memory(__pa(range_start), range_end - range_start, func); 172 173 /* nothing more available in this segment */ 174 if (range_end == end) return 0; 175 176 prev_start = rsvd_region[i].end; 177 } 178 /* end of memory marker allows full processing inside loop body */ 179 return 0; 180 } 181 182 /* 183 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 184 * are not filtered out. 185 */ 186 int __init 187 filter_memory(u64 start, u64 end, void *arg) 188 { 189 void (*func)(unsigned long, unsigned long, int); 190 191 #if IGNORE_PFN0 192 if (start == PAGE_OFFSET) { 193 printk(KERN_WARNING "warning: skipping physical page 0\n"); 194 start += PAGE_SIZE; 195 if (start >= end) 196 return 0; 197 } 198 #endif 199 func = arg; 200 if (start < end) 201 call_pernode_memory(__pa(start), end - start, func); 202 return 0; 203 } 204 205 static void __init 206 sort_regions (struct rsvd_region *rsvd_region, int max) 207 { 208 int j; 209 210 /* simple bubble sorting */ 211 while (max--) { 212 for (j = 0; j < max; ++j) { 213 if (rsvd_region[j].start > rsvd_region[j+1].start) { 214 struct rsvd_region tmp; 215 tmp = rsvd_region[j]; 216 rsvd_region[j] = rsvd_region[j + 1]; 217 rsvd_region[j + 1] = tmp; 218 } 219 } 220 } 221 } 222 223 /* 224 * Request address space for all standard resources 225 */ 226 static int __init register_memory(void) 227 { 228 code_resource.start = ia64_tpa(_text); 229 code_resource.end = ia64_tpa(_etext) - 1; 230 data_resource.start = ia64_tpa(_etext); 231 data_resource.end = ia64_tpa(_edata) - 1; 232 bss_resource.start = ia64_tpa(__bss_start); 233 bss_resource.end = ia64_tpa(_end) - 1; 234 efi_initialize_iomem_resources(&code_resource, &data_resource, 235 &bss_resource); 236 237 return 0; 238 } 239 240 __initcall(register_memory); 241 242 243 #ifdef CONFIG_KEXEC 244 245 /* 246 * This function checks if the reserved crashkernel is allowed on the specific 247 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 248 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 249 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 250 * in kdump case. See the comment in sba_init() in sba_iommu.c. 251 * 252 * So, the only machvec that really supports loading the kdump kernel 253 * over 4 GB is "sn2". 254 */ 255 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 256 { 257 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 258 return 1; 259 else 260 return pbase < (1UL << 32); 261 } 262 263 static void __init setup_crashkernel(unsigned long total, int *n) 264 { 265 unsigned long long base = 0, size = 0; 266 int ret; 267 268 ret = parse_crashkernel(boot_command_line, total, 269 &size, &base); 270 if (ret == 0 && size > 0) { 271 if (!base) { 272 sort_regions(rsvd_region, *n); 273 base = kdump_find_rsvd_region(size, 274 rsvd_region, *n); 275 } 276 277 if (!check_crashkernel_memory(base, size)) { 278 pr_warning("crashkernel: There would be kdump memory " 279 "at %ld GB but this is unusable because it " 280 "must\nbe below 4 GB. Change the memory " 281 "configuration of the machine.\n", 282 (unsigned long)(base >> 30)); 283 return; 284 } 285 286 if (base != ~0UL) { 287 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 288 "for crashkernel (System RAM: %ldMB)\n", 289 (unsigned long)(size >> 20), 290 (unsigned long)(base >> 20), 291 (unsigned long)(total >> 20)); 292 rsvd_region[*n].start = 293 (unsigned long)__va(base); 294 rsvd_region[*n].end = 295 (unsigned long)__va(base + size); 296 (*n)++; 297 crashk_res.start = base; 298 crashk_res.end = base + size - 1; 299 } 300 } 301 efi_memmap_res.start = ia64_boot_param->efi_memmap; 302 efi_memmap_res.end = efi_memmap_res.start + 303 ia64_boot_param->efi_memmap_size; 304 boot_param_res.start = __pa(ia64_boot_param); 305 boot_param_res.end = boot_param_res.start + 306 sizeof(*ia64_boot_param); 307 } 308 #else 309 static inline void __init setup_crashkernel(unsigned long total, int *n) 310 {} 311 #endif 312 313 /** 314 * reserve_memory - setup reserved memory areas 315 * 316 * Setup the reserved memory areas set aside for the boot parameters, 317 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 318 * see arch/ia64/include/asm/meminit.h if you need to define more. 319 */ 320 void __init 321 reserve_memory (void) 322 { 323 int n = 0; 324 unsigned long total_memory; 325 326 /* 327 * none of the entries in this table overlap 328 */ 329 rsvd_region[n].start = (unsigned long) ia64_boot_param; 330 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 331 n++; 332 333 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 334 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 335 n++; 336 337 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 338 rsvd_region[n].end = (rsvd_region[n].start 339 + strlen(__va(ia64_boot_param->command_line)) + 1); 340 n++; 341 342 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 343 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 344 n++; 345 346 n += paravirt_reserve_memory(&rsvd_region[n]); 347 348 #ifdef CONFIG_BLK_DEV_INITRD 349 if (ia64_boot_param->initrd_start) { 350 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 351 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 352 n++; 353 } 354 #endif 355 356 #ifdef CONFIG_CRASH_DUMP 357 if (reserve_elfcorehdr(&rsvd_region[n].start, 358 &rsvd_region[n].end) == 0) 359 n++; 360 #endif 361 362 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 363 n++; 364 365 setup_crashkernel(total_memory, &n); 366 367 /* end of memory marker */ 368 rsvd_region[n].start = ~0UL; 369 rsvd_region[n].end = ~0UL; 370 n++; 371 372 num_rsvd_regions = n; 373 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 374 375 sort_regions(rsvd_region, num_rsvd_regions); 376 } 377 378 379 /** 380 * find_initrd - get initrd parameters from the boot parameter structure 381 * 382 * Grab the initrd start and end from the boot parameter struct given us by 383 * the boot loader. 384 */ 385 void __init 386 find_initrd (void) 387 { 388 #ifdef CONFIG_BLK_DEV_INITRD 389 if (ia64_boot_param->initrd_start) { 390 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 391 initrd_end = initrd_start+ia64_boot_param->initrd_size; 392 393 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 394 initrd_start, ia64_boot_param->initrd_size); 395 } 396 #endif 397 } 398 399 static void __init 400 io_port_init (void) 401 { 402 unsigned long phys_iobase; 403 404 /* 405 * Set `iobase' based on the EFI memory map or, failing that, the 406 * value firmware left in ar.k0. 407 * 408 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 409 * the port's virtual address, so ia32_load_state() loads it with a 410 * user virtual address. But in ia64 mode, glibc uses the 411 * *physical* address in ar.k0 to mmap the appropriate area from 412 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 413 * cases, user-mode can only use the legacy 0-64K I/O port space. 414 * 415 * ar.k0 is not involved in kernel I/O port accesses, which can use 416 * any of the I/O port spaces and are done via MMIO using the 417 * virtual mmio_base from the appropriate io_space[]. 418 */ 419 phys_iobase = efi_get_iobase(); 420 if (!phys_iobase) { 421 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 422 printk(KERN_INFO "No I/O port range found in EFI memory map, " 423 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 424 } 425 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 426 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 427 428 /* setup legacy IO port space */ 429 io_space[0].mmio_base = ia64_iobase; 430 io_space[0].sparse = 1; 431 num_io_spaces = 1; 432 } 433 434 /** 435 * early_console_setup - setup debugging console 436 * 437 * Consoles started here require little enough setup that we can start using 438 * them very early in the boot process, either right after the machine 439 * vector initialization, or even before if the drivers can detect their hw. 440 * 441 * Returns non-zero if a console couldn't be setup. 442 */ 443 static inline int __init 444 early_console_setup (char *cmdline) 445 { 446 int earlycons = 0; 447 448 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 449 { 450 extern int sn_serial_console_early_setup(void); 451 if (!sn_serial_console_early_setup()) 452 earlycons++; 453 } 454 #endif 455 #ifdef CONFIG_EFI_PCDP 456 if (!efi_setup_pcdp_console(cmdline)) 457 earlycons++; 458 #endif 459 if (!simcons_register()) 460 earlycons++; 461 462 return (earlycons) ? 0 : -1; 463 } 464 465 static inline void 466 mark_bsp_online (void) 467 { 468 #ifdef CONFIG_SMP 469 /* If we register an early console, allow CPU 0 to printk */ 470 cpu_set(smp_processor_id(), cpu_online_map); 471 #endif 472 } 473 474 static __initdata int nomca; 475 static __init int setup_nomca(char *s) 476 { 477 nomca = 1; 478 return 0; 479 } 480 early_param("nomca", setup_nomca); 481 482 #ifdef CONFIG_CRASH_DUMP 483 int __init reserve_elfcorehdr(u64 *start, u64 *end) 484 { 485 u64 length; 486 487 /* We get the address using the kernel command line, 488 * but the size is extracted from the EFI tables. 489 * Both address and size are required for reservation 490 * to work properly. 491 */ 492 493 if (!is_vmcore_usable()) 494 return -EINVAL; 495 496 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 497 vmcore_unusable(); 498 return -EINVAL; 499 } 500 501 *start = (unsigned long)__va(elfcorehdr_addr); 502 *end = *start + length; 503 return 0; 504 } 505 506 #endif /* CONFIG_PROC_VMCORE */ 507 508 void __init 509 setup_arch (char **cmdline_p) 510 { 511 unw_init(); 512 513 paravirt_arch_setup_early(); 514 515 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 516 paravirt_patch_apply(); 517 518 *cmdline_p = __va(ia64_boot_param->command_line); 519 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 520 521 efi_init(); 522 io_port_init(); 523 524 #ifdef CONFIG_IA64_GENERIC 525 /* machvec needs to be parsed from the command line 526 * before parse_early_param() is called to ensure 527 * that ia64_mv is initialised before any command line 528 * settings may cause console setup to occur 529 */ 530 machvec_init_from_cmdline(*cmdline_p); 531 #endif 532 533 parse_early_param(); 534 535 if (early_console_setup(*cmdline_p) == 0) 536 mark_bsp_online(); 537 538 #ifdef CONFIG_ACPI 539 /* Initialize the ACPI boot-time table parser */ 540 acpi_table_init(); 541 early_acpi_boot_init(); 542 # ifdef CONFIG_ACPI_NUMA 543 acpi_numa_init(); 544 # ifdef CONFIG_ACPI_HOTPLUG_CPU 545 prefill_possible_map(); 546 # endif 547 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? 548 32 : cpus_weight(early_cpu_possible_map)), 549 additional_cpus > 0 ? additional_cpus : 0); 550 # endif 551 #endif /* CONFIG_APCI_BOOT */ 552 553 #ifdef CONFIG_SMP 554 smp_build_cpu_map(); 555 #endif 556 find_memory(); 557 558 /* process SAL system table: */ 559 ia64_sal_init(__va(efi.sal_systab)); 560 561 #ifdef CONFIG_ITANIUM 562 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 563 #else 564 { 565 unsigned long num_phys_stacked; 566 567 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 568 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 569 } 570 #endif 571 572 #ifdef CONFIG_SMP 573 cpu_physical_id(0) = hard_smp_processor_id(); 574 #endif 575 576 cpu_init(); /* initialize the bootstrap CPU */ 577 mmu_context_init(); /* initialize context_id bitmap */ 578 579 paravirt_banner(); 580 paravirt_arch_setup_console(cmdline_p); 581 582 #ifdef CONFIG_VT 583 if (!conswitchp) { 584 # if defined(CONFIG_DUMMY_CONSOLE) 585 conswitchp = &dummy_con; 586 # endif 587 # if defined(CONFIG_VGA_CONSOLE) 588 /* 589 * Non-legacy systems may route legacy VGA MMIO range to system 590 * memory. vga_con probes the MMIO hole, so memory looks like 591 * a VGA device to it. The EFI memory map can tell us if it's 592 * memory so we can avoid this problem. 593 */ 594 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 595 conswitchp = &vga_con; 596 # endif 597 } 598 #endif 599 600 /* enable IA-64 Machine Check Abort Handling unless disabled */ 601 if (paravirt_arch_setup_nomca()) 602 nomca = 1; 603 if (!nomca) 604 ia64_mca_init(); 605 606 platform_setup(cmdline_p); 607 #ifndef CONFIG_IA64_HP_SIM 608 check_sal_cache_flush(); 609 #endif 610 paging_init(); 611 } 612 613 /* 614 * Display cpu info for all CPUs. 615 */ 616 static int 617 show_cpuinfo (struct seq_file *m, void *v) 618 { 619 #ifdef CONFIG_SMP 620 # define lpj c->loops_per_jiffy 621 # define cpunum c->cpu 622 #else 623 # define lpj loops_per_jiffy 624 # define cpunum 0 625 #endif 626 static struct { 627 unsigned long mask; 628 const char *feature_name; 629 } feature_bits[] = { 630 { 1UL << 0, "branchlong" }, 631 { 1UL << 1, "spontaneous deferral"}, 632 { 1UL << 2, "16-byte atomic ops" } 633 }; 634 char features[128], *cp, *sep; 635 struct cpuinfo_ia64 *c = v; 636 unsigned long mask; 637 unsigned long proc_freq; 638 int i, size; 639 640 mask = c->features; 641 642 /* build the feature string: */ 643 memcpy(features, "standard", 9); 644 cp = features; 645 size = sizeof(features); 646 sep = ""; 647 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 648 if (mask & feature_bits[i].mask) { 649 cp += snprintf(cp, size, "%s%s", sep, 650 feature_bits[i].feature_name), 651 sep = ", "; 652 mask &= ~feature_bits[i].mask; 653 size = sizeof(features) - (cp - features); 654 } 655 } 656 if (mask && size > 1) { 657 /* print unknown features as a hex value */ 658 snprintf(cp, size, "%s0x%lx", sep, mask); 659 } 660 661 proc_freq = cpufreq_quick_get(cpunum); 662 if (!proc_freq) 663 proc_freq = c->proc_freq / 1000; 664 665 seq_printf(m, 666 "processor : %d\n" 667 "vendor : %s\n" 668 "arch : IA-64\n" 669 "family : %u\n" 670 "model : %u\n" 671 "model name : %s\n" 672 "revision : %u\n" 673 "archrev : %u\n" 674 "features : %s\n" 675 "cpu number : %lu\n" 676 "cpu regs : %u\n" 677 "cpu MHz : %lu.%03lu\n" 678 "itc MHz : %lu.%06lu\n" 679 "BogoMIPS : %lu.%02lu\n", 680 cpunum, c->vendor, c->family, c->model, 681 c->model_name, c->revision, c->archrev, 682 features, c->ppn, c->number, 683 proc_freq / 1000, proc_freq % 1000, 684 c->itc_freq / 1000000, c->itc_freq % 1000000, 685 lpj*HZ/500000, (lpj*HZ/5000) % 100); 686 #ifdef CONFIG_SMP 687 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 688 if (c->socket_id != -1) 689 seq_printf(m, "physical id: %u\n", c->socket_id); 690 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 691 seq_printf(m, 692 "core id : %u\n" 693 "thread id : %u\n", 694 c->core_id, c->thread_id); 695 #endif 696 seq_printf(m,"\n"); 697 698 return 0; 699 } 700 701 static void * 702 c_start (struct seq_file *m, loff_t *pos) 703 { 704 #ifdef CONFIG_SMP 705 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 706 ++*pos; 707 #endif 708 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 709 } 710 711 static void * 712 c_next (struct seq_file *m, void *v, loff_t *pos) 713 { 714 ++*pos; 715 return c_start(m, pos); 716 } 717 718 static void 719 c_stop (struct seq_file *m, void *v) 720 { 721 } 722 723 const struct seq_operations cpuinfo_op = { 724 .start = c_start, 725 .next = c_next, 726 .stop = c_stop, 727 .show = show_cpuinfo 728 }; 729 730 #define MAX_BRANDS 8 731 static char brandname[MAX_BRANDS][128]; 732 733 static char * __cpuinit 734 get_model_name(__u8 family, __u8 model) 735 { 736 static int overflow; 737 char brand[128]; 738 int i; 739 740 memcpy(brand, "Unknown", 8); 741 if (ia64_pal_get_brand_info(brand)) { 742 if (family == 0x7) 743 memcpy(brand, "Merced", 7); 744 else if (family == 0x1f) switch (model) { 745 case 0: memcpy(brand, "McKinley", 9); break; 746 case 1: memcpy(brand, "Madison", 8); break; 747 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 748 } 749 } 750 for (i = 0; i < MAX_BRANDS; i++) 751 if (strcmp(brandname[i], brand) == 0) 752 return brandname[i]; 753 for (i = 0; i < MAX_BRANDS; i++) 754 if (brandname[i][0] == '\0') 755 return strcpy(brandname[i], brand); 756 if (overflow++ == 0) 757 printk(KERN_ERR 758 "%s: Table overflow. Some processor model information will be missing\n", 759 __func__); 760 return "Unknown"; 761 } 762 763 static void __cpuinit 764 identify_cpu (struct cpuinfo_ia64 *c) 765 { 766 union { 767 unsigned long bits[5]; 768 struct { 769 /* id 0 & 1: */ 770 char vendor[16]; 771 772 /* id 2 */ 773 u64 ppn; /* processor serial number */ 774 775 /* id 3: */ 776 unsigned number : 8; 777 unsigned revision : 8; 778 unsigned model : 8; 779 unsigned family : 8; 780 unsigned archrev : 8; 781 unsigned reserved : 24; 782 783 /* id 4: */ 784 u64 features; 785 } field; 786 } cpuid; 787 pal_vm_info_1_u_t vm1; 788 pal_vm_info_2_u_t vm2; 789 pal_status_t status; 790 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 791 int i; 792 for (i = 0; i < 5; ++i) 793 cpuid.bits[i] = ia64_get_cpuid(i); 794 795 memcpy(c->vendor, cpuid.field.vendor, 16); 796 #ifdef CONFIG_SMP 797 c->cpu = smp_processor_id(); 798 799 /* below default values will be overwritten by identify_siblings() 800 * for Multi-Threading/Multi-Core capable CPUs 801 */ 802 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 803 c->socket_id = -1; 804 805 identify_siblings(c); 806 807 if (c->threads_per_core > smp_num_siblings) 808 smp_num_siblings = c->threads_per_core; 809 #endif 810 c->ppn = cpuid.field.ppn; 811 c->number = cpuid.field.number; 812 c->revision = cpuid.field.revision; 813 c->model = cpuid.field.model; 814 c->family = cpuid.field.family; 815 c->archrev = cpuid.field.archrev; 816 c->features = cpuid.field.features; 817 c->model_name = get_model_name(c->family, c->model); 818 819 status = ia64_pal_vm_summary(&vm1, &vm2); 820 if (status == PAL_STATUS_SUCCESS) { 821 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 822 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 823 } 824 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 825 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 826 } 827 828 /* 829 * Do the following calculations: 830 * 831 * 1. the max. cache line size. 832 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 833 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 834 */ 835 static void __cpuinit 836 get_cache_info(void) 837 { 838 unsigned long line_size, max = 1; 839 unsigned long l, levels, unique_caches; 840 pal_cache_config_info_t cci; 841 long status; 842 843 status = ia64_pal_cache_summary(&levels, &unique_caches); 844 if (status != 0) { 845 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 846 __func__, status); 847 max = SMP_CACHE_BYTES; 848 /* Safest setup for "flush_icache_range()" */ 849 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 850 /* Safest setup for "clflush_cache_range()" */ 851 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 852 goto out; 853 } 854 855 for (l = 0; l < levels; ++l) { 856 /* cache_type (data_or_unified)=2 */ 857 status = ia64_pal_cache_config_info(l, 2, &cci); 858 if (status != 0) { 859 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 860 "(l=%lu, 2) failed (status=%ld)\n", 861 __func__, l, status); 862 max = SMP_CACHE_BYTES; 863 /* The safest setup for "flush_icache_range()" */ 864 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 865 /* The safest setup for "clflush_cache_range()" */ 866 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 867 cci.pcci_unified = 1; 868 } else { 869 if (cci.pcci_stride < ia64_cache_stride_shift) 870 ia64_cache_stride_shift = cci.pcci_stride; 871 872 line_size = 1 << cci.pcci_line_size; 873 if (line_size > max) 874 max = line_size; 875 } 876 877 if (!cci.pcci_unified) { 878 /* cache_type (instruction)=1*/ 879 status = ia64_pal_cache_config_info(l, 1, &cci); 880 if (status != 0) { 881 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 882 "(l=%lu, 1) failed (status=%ld)\n", 883 __func__, l, status); 884 /* The safest setup for flush_icache_range() */ 885 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 886 } 887 } 888 if (cci.pcci_stride < ia64_i_cache_stride_shift) 889 ia64_i_cache_stride_shift = cci.pcci_stride; 890 } 891 out: 892 if (max > ia64_max_cacheline_size) 893 ia64_max_cacheline_size = max; 894 } 895 896 /* 897 * cpu_init() initializes state that is per-CPU. This function acts 898 * as a 'CPU state barrier', nothing should get across. 899 */ 900 void __cpuinit 901 cpu_init (void) 902 { 903 extern void __cpuinit ia64_mmu_init (void *); 904 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 905 unsigned long num_phys_stacked; 906 pal_vm_info_2_u_t vmi; 907 unsigned int max_ctx; 908 struct cpuinfo_ia64 *cpu_info; 909 void *cpu_data; 910 911 cpu_data = per_cpu_init(); 912 #ifdef CONFIG_SMP 913 /* 914 * insert boot cpu into sibling and core mapes 915 * (must be done after per_cpu area is setup) 916 */ 917 if (smp_processor_id() == 0) { 918 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 919 cpu_set(0, cpu_core_map[0]); 920 } else { 921 /* 922 * Set ar.k3 so that assembly code in MCA handler can compute 923 * physical addresses of per cpu variables with a simple: 924 * phys = ar.k3 + &per_cpu_var 925 * and the alt-dtlb-miss handler can set per-cpu mapping into 926 * the TLB when needed. head.S already did this for cpu0. 927 */ 928 ia64_set_kr(IA64_KR_PER_CPU_DATA, 929 ia64_tpa(cpu_data) - (long) __per_cpu_start); 930 } 931 #endif 932 933 get_cache_info(); 934 935 /* 936 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 937 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 938 * depends on the data returned by identify_cpu(). We break the dependency by 939 * accessing cpu_data() through the canonical per-CPU address. 940 */ 941 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 942 identify_cpu(cpu_info); 943 944 #ifdef CONFIG_MCKINLEY 945 { 946 # define FEATURE_SET 16 947 struct ia64_pal_retval iprv; 948 949 if (cpu_info->family == 0x1f) { 950 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 951 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 952 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 953 (iprv.v1 | 0x80), FEATURE_SET, 0); 954 } 955 } 956 #endif 957 958 /* Clear the stack memory reserved for pt_regs: */ 959 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 960 961 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 962 963 /* 964 * Initialize the page-table base register to a global 965 * directory with all zeroes. This ensure that we can handle 966 * TLB-misses to user address-space even before we created the 967 * first user address-space. This may happen, e.g., due to 968 * aggressive use of lfetch.fault. 969 */ 970 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 971 972 /* 973 * Initialize default control register to defer speculative faults except 974 * for those arising from TLB misses, which are not deferred. The 975 * kernel MUST NOT depend on a particular setting of these bits (in other words, 976 * the kernel must have recovery code for all speculative accesses). Turn on 977 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 978 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 979 * be fine). 980 */ 981 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 982 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 983 atomic_inc(&init_mm.mm_count); 984 current->active_mm = &init_mm; 985 BUG_ON(current->mm); 986 987 ia64_mmu_init(ia64_imva(cpu_data)); 988 ia64_mca_cpu_init(ia64_imva(cpu_data)); 989 990 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 991 ia64_set_itc(0); 992 993 /* disable all local interrupt sources: */ 994 ia64_set_itv(1 << 16); 995 ia64_set_lrr0(1 << 16); 996 ia64_set_lrr1(1 << 16); 997 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 998 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 999 1000 /* clear TPR & XTP to enable all interrupt classes: */ 1001 ia64_setreg(_IA64_REG_CR_TPR, 0); 1002 1003 /* Clear any pending interrupts left by SAL/EFI */ 1004 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1005 ia64_eoi(); 1006 1007 #ifdef CONFIG_SMP 1008 normal_xtp(); 1009 #endif 1010 1011 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1012 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1013 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1014 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1015 } else { 1016 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1017 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1018 } 1019 while (max_ctx < ia64_ctx.max_ctx) { 1020 unsigned int old = ia64_ctx.max_ctx; 1021 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1022 break; 1023 } 1024 1025 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1026 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1027 "stacked regs\n"); 1028 num_phys_stacked = 96; 1029 } 1030 /* size of physical stacked register partition plus 8 bytes: */ 1031 if (num_phys_stacked > max_num_phys_stacked) { 1032 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1033 max_num_phys_stacked = num_phys_stacked; 1034 } 1035 platform_cpu_init(); 1036 pm_idle = default_idle; 1037 } 1038 1039 void __init 1040 check_bugs (void) 1041 { 1042 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1043 (unsigned long) __end___mckinley_e9_bundles); 1044 } 1045 1046 static int __init run_dmi_scan(void) 1047 { 1048 dmi_scan_machine(); 1049 return 0; 1050 } 1051 core_initcall(run_dmi_scan); 1052