1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/paravirt.h> 55 #include <asm/patch.h> 56 #include <asm/pgtable.h> 57 #include <asm/processor.h> 58 #include <asm/sal.h> 59 #include <asm/sections.h> 60 #include <asm/setup.h> 61 #include <asm/smp.h> 62 #include <asm/system.h> 63 #include <asm/tlbflush.h> 64 #include <asm/unistd.h> 65 #include <asm/hpsim.h> 66 67 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 68 # error "struct cpuinfo_ia64 too big!" 69 #endif 70 71 #ifdef CONFIG_SMP 72 unsigned long __per_cpu_offset[NR_CPUS]; 73 EXPORT_SYMBOL(__per_cpu_offset); 74 #endif 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 94 static struct resource bss_resource = { 95 .name = "Kernel bss", 96 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 97 }; 98 99 unsigned long ia64_max_cacheline_size; 100 101 int dma_get_cache_alignment(void) 102 { 103 return ia64_max_cacheline_size; 104 } 105 EXPORT_SYMBOL(dma_get_cache_alignment); 106 107 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 108 EXPORT_SYMBOL(ia64_iobase); 109 struct io_space io_space[MAX_IO_SPACES]; 110 EXPORT_SYMBOL(io_space); 111 unsigned int num_io_spaces; 112 113 /* 114 * "flush_icache_range()" needs to know what processor dependent stride size to use 115 * when it makes i-cache(s) coherent with d-caches. 116 */ 117 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 118 unsigned long ia64_i_cache_stride_shift = ~0; 119 /* 120 * "clflush_cache_range()" needs to know what processor dependent stride size to 121 * use when it flushes cache lines including both d-cache and i-cache. 122 */ 123 /* Safest way to go: 32 bytes by 32 bytes */ 124 #define CACHE_STRIDE_SHIFT 5 125 unsigned long ia64_cache_stride_shift = ~0; 126 127 /* 128 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 129 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 130 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 131 * address of the second buffer must be aligned to (merge_mask+1) in order to be 132 * mergeable). By default, we assume there is no I/O MMU which can merge physically 133 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 134 * page-size of 2^64. 135 */ 136 unsigned long ia64_max_iommu_merge_mask = ~0UL; 137 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 138 139 /* 140 * We use a special marker for the end of memory and it uses the extra (+1) slot 141 */ 142 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 143 int num_rsvd_regions __initdata; 144 145 146 /* 147 * Filter incoming memory segments based on the primitive map created from the boot 148 * parameters. Segments contained in the map are removed from the memory ranges. A 149 * caller-specified function is called with the memory ranges that remain after filtering. 150 * This routine does not assume the incoming segments are sorted. 151 */ 152 int __init 153 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 154 { 155 unsigned long range_start, range_end, prev_start; 156 void (*func)(unsigned long, unsigned long, int); 157 int i; 158 159 #if IGNORE_PFN0 160 if (start == PAGE_OFFSET) { 161 printk(KERN_WARNING "warning: skipping physical page 0\n"); 162 start += PAGE_SIZE; 163 if (start >= end) return 0; 164 } 165 #endif 166 /* 167 * lowest possible address(walker uses virtual) 168 */ 169 prev_start = PAGE_OFFSET; 170 func = arg; 171 172 for (i = 0; i < num_rsvd_regions; ++i) { 173 range_start = max(start, prev_start); 174 range_end = min(end, rsvd_region[i].start); 175 176 if (range_start < range_end) 177 call_pernode_memory(__pa(range_start), range_end - range_start, func); 178 179 /* nothing more available in this segment */ 180 if (range_end == end) return 0; 181 182 prev_start = rsvd_region[i].end; 183 } 184 /* end of memory marker allows full processing inside loop body */ 185 return 0; 186 } 187 188 /* 189 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 190 * are not filtered out. 191 */ 192 int __init 193 filter_memory(unsigned long start, unsigned long end, void *arg) 194 { 195 void (*func)(unsigned long, unsigned long, int); 196 197 #if IGNORE_PFN0 198 if (start == PAGE_OFFSET) { 199 printk(KERN_WARNING "warning: skipping physical page 0\n"); 200 start += PAGE_SIZE; 201 if (start >= end) 202 return 0; 203 } 204 #endif 205 func = arg; 206 if (start < end) 207 call_pernode_memory(__pa(start), end - start, func); 208 return 0; 209 } 210 211 static void __init 212 sort_regions (struct rsvd_region *rsvd_region, int max) 213 { 214 int j; 215 216 /* simple bubble sorting */ 217 while (max--) { 218 for (j = 0; j < max; ++j) { 219 if (rsvd_region[j].start > rsvd_region[j+1].start) { 220 struct rsvd_region tmp; 221 tmp = rsvd_region[j]; 222 rsvd_region[j] = rsvd_region[j + 1]; 223 rsvd_region[j + 1] = tmp; 224 } 225 } 226 } 227 } 228 229 /* 230 * Request address space for all standard resources 231 */ 232 static int __init register_memory(void) 233 { 234 code_resource.start = ia64_tpa(_text); 235 code_resource.end = ia64_tpa(_etext) - 1; 236 data_resource.start = ia64_tpa(_etext); 237 data_resource.end = ia64_tpa(_edata) - 1; 238 bss_resource.start = ia64_tpa(__bss_start); 239 bss_resource.end = ia64_tpa(_end) - 1; 240 efi_initialize_iomem_resources(&code_resource, &data_resource, 241 &bss_resource); 242 243 return 0; 244 } 245 246 __initcall(register_memory); 247 248 249 #ifdef CONFIG_KEXEC 250 251 /* 252 * This function checks if the reserved crashkernel is allowed on the specific 253 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 254 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 255 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 256 * in kdump case. See the comment in sba_init() in sba_iommu.c. 257 * 258 * So, the only machvec that really supports loading the kdump kernel 259 * over 4 GB is "sn2". 260 */ 261 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 262 { 263 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 264 return 1; 265 else 266 return pbase < (1UL << 32); 267 } 268 269 static void __init setup_crashkernel(unsigned long total, int *n) 270 { 271 unsigned long long base = 0, size = 0; 272 int ret; 273 274 ret = parse_crashkernel(boot_command_line, total, 275 &size, &base); 276 if (ret == 0 && size > 0) { 277 if (!base) { 278 sort_regions(rsvd_region, *n); 279 base = kdump_find_rsvd_region(size, 280 rsvd_region, *n); 281 } 282 283 if (!check_crashkernel_memory(base, size)) { 284 pr_warning("crashkernel: There would be kdump memory " 285 "at %ld GB but this is unusable because it " 286 "must\nbe below 4 GB. Change the memory " 287 "configuration of the machine.\n", 288 (unsigned long)(base >> 30)); 289 return; 290 } 291 292 if (base != ~0UL) { 293 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 294 "for crashkernel (System RAM: %ldMB)\n", 295 (unsigned long)(size >> 20), 296 (unsigned long)(base >> 20), 297 (unsigned long)(total >> 20)); 298 rsvd_region[*n].start = 299 (unsigned long)__va(base); 300 rsvd_region[*n].end = 301 (unsigned long)__va(base + size); 302 (*n)++; 303 crashk_res.start = base; 304 crashk_res.end = base + size - 1; 305 } 306 } 307 efi_memmap_res.start = ia64_boot_param->efi_memmap; 308 efi_memmap_res.end = efi_memmap_res.start + 309 ia64_boot_param->efi_memmap_size; 310 boot_param_res.start = __pa(ia64_boot_param); 311 boot_param_res.end = boot_param_res.start + 312 sizeof(*ia64_boot_param); 313 } 314 #else 315 static inline void __init setup_crashkernel(unsigned long total, int *n) 316 {} 317 #endif 318 319 /** 320 * reserve_memory - setup reserved memory areas 321 * 322 * Setup the reserved memory areas set aside for the boot parameters, 323 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 324 * see arch/ia64/include/asm/meminit.h if you need to define more. 325 */ 326 void __init 327 reserve_memory (void) 328 { 329 int n = 0; 330 unsigned long total_memory; 331 332 /* 333 * none of the entries in this table overlap 334 */ 335 rsvd_region[n].start = (unsigned long) ia64_boot_param; 336 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 337 n++; 338 339 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 340 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 341 n++; 342 343 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 344 rsvd_region[n].end = (rsvd_region[n].start 345 + strlen(__va(ia64_boot_param->command_line)) + 1); 346 n++; 347 348 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 349 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 350 n++; 351 352 n += paravirt_reserve_memory(&rsvd_region[n]); 353 354 #ifdef CONFIG_BLK_DEV_INITRD 355 if (ia64_boot_param->initrd_start) { 356 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 357 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 358 n++; 359 } 360 #endif 361 362 #ifdef CONFIG_CRASH_KERNEL 363 if (reserve_elfcorehdr(&rsvd_region[n].start, 364 &rsvd_region[n].end) == 0) 365 n++; 366 #endif 367 368 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 369 n++; 370 371 setup_crashkernel(total_memory, &n); 372 373 /* end of memory marker */ 374 rsvd_region[n].start = ~0UL; 375 rsvd_region[n].end = ~0UL; 376 n++; 377 378 num_rsvd_regions = n; 379 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 380 381 sort_regions(rsvd_region, num_rsvd_regions); 382 } 383 384 385 /** 386 * find_initrd - get initrd parameters from the boot parameter structure 387 * 388 * Grab the initrd start and end from the boot parameter struct given us by 389 * the boot loader. 390 */ 391 void __init 392 find_initrd (void) 393 { 394 #ifdef CONFIG_BLK_DEV_INITRD 395 if (ia64_boot_param->initrd_start) { 396 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 397 initrd_end = initrd_start+ia64_boot_param->initrd_size; 398 399 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 400 initrd_start, ia64_boot_param->initrd_size); 401 } 402 #endif 403 } 404 405 static void __init 406 io_port_init (void) 407 { 408 unsigned long phys_iobase; 409 410 /* 411 * Set `iobase' based on the EFI memory map or, failing that, the 412 * value firmware left in ar.k0. 413 * 414 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 415 * the port's virtual address, so ia32_load_state() loads it with a 416 * user virtual address. But in ia64 mode, glibc uses the 417 * *physical* address in ar.k0 to mmap the appropriate area from 418 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 419 * cases, user-mode can only use the legacy 0-64K I/O port space. 420 * 421 * ar.k0 is not involved in kernel I/O port accesses, which can use 422 * any of the I/O port spaces and are done via MMIO using the 423 * virtual mmio_base from the appropriate io_space[]. 424 */ 425 phys_iobase = efi_get_iobase(); 426 if (!phys_iobase) { 427 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 428 printk(KERN_INFO "No I/O port range found in EFI memory map, " 429 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 430 } 431 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 432 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 433 434 /* setup legacy IO port space */ 435 io_space[0].mmio_base = ia64_iobase; 436 io_space[0].sparse = 1; 437 num_io_spaces = 1; 438 } 439 440 /** 441 * early_console_setup - setup debugging console 442 * 443 * Consoles started here require little enough setup that we can start using 444 * them very early in the boot process, either right after the machine 445 * vector initialization, or even before if the drivers can detect their hw. 446 * 447 * Returns non-zero if a console couldn't be setup. 448 */ 449 static inline int __init 450 early_console_setup (char *cmdline) 451 { 452 int earlycons = 0; 453 454 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 455 { 456 extern int sn_serial_console_early_setup(void); 457 if (!sn_serial_console_early_setup()) 458 earlycons++; 459 } 460 #endif 461 #ifdef CONFIG_EFI_PCDP 462 if (!efi_setup_pcdp_console(cmdline)) 463 earlycons++; 464 #endif 465 if (!simcons_register()) 466 earlycons++; 467 468 return (earlycons) ? 0 : -1; 469 } 470 471 static inline void 472 mark_bsp_online (void) 473 { 474 #ifdef CONFIG_SMP 475 /* If we register an early console, allow CPU 0 to printk */ 476 cpu_set(smp_processor_id(), cpu_online_map); 477 #endif 478 } 479 480 static __initdata int nomca; 481 static __init int setup_nomca(char *s) 482 { 483 nomca = 1; 484 return 0; 485 } 486 early_param("nomca", setup_nomca); 487 488 /* 489 * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by 490 * is_kdump_kernel() to determine if we are booting after a panic. Hence 491 * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE. 492 */ 493 #ifdef CONFIG_CRASH_DUMP 494 /* elfcorehdr= specifies the location of elf core header 495 * stored by the crashed kernel. 496 */ 497 static int __init parse_elfcorehdr(char *arg) 498 { 499 if (!arg) 500 return -EINVAL; 501 502 elfcorehdr_addr = memparse(arg, &arg); 503 return 0; 504 } 505 early_param("elfcorehdr", parse_elfcorehdr); 506 507 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 508 { 509 unsigned long length; 510 511 /* We get the address using the kernel command line, 512 * but the size is extracted from the EFI tables. 513 * Both address and size are required for reservation 514 * to work properly. 515 */ 516 517 if (!is_vmcore_usable()) 518 return -EINVAL; 519 520 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 521 vmcore_unusable(); 522 return -EINVAL; 523 } 524 525 *start = (unsigned long)__va(elfcorehdr_addr); 526 *end = *start + length; 527 return 0; 528 } 529 530 #endif /* CONFIG_PROC_VMCORE */ 531 532 void __init 533 setup_arch (char **cmdline_p) 534 { 535 unw_init(); 536 537 paravirt_arch_setup_early(); 538 539 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 540 541 *cmdline_p = __va(ia64_boot_param->command_line); 542 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 543 544 efi_init(); 545 io_port_init(); 546 547 #ifdef CONFIG_IA64_GENERIC 548 /* machvec needs to be parsed from the command line 549 * before parse_early_param() is called to ensure 550 * that ia64_mv is initialised before any command line 551 * settings may cause console setup to occur 552 */ 553 machvec_init_from_cmdline(*cmdline_p); 554 #endif 555 556 parse_early_param(); 557 558 if (early_console_setup(*cmdline_p) == 0) 559 mark_bsp_online(); 560 561 #ifdef CONFIG_ACPI 562 /* Initialize the ACPI boot-time table parser */ 563 acpi_table_init(); 564 # ifdef CONFIG_ACPI_NUMA 565 acpi_numa_init(); 566 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? 567 32 : cpus_weight(early_cpu_possible_map)), 568 additional_cpus > 0 ? additional_cpus : 0); 569 # endif 570 #else 571 # ifdef CONFIG_SMP 572 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 573 # endif 574 #endif /* CONFIG_APCI_BOOT */ 575 576 find_memory(); 577 578 /* process SAL system table: */ 579 ia64_sal_init(__va(efi.sal_systab)); 580 581 #ifdef CONFIG_ITANIUM 582 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 583 #else 584 { 585 u64 num_phys_stacked; 586 587 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 588 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 589 } 590 #endif 591 592 #ifdef CONFIG_SMP 593 cpu_physical_id(0) = hard_smp_processor_id(); 594 #endif 595 596 cpu_init(); /* initialize the bootstrap CPU */ 597 mmu_context_init(); /* initialize context_id bitmap */ 598 599 #ifdef CONFIG_ACPI 600 acpi_boot_init(); 601 #endif 602 603 paravirt_banner(); 604 paravirt_arch_setup_console(cmdline_p); 605 606 #ifdef CONFIG_VT 607 if (!conswitchp) { 608 # if defined(CONFIG_DUMMY_CONSOLE) 609 conswitchp = &dummy_con; 610 # endif 611 # if defined(CONFIG_VGA_CONSOLE) 612 /* 613 * Non-legacy systems may route legacy VGA MMIO range to system 614 * memory. vga_con probes the MMIO hole, so memory looks like 615 * a VGA device to it. The EFI memory map can tell us if it's 616 * memory so we can avoid this problem. 617 */ 618 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 619 conswitchp = &vga_con; 620 # endif 621 } 622 #endif 623 624 /* enable IA-64 Machine Check Abort Handling unless disabled */ 625 if (paravirt_arch_setup_nomca()) 626 nomca = 1; 627 if (!nomca) 628 ia64_mca_init(); 629 630 platform_setup(cmdline_p); 631 #ifndef CONFIG_IA64_HP_SIM 632 check_sal_cache_flush(); 633 #endif 634 paging_init(); 635 } 636 637 /* 638 * Display cpu info for all CPUs. 639 */ 640 static int 641 show_cpuinfo (struct seq_file *m, void *v) 642 { 643 #ifdef CONFIG_SMP 644 # define lpj c->loops_per_jiffy 645 # define cpunum c->cpu 646 #else 647 # define lpj loops_per_jiffy 648 # define cpunum 0 649 #endif 650 static struct { 651 unsigned long mask; 652 const char *feature_name; 653 } feature_bits[] = { 654 { 1UL << 0, "branchlong" }, 655 { 1UL << 1, "spontaneous deferral"}, 656 { 1UL << 2, "16-byte atomic ops" } 657 }; 658 char features[128], *cp, *sep; 659 struct cpuinfo_ia64 *c = v; 660 unsigned long mask; 661 unsigned long proc_freq; 662 int i, size; 663 664 mask = c->features; 665 666 /* build the feature string: */ 667 memcpy(features, "standard", 9); 668 cp = features; 669 size = sizeof(features); 670 sep = ""; 671 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 672 if (mask & feature_bits[i].mask) { 673 cp += snprintf(cp, size, "%s%s", sep, 674 feature_bits[i].feature_name), 675 sep = ", "; 676 mask &= ~feature_bits[i].mask; 677 size = sizeof(features) - (cp - features); 678 } 679 } 680 if (mask && size > 1) { 681 /* print unknown features as a hex value */ 682 snprintf(cp, size, "%s0x%lx", sep, mask); 683 } 684 685 proc_freq = cpufreq_quick_get(cpunum); 686 if (!proc_freq) 687 proc_freq = c->proc_freq / 1000; 688 689 seq_printf(m, 690 "processor : %d\n" 691 "vendor : %s\n" 692 "arch : IA-64\n" 693 "family : %u\n" 694 "model : %u\n" 695 "model name : %s\n" 696 "revision : %u\n" 697 "archrev : %u\n" 698 "features : %s\n" 699 "cpu number : %lu\n" 700 "cpu regs : %u\n" 701 "cpu MHz : %lu.%03lu\n" 702 "itc MHz : %lu.%06lu\n" 703 "BogoMIPS : %lu.%02lu\n", 704 cpunum, c->vendor, c->family, c->model, 705 c->model_name, c->revision, c->archrev, 706 features, c->ppn, c->number, 707 proc_freq / 1000, proc_freq % 1000, 708 c->itc_freq / 1000000, c->itc_freq % 1000000, 709 lpj*HZ/500000, (lpj*HZ/5000) % 100); 710 #ifdef CONFIG_SMP 711 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 712 if (c->socket_id != -1) 713 seq_printf(m, "physical id: %u\n", c->socket_id); 714 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 715 seq_printf(m, 716 "core id : %u\n" 717 "thread id : %u\n", 718 c->core_id, c->thread_id); 719 #endif 720 seq_printf(m,"\n"); 721 722 return 0; 723 } 724 725 static void * 726 c_start (struct seq_file *m, loff_t *pos) 727 { 728 #ifdef CONFIG_SMP 729 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 730 ++*pos; 731 #endif 732 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 733 } 734 735 static void * 736 c_next (struct seq_file *m, void *v, loff_t *pos) 737 { 738 ++*pos; 739 return c_start(m, pos); 740 } 741 742 static void 743 c_stop (struct seq_file *m, void *v) 744 { 745 } 746 747 const struct seq_operations cpuinfo_op = { 748 .start = c_start, 749 .next = c_next, 750 .stop = c_stop, 751 .show = show_cpuinfo 752 }; 753 754 #define MAX_BRANDS 8 755 static char brandname[MAX_BRANDS][128]; 756 757 static char * __cpuinit 758 get_model_name(__u8 family, __u8 model) 759 { 760 static int overflow; 761 char brand[128]; 762 int i; 763 764 memcpy(brand, "Unknown", 8); 765 if (ia64_pal_get_brand_info(brand)) { 766 if (family == 0x7) 767 memcpy(brand, "Merced", 7); 768 else if (family == 0x1f) switch (model) { 769 case 0: memcpy(brand, "McKinley", 9); break; 770 case 1: memcpy(brand, "Madison", 8); break; 771 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 772 } 773 } 774 for (i = 0; i < MAX_BRANDS; i++) 775 if (strcmp(brandname[i], brand) == 0) 776 return brandname[i]; 777 for (i = 0; i < MAX_BRANDS; i++) 778 if (brandname[i][0] == '\0') 779 return strcpy(brandname[i], brand); 780 if (overflow++ == 0) 781 printk(KERN_ERR 782 "%s: Table overflow. Some processor model information will be missing\n", 783 __func__); 784 return "Unknown"; 785 } 786 787 static void __cpuinit 788 identify_cpu (struct cpuinfo_ia64 *c) 789 { 790 union { 791 unsigned long bits[5]; 792 struct { 793 /* id 0 & 1: */ 794 char vendor[16]; 795 796 /* id 2 */ 797 u64 ppn; /* processor serial number */ 798 799 /* id 3: */ 800 unsigned number : 8; 801 unsigned revision : 8; 802 unsigned model : 8; 803 unsigned family : 8; 804 unsigned archrev : 8; 805 unsigned reserved : 24; 806 807 /* id 4: */ 808 u64 features; 809 } field; 810 } cpuid; 811 pal_vm_info_1_u_t vm1; 812 pal_vm_info_2_u_t vm2; 813 pal_status_t status; 814 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 815 int i; 816 for (i = 0; i < 5; ++i) 817 cpuid.bits[i] = ia64_get_cpuid(i); 818 819 memcpy(c->vendor, cpuid.field.vendor, 16); 820 #ifdef CONFIG_SMP 821 c->cpu = smp_processor_id(); 822 823 /* below default values will be overwritten by identify_siblings() 824 * for Multi-Threading/Multi-Core capable CPUs 825 */ 826 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 827 c->socket_id = -1; 828 829 identify_siblings(c); 830 831 if (c->threads_per_core > smp_num_siblings) 832 smp_num_siblings = c->threads_per_core; 833 #endif 834 c->ppn = cpuid.field.ppn; 835 c->number = cpuid.field.number; 836 c->revision = cpuid.field.revision; 837 c->model = cpuid.field.model; 838 c->family = cpuid.field.family; 839 c->archrev = cpuid.field.archrev; 840 c->features = cpuid.field.features; 841 c->model_name = get_model_name(c->family, c->model); 842 843 status = ia64_pal_vm_summary(&vm1, &vm2); 844 if (status == PAL_STATUS_SUCCESS) { 845 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 846 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 847 } 848 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 849 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 850 } 851 852 void __init 853 setup_per_cpu_areas (void) 854 { 855 /* start_kernel() requires this... */ 856 #ifdef CONFIG_ACPI_HOTPLUG_CPU 857 prefill_possible_map(); 858 #endif 859 } 860 861 /* 862 * Do the following calculations: 863 * 864 * 1. the max. cache line size. 865 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 866 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 867 */ 868 static void __cpuinit 869 get_cache_info(void) 870 { 871 unsigned long line_size, max = 1; 872 u64 l, levels, unique_caches; 873 pal_cache_config_info_t cci; 874 s64 status; 875 876 status = ia64_pal_cache_summary(&levels, &unique_caches); 877 if (status != 0) { 878 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 879 __func__, status); 880 max = SMP_CACHE_BYTES; 881 /* Safest setup for "flush_icache_range()" */ 882 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 883 /* Safest setup for "clflush_cache_range()" */ 884 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 885 goto out; 886 } 887 888 for (l = 0; l < levels; ++l) { 889 /* cache_type (data_or_unified)=2 */ 890 status = ia64_pal_cache_config_info(l, 2, &cci); 891 if (status != 0) { 892 printk(KERN_ERR 893 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 894 __func__, l, status); 895 max = SMP_CACHE_BYTES; 896 /* The safest setup for "flush_icache_range()" */ 897 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 898 /* The safest setup for "clflush_cache_range()" */ 899 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 900 cci.pcci_unified = 1; 901 } else { 902 if (cci.pcci_stride < ia64_cache_stride_shift) 903 ia64_cache_stride_shift = cci.pcci_stride; 904 905 line_size = 1 << cci.pcci_line_size; 906 if (line_size > max) 907 max = line_size; 908 } 909 910 if (!cci.pcci_unified) { 911 /* cache_type (instruction)=1*/ 912 status = ia64_pal_cache_config_info(l, 1, &cci); 913 if (status != 0) { 914 printk(KERN_ERR 915 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 916 __func__, l, status); 917 /* The safest setup for "flush_icache_range()" */ 918 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 919 } 920 } 921 if (cci.pcci_stride < ia64_i_cache_stride_shift) 922 ia64_i_cache_stride_shift = cci.pcci_stride; 923 } 924 out: 925 if (max > ia64_max_cacheline_size) 926 ia64_max_cacheline_size = max; 927 } 928 929 /* 930 * cpu_init() initializes state that is per-CPU. This function acts 931 * as a 'CPU state barrier', nothing should get across. 932 */ 933 void __cpuinit 934 cpu_init (void) 935 { 936 extern void __cpuinit ia64_mmu_init (void *); 937 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 938 unsigned long num_phys_stacked; 939 pal_vm_info_2_u_t vmi; 940 unsigned int max_ctx; 941 struct cpuinfo_ia64 *cpu_info; 942 void *cpu_data; 943 944 cpu_data = per_cpu_init(); 945 #ifdef CONFIG_SMP 946 /* 947 * insert boot cpu into sibling and core mapes 948 * (must be done after per_cpu area is setup) 949 */ 950 if (smp_processor_id() == 0) { 951 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 952 cpu_set(0, cpu_core_map[0]); 953 } else { 954 /* 955 * Set ar.k3 so that assembly code in MCA handler can compute 956 * physical addresses of per cpu variables with a simple: 957 * phys = ar.k3 + &per_cpu_var 958 * and the alt-dtlb-miss handler can set per-cpu mapping into 959 * the TLB when needed. head.S already did this for cpu0. 960 */ 961 ia64_set_kr(IA64_KR_PER_CPU_DATA, 962 ia64_tpa(cpu_data) - (long) __per_cpu_start); 963 } 964 #endif 965 966 get_cache_info(); 967 968 /* 969 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 970 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 971 * depends on the data returned by identify_cpu(). We break the dependency by 972 * accessing cpu_data() through the canonical per-CPU address. 973 */ 974 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 975 identify_cpu(cpu_info); 976 977 #ifdef CONFIG_MCKINLEY 978 { 979 # define FEATURE_SET 16 980 struct ia64_pal_retval iprv; 981 982 if (cpu_info->family == 0x1f) { 983 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 984 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 985 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 986 (iprv.v1 | 0x80), FEATURE_SET, 0); 987 } 988 } 989 #endif 990 991 /* Clear the stack memory reserved for pt_regs: */ 992 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 993 994 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 995 996 /* 997 * Initialize the page-table base register to a global 998 * directory with all zeroes. This ensure that we can handle 999 * TLB-misses to user address-space even before we created the 1000 * first user address-space. This may happen, e.g., due to 1001 * aggressive use of lfetch.fault. 1002 */ 1003 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 1004 1005 /* 1006 * Initialize default control register to defer speculative faults except 1007 * for those arising from TLB misses, which are not deferred. The 1008 * kernel MUST NOT depend on a particular setting of these bits (in other words, 1009 * the kernel must have recovery code for all speculative accesses). Turn on 1010 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 1011 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 1012 * be fine). 1013 */ 1014 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 1015 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 1016 atomic_inc(&init_mm.mm_count); 1017 current->active_mm = &init_mm; 1018 if (current->mm) 1019 BUG(); 1020 1021 ia64_mmu_init(ia64_imva(cpu_data)); 1022 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1023 1024 #ifdef CONFIG_IA32_SUPPORT 1025 ia32_cpu_init(); 1026 #endif 1027 1028 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1029 ia64_set_itc(0); 1030 1031 /* disable all local interrupt sources: */ 1032 ia64_set_itv(1 << 16); 1033 ia64_set_lrr0(1 << 16); 1034 ia64_set_lrr1(1 << 16); 1035 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1036 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1037 1038 /* clear TPR & XTP to enable all interrupt classes: */ 1039 ia64_setreg(_IA64_REG_CR_TPR, 0); 1040 1041 /* Clear any pending interrupts left by SAL/EFI */ 1042 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1043 ia64_eoi(); 1044 1045 #ifdef CONFIG_SMP 1046 normal_xtp(); 1047 #endif 1048 1049 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1050 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1051 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1052 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1053 } else { 1054 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1055 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1056 } 1057 while (max_ctx < ia64_ctx.max_ctx) { 1058 unsigned int old = ia64_ctx.max_ctx; 1059 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1060 break; 1061 } 1062 1063 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1064 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1065 "stacked regs\n"); 1066 num_phys_stacked = 96; 1067 } 1068 /* size of physical stacked register partition plus 8 bytes: */ 1069 if (num_phys_stacked > max_num_phys_stacked) { 1070 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1071 max_num_phys_stacked = num_phys_stacked; 1072 } 1073 platform_cpu_init(); 1074 pm_idle = default_idle; 1075 } 1076 1077 void __init 1078 check_bugs (void) 1079 { 1080 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1081 (unsigned long) __end___mckinley_e9_bundles); 1082 } 1083 1084 static int __init run_dmi_scan(void) 1085 { 1086 dmi_scan_machine(); 1087 return 0; 1088 } 1089 core_initcall(run_dmi_scan); 1090