1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/tty.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 47 #include <asm/ia32.h> 48 #include <asm/machvec.h> 49 #include <asm/mca.h> 50 #include <asm/meminit.h> 51 #include <asm/page.h> 52 #include <asm/patch.h> 53 #include <asm/pgtable.h> 54 #include <asm/processor.h> 55 #include <asm/sal.h> 56 #include <asm/sections.h> 57 #include <asm/serial.h> 58 #include <asm/setup.h> 59 #include <asm/smp.h> 60 #include <asm/system.h> 61 #include <asm/unistd.h> 62 #include <asm/system.h> 63 64 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 65 # error "struct cpuinfo_ia64 too big!" 66 #endif 67 68 #ifdef CONFIG_SMP 69 unsigned long __per_cpu_offset[NR_CPUS]; 70 EXPORT_SYMBOL(__per_cpu_offset); 71 #endif 72 73 extern void ia64_setup_printk_clock(void); 74 75 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 76 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 77 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 extern void efi_initialize_iomem_resources(struct resource *, 94 struct resource *); 95 extern char _text[], _end[], _etext[]; 96 97 unsigned long ia64_max_cacheline_size; 98 99 int dma_get_cache_alignment(void) 100 { 101 return ia64_max_cacheline_size; 102 } 103 EXPORT_SYMBOL(dma_get_cache_alignment); 104 105 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 106 EXPORT_SYMBOL(ia64_iobase); 107 struct io_space io_space[MAX_IO_SPACES]; 108 EXPORT_SYMBOL(io_space); 109 unsigned int num_io_spaces; 110 111 /* 112 * "flush_icache_range()" needs to know what processor dependent stride size to use 113 * when it makes i-cache(s) coherent with d-caches. 114 */ 115 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 116 unsigned long ia64_i_cache_stride_shift = ~0; 117 118 /* 119 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 120 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 121 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 122 * address of the second buffer must be aligned to (merge_mask+1) in order to be 123 * mergeable). By default, we assume there is no I/O MMU which can merge physically 124 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 125 * page-size of 2^64. 126 */ 127 unsigned long ia64_max_iommu_merge_mask = ~0UL; 128 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 129 130 /* 131 * We use a special marker for the end of memory and it uses the extra (+1) slot 132 */ 133 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 134 int num_rsvd_regions __initdata; 135 136 137 /* 138 * Filter incoming memory segments based on the primitive map created from the boot 139 * parameters. Segments contained in the map are removed from the memory ranges. A 140 * caller-specified function is called with the memory ranges that remain after filtering. 141 * This routine does not assume the incoming segments are sorted. 142 */ 143 int __init 144 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 145 { 146 unsigned long range_start, range_end, prev_start; 147 void (*func)(unsigned long, unsigned long, int); 148 int i; 149 150 #if IGNORE_PFN0 151 if (start == PAGE_OFFSET) { 152 printk(KERN_WARNING "warning: skipping physical page 0\n"); 153 start += PAGE_SIZE; 154 if (start >= end) return 0; 155 } 156 #endif 157 /* 158 * lowest possible address(walker uses virtual) 159 */ 160 prev_start = PAGE_OFFSET; 161 func = arg; 162 163 for (i = 0; i < num_rsvd_regions; ++i) { 164 range_start = max(start, prev_start); 165 range_end = min(end, rsvd_region[i].start); 166 167 if (range_start < range_end) 168 call_pernode_memory(__pa(range_start), range_end - range_start, func); 169 170 /* nothing more available in this segment */ 171 if (range_end == end) return 0; 172 173 prev_start = rsvd_region[i].end; 174 } 175 /* end of memory marker allows full processing inside loop body */ 176 return 0; 177 } 178 179 static void __init 180 sort_regions (struct rsvd_region *rsvd_region, int max) 181 { 182 int j; 183 184 /* simple bubble sorting */ 185 while (max--) { 186 for (j = 0; j < max; ++j) { 187 if (rsvd_region[j].start > rsvd_region[j+1].start) { 188 struct rsvd_region tmp; 189 tmp = rsvd_region[j]; 190 rsvd_region[j] = rsvd_region[j + 1]; 191 rsvd_region[j + 1] = tmp; 192 } 193 } 194 } 195 } 196 197 /* 198 * Request address space for all standard resources 199 */ 200 static int __init register_memory(void) 201 { 202 code_resource.start = ia64_tpa(_text); 203 code_resource.end = ia64_tpa(_etext) - 1; 204 data_resource.start = ia64_tpa(_etext); 205 data_resource.end = ia64_tpa(_end) - 1; 206 efi_initialize_iomem_resources(&code_resource, &data_resource); 207 208 return 0; 209 } 210 211 __initcall(register_memory); 212 213 /** 214 * reserve_memory - setup reserved memory areas 215 * 216 * Setup the reserved memory areas set aside for the boot parameters, 217 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 218 * see include/asm-ia64/meminit.h if you need to define more. 219 */ 220 void __init 221 reserve_memory (void) 222 { 223 int n = 0; 224 225 /* 226 * none of the entries in this table overlap 227 */ 228 rsvd_region[n].start = (unsigned long) ia64_boot_param; 229 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 230 n++; 231 232 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 233 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 234 n++; 235 236 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 237 rsvd_region[n].end = (rsvd_region[n].start 238 + strlen(__va(ia64_boot_param->command_line)) + 1); 239 n++; 240 241 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 242 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 243 n++; 244 245 #ifdef CONFIG_BLK_DEV_INITRD 246 if (ia64_boot_param->initrd_start) { 247 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 248 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 249 n++; 250 } 251 #endif 252 253 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 254 n++; 255 256 /* end of memory marker */ 257 rsvd_region[n].start = ~0UL; 258 rsvd_region[n].end = ~0UL; 259 n++; 260 261 num_rsvd_regions = n; 262 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 263 264 sort_regions(rsvd_region, num_rsvd_regions); 265 } 266 267 /** 268 * find_initrd - get initrd parameters from the boot parameter structure 269 * 270 * Grab the initrd start and end from the boot parameter struct given us by 271 * the boot loader. 272 */ 273 void __init 274 find_initrd (void) 275 { 276 #ifdef CONFIG_BLK_DEV_INITRD 277 if (ia64_boot_param->initrd_start) { 278 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 279 initrd_end = initrd_start+ia64_boot_param->initrd_size; 280 281 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 282 initrd_start, ia64_boot_param->initrd_size); 283 } 284 #endif 285 } 286 287 static void __init 288 io_port_init (void) 289 { 290 unsigned long phys_iobase; 291 292 /* 293 * Set `iobase' based on the EFI memory map or, failing that, the 294 * value firmware left in ar.k0. 295 * 296 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 297 * the port's virtual address, so ia32_load_state() loads it with a 298 * user virtual address. But in ia64 mode, glibc uses the 299 * *physical* address in ar.k0 to mmap the appropriate area from 300 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 301 * cases, user-mode can only use the legacy 0-64K I/O port space. 302 * 303 * ar.k0 is not involved in kernel I/O port accesses, which can use 304 * any of the I/O port spaces and are done via MMIO using the 305 * virtual mmio_base from the appropriate io_space[]. 306 */ 307 phys_iobase = efi_get_iobase(); 308 if (!phys_iobase) { 309 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 310 printk(KERN_INFO "No I/O port range found in EFI memory map, " 311 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 312 } 313 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 314 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 315 316 /* setup legacy IO port space */ 317 io_space[0].mmio_base = ia64_iobase; 318 io_space[0].sparse = 1; 319 num_io_spaces = 1; 320 } 321 322 /** 323 * early_console_setup - setup debugging console 324 * 325 * Consoles started here require little enough setup that we can start using 326 * them very early in the boot process, either right after the machine 327 * vector initialization, or even before if the drivers can detect their hw. 328 * 329 * Returns non-zero if a console couldn't be setup. 330 */ 331 static inline int __init 332 early_console_setup (char *cmdline) 333 { 334 int earlycons = 0; 335 336 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 337 { 338 extern int sn_serial_console_early_setup(void); 339 if (!sn_serial_console_early_setup()) 340 earlycons++; 341 } 342 #endif 343 #ifdef CONFIG_EFI_PCDP 344 if (!efi_setup_pcdp_console(cmdline)) 345 earlycons++; 346 #endif 347 #ifdef CONFIG_SERIAL_8250_CONSOLE 348 if (!early_serial_console_init(cmdline)) 349 earlycons++; 350 #endif 351 352 return (earlycons) ? 0 : -1; 353 } 354 355 static inline void 356 mark_bsp_online (void) 357 { 358 #ifdef CONFIG_SMP 359 /* If we register an early console, allow CPU 0 to printk */ 360 cpu_set(smp_processor_id(), cpu_online_map); 361 #endif 362 } 363 364 #ifdef CONFIG_SMP 365 static void __init 366 check_for_logical_procs (void) 367 { 368 pal_logical_to_physical_t info; 369 s64 status; 370 371 status = ia64_pal_logical_to_phys(0, &info); 372 if (status == -1) { 373 printk(KERN_INFO "No logical to physical processor mapping " 374 "available\n"); 375 return; 376 } 377 if (status) { 378 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 379 status); 380 return; 381 } 382 /* 383 * Total number of siblings that BSP has. Though not all of them 384 * may have booted successfully. The correct number of siblings 385 * booted is in info.overview_num_log. 386 */ 387 smp_num_siblings = info.overview_tpc; 388 smp_num_cpucores = info.overview_cpp; 389 } 390 #endif 391 392 static __initdata int nomca; 393 static __init int setup_nomca(char *s) 394 { 395 nomca = 1; 396 return 0; 397 } 398 early_param("nomca", setup_nomca); 399 400 void __init 401 setup_arch (char **cmdline_p) 402 { 403 unw_init(); 404 405 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 406 407 *cmdline_p = __va(ia64_boot_param->command_line); 408 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 409 410 efi_init(); 411 io_port_init(); 412 413 parse_early_param(); 414 415 #ifdef CONFIG_IA64_GENERIC 416 machvec_init(NULL); 417 #endif 418 419 if (early_console_setup(*cmdline_p) == 0) 420 mark_bsp_online(); 421 422 #ifdef CONFIG_ACPI 423 /* Initialize the ACPI boot-time table parser */ 424 acpi_table_init(); 425 # ifdef CONFIG_ACPI_NUMA 426 acpi_numa_init(); 427 # endif 428 #else 429 # ifdef CONFIG_SMP 430 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 431 # endif 432 #endif /* CONFIG_APCI_BOOT */ 433 434 find_memory(); 435 436 /* process SAL system table: */ 437 ia64_sal_init(__va(efi.sal_systab)); 438 439 ia64_setup_printk_clock(); 440 441 #ifdef CONFIG_SMP 442 cpu_physical_id(0) = hard_smp_processor_id(); 443 444 cpu_set(0, cpu_sibling_map[0]); 445 cpu_set(0, cpu_core_map[0]); 446 447 check_for_logical_procs(); 448 if (smp_num_cpucores > 1) 449 printk(KERN_INFO 450 "cpu package is Multi-Core capable: number of cores=%d\n", 451 smp_num_cpucores); 452 if (smp_num_siblings > 1) 453 printk(KERN_INFO 454 "cpu package is Multi-Threading capable: number of siblings=%d\n", 455 smp_num_siblings); 456 #endif 457 458 cpu_init(); /* initialize the bootstrap CPU */ 459 mmu_context_init(); /* initialize context_id bitmap */ 460 461 #ifdef CONFIG_ACPI 462 acpi_boot_init(); 463 #endif 464 465 #ifdef CONFIG_VT 466 if (!conswitchp) { 467 # if defined(CONFIG_DUMMY_CONSOLE) 468 conswitchp = &dummy_con; 469 # endif 470 # if defined(CONFIG_VGA_CONSOLE) 471 /* 472 * Non-legacy systems may route legacy VGA MMIO range to system 473 * memory. vga_con probes the MMIO hole, so memory looks like 474 * a VGA device to it. The EFI memory map can tell us if it's 475 * memory so we can avoid this problem. 476 */ 477 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 478 conswitchp = &vga_con; 479 # endif 480 } 481 #endif 482 483 /* enable IA-64 Machine Check Abort Handling unless disabled */ 484 if (!nomca) 485 ia64_mca_init(); 486 487 platform_setup(cmdline_p); 488 paging_init(); 489 } 490 491 /* 492 * Display cpu info for all cpu's. 493 */ 494 static int 495 show_cpuinfo (struct seq_file *m, void *v) 496 { 497 #ifdef CONFIG_SMP 498 # define lpj c->loops_per_jiffy 499 # define cpunum c->cpu 500 #else 501 # define lpj loops_per_jiffy 502 # define cpunum 0 503 #endif 504 static struct { 505 unsigned long mask; 506 const char *feature_name; 507 } feature_bits[] = { 508 { 1UL << 0, "branchlong" }, 509 { 1UL << 1, "spontaneous deferral"}, 510 { 1UL << 2, "16-byte atomic ops" } 511 }; 512 char family[32], features[128], *cp, sep; 513 struct cpuinfo_ia64 *c = v; 514 unsigned long mask; 515 unsigned long proc_freq; 516 int i; 517 518 mask = c->features; 519 520 switch (c->family) { 521 case 0x07: memcpy(family, "Itanium", 8); break; 522 case 0x1f: memcpy(family, "Itanium 2", 10); break; 523 default: sprintf(family, "%u", c->family); break; 524 } 525 526 /* build the feature string: */ 527 memcpy(features, " standard", 10); 528 cp = features; 529 sep = 0; 530 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 531 if (mask & feature_bits[i].mask) { 532 if (sep) 533 *cp++ = sep; 534 sep = ','; 535 *cp++ = ' '; 536 strcpy(cp, feature_bits[i].feature_name); 537 cp += strlen(feature_bits[i].feature_name); 538 mask &= ~feature_bits[i].mask; 539 } 540 } 541 if (mask) { 542 /* print unknown features as a hex value: */ 543 if (sep) 544 *cp++ = sep; 545 sprintf(cp, " 0x%lx", mask); 546 } 547 548 proc_freq = cpufreq_quick_get(cpunum); 549 if (!proc_freq) 550 proc_freq = c->proc_freq / 1000; 551 552 seq_printf(m, 553 "processor : %d\n" 554 "vendor : %s\n" 555 "arch : IA-64\n" 556 "family : %s\n" 557 "model : %u\n" 558 "revision : %u\n" 559 "archrev : %u\n" 560 "features :%s\n" /* don't change this---it _is_ right! */ 561 "cpu number : %lu\n" 562 "cpu regs : %u\n" 563 "cpu MHz : %lu.%06lu\n" 564 "itc MHz : %lu.%06lu\n" 565 "BogoMIPS : %lu.%02lu\n", 566 cpunum, c->vendor, family, c->model, c->revision, c->archrev, 567 features, c->ppn, c->number, 568 proc_freq / 1000, proc_freq % 1000, 569 c->itc_freq / 1000000, c->itc_freq % 1000000, 570 lpj*HZ/500000, (lpj*HZ/5000) % 100); 571 #ifdef CONFIG_SMP 572 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 573 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 574 seq_printf(m, 575 "physical id: %u\n" 576 "core id : %u\n" 577 "thread id : %u\n", 578 c->socket_id, c->core_id, c->thread_id); 579 #endif 580 seq_printf(m,"\n"); 581 582 return 0; 583 } 584 585 static void * 586 c_start (struct seq_file *m, loff_t *pos) 587 { 588 #ifdef CONFIG_SMP 589 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 590 ++*pos; 591 #endif 592 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 593 } 594 595 static void * 596 c_next (struct seq_file *m, void *v, loff_t *pos) 597 { 598 ++*pos; 599 return c_start(m, pos); 600 } 601 602 static void 603 c_stop (struct seq_file *m, void *v) 604 { 605 } 606 607 struct seq_operations cpuinfo_op = { 608 .start = c_start, 609 .next = c_next, 610 .stop = c_stop, 611 .show = show_cpuinfo 612 }; 613 614 static void __cpuinit 615 identify_cpu (struct cpuinfo_ia64 *c) 616 { 617 union { 618 unsigned long bits[5]; 619 struct { 620 /* id 0 & 1: */ 621 char vendor[16]; 622 623 /* id 2 */ 624 u64 ppn; /* processor serial number */ 625 626 /* id 3: */ 627 unsigned number : 8; 628 unsigned revision : 8; 629 unsigned model : 8; 630 unsigned family : 8; 631 unsigned archrev : 8; 632 unsigned reserved : 24; 633 634 /* id 4: */ 635 u64 features; 636 } field; 637 } cpuid; 638 pal_vm_info_1_u_t vm1; 639 pal_vm_info_2_u_t vm2; 640 pal_status_t status; 641 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 642 int i; 643 644 for (i = 0; i < 5; ++i) 645 cpuid.bits[i] = ia64_get_cpuid(i); 646 647 memcpy(c->vendor, cpuid.field.vendor, 16); 648 #ifdef CONFIG_SMP 649 c->cpu = smp_processor_id(); 650 651 /* below default values will be overwritten by identify_siblings() 652 * for Multi-Threading/Multi-Core capable cpu's 653 */ 654 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 655 c->socket_id = -1; 656 657 identify_siblings(c); 658 #endif 659 c->ppn = cpuid.field.ppn; 660 c->number = cpuid.field.number; 661 c->revision = cpuid.field.revision; 662 c->model = cpuid.field.model; 663 c->family = cpuid.field.family; 664 c->archrev = cpuid.field.archrev; 665 c->features = cpuid.field.features; 666 667 status = ia64_pal_vm_summary(&vm1, &vm2); 668 if (status == PAL_STATUS_SUCCESS) { 669 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 670 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 671 } 672 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 673 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 674 } 675 676 void 677 setup_per_cpu_areas (void) 678 { 679 /* start_kernel() requires this... */ 680 #ifdef CONFIG_ACPI_HOTPLUG_CPU 681 prefill_possible_map(); 682 #endif 683 } 684 685 /* 686 * Calculate the max. cache line size. 687 * 688 * In addition, the minimum of the i-cache stride sizes is calculated for 689 * "flush_icache_range()". 690 */ 691 static void __cpuinit 692 get_max_cacheline_size (void) 693 { 694 unsigned long line_size, max = 1; 695 unsigned int cache_size = 0; 696 u64 l, levels, unique_caches; 697 pal_cache_config_info_t cci; 698 s64 status; 699 700 status = ia64_pal_cache_summary(&levels, &unique_caches); 701 if (status != 0) { 702 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 703 __FUNCTION__, status); 704 max = SMP_CACHE_BYTES; 705 /* Safest setup for "flush_icache_range()" */ 706 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 707 goto out; 708 } 709 710 for (l = 0; l < levels; ++l) { 711 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 712 &cci); 713 if (status != 0) { 714 printk(KERN_ERR 715 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 716 __FUNCTION__, l, status); 717 max = SMP_CACHE_BYTES; 718 /* The safest setup for "flush_icache_range()" */ 719 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 720 cci.pcci_unified = 1; 721 } 722 line_size = 1 << cci.pcci_line_size; 723 if (line_size > max) 724 max = line_size; 725 if (cache_size < cci.pcci_cache_size) 726 cache_size = cci.pcci_cache_size; 727 if (!cci.pcci_unified) { 728 status = ia64_pal_cache_config_info(l, 729 /* cache_type (instruction)= */ 1, 730 &cci); 731 if (status != 0) { 732 printk(KERN_ERR 733 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 734 __FUNCTION__, l, status); 735 /* The safest setup for "flush_icache_range()" */ 736 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 737 } 738 } 739 if (cci.pcci_stride < ia64_i_cache_stride_shift) 740 ia64_i_cache_stride_shift = cci.pcci_stride; 741 } 742 out: 743 #ifdef CONFIG_SMP 744 max_cache_size = max(max_cache_size, cache_size); 745 #endif 746 if (max > ia64_max_cacheline_size) 747 ia64_max_cacheline_size = max; 748 } 749 750 /* 751 * cpu_init() initializes state that is per-CPU. This function acts 752 * as a 'CPU state barrier', nothing should get across. 753 */ 754 void __cpuinit 755 cpu_init (void) 756 { 757 extern void __cpuinit ia64_mmu_init (void *); 758 unsigned long num_phys_stacked; 759 pal_vm_info_2_u_t vmi; 760 unsigned int max_ctx; 761 struct cpuinfo_ia64 *cpu_info; 762 void *cpu_data; 763 764 cpu_data = per_cpu_init(); 765 766 /* 767 * We set ar.k3 so that assembly code in MCA handler can compute 768 * physical addresses of per cpu variables with a simple: 769 * phys = ar.k3 + &per_cpu_var 770 */ 771 ia64_set_kr(IA64_KR_PER_CPU_DATA, 772 ia64_tpa(cpu_data) - (long) __per_cpu_start); 773 774 get_max_cacheline_size(); 775 776 /* 777 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 778 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 779 * depends on the data returned by identify_cpu(). We break the dependency by 780 * accessing cpu_data() through the canonical per-CPU address. 781 */ 782 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 783 identify_cpu(cpu_info); 784 785 #ifdef CONFIG_MCKINLEY 786 { 787 # define FEATURE_SET 16 788 struct ia64_pal_retval iprv; 789 790 if (cpu_info->family == 0x1f) { 791 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 792 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 793 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 794 (iprv.v1 | 0x80), FEATURE_SET, 0); 795 } 796 } 797 #endif 798 799 /* Clear the stack memory reserved for pt_regs: */ 800 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 801 802 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 803 804 /* 805 * Initialize the page-table base register to a global 806 * directory with all zeroes. This ensure that we can handle 807 * TLB-misses to user address-space even before we created the 808 * first user address-space. This may happen, e.g., due to 809 * aggressive use of lfetch.fault. 810 */ 811 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 812 813 /* 814 * Initialize default control register to defer speculative faults except 815 * for those arising from TLB misses, which are not deferred. The 816 * kernel MUST NOT depend on a particular setting of these bits (in other words, 817 * the kernel must have recovery code for all speculative accesses). Turn on 818 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 819 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 820 * be fine). 821 */ 822 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 823 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 824 atomic_inc(&init_mm.mm_count); 825 current->active_mm = &init_mm; 826 if (current->mm) 827 BUG(); 828 829 ia64_mmu_init(ia64_imva(cpu_data)); 830 ia64_mca_cpu_init(ia64_imva(cpu_data)); 831 832 #ifdef CONFIG_IA32_SUPPORT 833 ia32_cpu_init(); 834 #endif 835 836 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 837 ia64_set_itc(0); 838 839 /* disable all local interrupt sources: */ 840 ia64_set_itv(1 << 16); 841 ia64_set_lrr0(1 << 16); 842 ia64_set_lrr1(1 << 16); 843 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 844 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 845 846 /* clear TPR & XTP to enable all interrupt classes: */ 847 ia64_setreg(_IA64_REG_CR_TPR, 0); 848 #ifdef CONFIG_SMP 849 normal_xtp(); 850 #endif 851 852 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 853 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 854 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 855 else { 856 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 857 max_ctx = (1U << 15) - 1; /* use architected minimum */ 858 } 859 while (max_ctx < ia64_ctx.max_ctx) { 860 unsigned int old = ia64_ctx.max_ctx; 861 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 862 break; 863 } 864 865 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 866 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 867 "stacked regs\n"); 868 num_phys_stacked = 96; 869 } 870 /* size of physical stacked register partition plus 8 bytes: */ 871 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 872 platform_cpu_init(); 873 pm_idle = default_idle; 874 } 875 876 /* 877 * On SMP systems, when the scheduler does migration-cost autodetection, 878 * it needs a way to flush as much of the CPU's caches as possible. 879 */ 880 void sched_cacheflush(void) 881 { 882 ia64_sal_cache_flush(3); 883 } 884 885 void __init 886 check_bugs (void) 887 { 888 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 889 (unsigned long) __end___mckinley_e9_bundles); 890 } 891 892 static int __init run_dmi_scan(void) 893 { 894 dmi_scan_machine(); 895 return 0; 896 } 897 core_initcall(run_dmi_scan); 898