1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 */ 24 #include <linux/config.h> 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/tty.h> 39 #include <linux/serial.h> 40 #include <linux/serial_core.h> 41 #include <linux/efi.h> 42 #include <linux/initrd.h> 43 44 #include <asm/ia32.h> 45 #include <asm/machvec.h> 46 #include <asm/mca.h> 47 #include <asm/meminit.h> 48 #include <asm/page.h> 49 #include <asm/patch.h> 50 #include <asm/pgtable.h> 51 #include <asm/processor.h> 52 #include <asm/sal.h> 53 #include <asm/sections.h> 54 #include <asm/serial.h> 55 #include <asm/setup.h> 56 #include <asm/smp.h> 57 #include <asm/system.h> 58 #include <asm/unistd.h> 59 60 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 61 # error "struct cpuinfo_ia64 too big!" 62 #endif 63 64 #ifdef CONFIG_SMP 65 unsigned long __per_cpu_offset[NR_CPUS]; 66 EXPORT_SYMBOL(__per_cpu_offset); 67 #endif 68 69 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 70 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 71 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 72 unsigned long ia64_cycles_per_usec; 73 struct ia64_boot_param *ia64_boot_param; 74 struct screen_info screen_info; 75 unsigned long vga_console_iobase; 76 unsigned long vga_console_membase; 77 78 unsigned long ia64_max_cacheline_size; 79 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 80 EXPORT_SYMBOL(ia64_iobase); 81 struct io_space io_space[MAX_IO_SPACES]; 82 EXPORT_SYMBOL(io_space); 83 unsigned int num_io_spaces; 84 85 /* 86 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 87 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 88 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 89 * address of the second buffer must be aligned to (merge_mask+1) in order to be 90 * mergeable). By default, we assume there is no I/O MMU which can merge physically 91 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 92 * page-size of 2^64. 93 */ 94 unsigned long ia64_max_iommu_merge_mask = ~0UL; 95 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 96 97 /* 98 * We use a special marker for the end of memory and it uses the extra (+1) slot 99 */ 100 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1]; 101 int num_rsvd_regions; 102 103 104 /* 105 * Filter incoming memory segments based on the primitive map created from the boot 106 * parameters. Segments contained in the map are removed from the memory ranges. A 107 * caller-specified function is called with the memory ranges that remain after filtering. 108 * This routine does not assume the incoming segments are sorted. 109 */ 110 int 111 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 112 { 113 unsigned long range_start, range_end, prev_start; 114 void (*func)(unsigned long, unsigned long, int); 115 int i; 116 117 #if IGNORE_PFN0 118 if (start == PAGE_OFFSET) { 119 printk(KERN_WARNING "warning: skipping physical page 0\n"); 120 start += PAGE_SIZE; 121 if (start >= end) return 0; 122 } 123 #endif 124 /* 125 * lowest possible address(walker uses virtual) 126 */ 127 prev_start = PAGE_OFFSET; 128 func = arg; 129 130 for (i = 0; i < num_rsvd_regions; ++i) { 131 range_start = max(start, prev_start); 132 range_end = min(end, rsvd_region[i].start); 133 134 if (range_start < range_end) 135 call_pernode_memory(__pa(range_start), range_end - range_start, func); 136 137 /* nothing more available in this segment */ 138 if (range_end == end) return 0; 139 140 prev_start = rsvd_region[i].end; 141 } 142 /* end of memory marker allows full processing inside loop body */ 143 return 0; 144 } 145 146 static void 147 sort_regions (struct rsvd_region *rsvd_region, int max) 148 { 149 int j; 150 151 /* simple bubble sorting */ 152 while (max--) { 153 for (j = 0; j < max; ++j) { 154 if (rsvd_region[j].start > rsvd_region[j+1].start) { 155 struct rsvd_region tmp; 156 tmp = rsvd_region[j]; 157 rsvd_region[j] = rsvd_region[j + 1]; 158 rsvd_region[j + 1] = tmp; 159 } 160 } 161 } 162 } 163 164 /** 165 * reserve_memory - setup reserved memory areas 166 * 167 * Setup the reserved memory areas set aside for the boot parameters, 168 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 169 * see include/asm-ia64/meminit.h if you need to define more. 170 */ 171 void 172 reserve_memory (void) 173 { 174 int n = 0; 175 176 /* 177 * none of the entries in this table overlap 178 */ 179 rsvd_region[n].start = (unsigned long) ia64_boot_param; 180 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 181 n++; 182 183 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 184 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 185 n++; 186 187 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 188 rsvd_region[n].end = (rsvd_region[n].start 189 + strlen(__va(ia64_boot_param->command_line)) + 1); 190 n++; 191 192 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 193 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 194 n++; 195 196 #ifdef CONFIG_BLK_DEV_INITRD 197 if (ia64_boot_param->initrd_start) { 198 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 199 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 200 n++; 201 } 202 #endif 203 204 /* end of memory marker */ 205 rsvd_region[n].start = ~0UL; 206 rsvd_region[n].end = ~0UL; 207 n++; 208 209 num_rsvd_regions = n; 210 211 sort_regions(rsvd_region, num_rsvd_regions); 212 } 213 214 /** 215 * find_initrd - get initrd parameters from the boot parameter structure 216 * 217 * Grab the initrd start and end from the boot parameter struct given us by 218 * the boot loader. 219 */ 220 void 221 find_initrd (void) 222 { 223 #ifdef CONFIG_BLK_DEV_INITRD 224 if (ia64_boot_param->initrd_start) { 225 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 226 initrd_end = initrd_start+ia64_boot_param->initrd_size; 227 228 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 229 initrd_start, ia64_boot_param->initrd_size); 230 } 231 #endif 232 } 233 234 static void __init 235 io_port_init (void) 236 { 237 extern unsigned long ia64_iobase; 238 unsigned long phys_iobase; 239 240 /* 241 * Set `iobase' to the appropriate address in region 6 (uncached access range). 242 * 243 * The EFI memory map is the "preferred" location to get the I/O port space base, 244 * rather the relying on AR.KR0. This should become more clear in future SAL 245 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is 246 * found in the memory map. 247 */ 248 phys_iobase = efi_get_iobase(); 249 if (phys_iobase) 250 /* set AR.KR0 since this is all we use it for anyway */ 251 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase); 252 else { 253 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 254 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back " 255 "to AR.KR0\n"); 256 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase); 257 } 258 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 259 260 /* setup legacy IO port space */ 261 io_space[0].mmio_base = ia64_iobase; 262 io_space[0].sparse = 1; 263 num_io_spaces = 1; 264 } 265 266 /** 267 * early_console_setup - setup debugging console 268 * 269 * Consoles started here require little enough setup that we can start using 270 * them very early in the boot process, either right after the machine 271 * vector initialization, or even before if the drivers can detect their hw. 272 * 273 * Returns non-zero if a console couldn't be setup. 274 */ 275 static inline int __init 276 early_console_setup (char *cmdline) 277 { 278 int earlycons = 0; 279 280 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 281 { 282 extern int sn_serial_console_early_setup(void); 283 if (!sn_serial_console_early_setup()) 284 earlycons++; 285 } 286 #endif 287 #ifdef CONFIG_EFI_PCDP 288 if (!efi_setup_pcdp_console(cmdline)) 289 earlycons++; 290 #endif 291 #ifdef CONFIG_SERIAL_8250_CONSOLE 292 if (!early_serial_console_init(cmdline)) 293 earlycons++; 294 #endif 295 296 return (earlycons) ? 0 : -1; 297 } 298 299 static inline void 300 mark_bsp_online (void) 301 { 302 #ifdef CONFIG_SMP 303 /* If we register an early console, allow CPU 0 to printk */ 304 cpu_set(smp_processor_id(), cpu_online_map); 305 #endif 306 } 307 308 #ifdef CONFIG_SMP 309 static void 310 check_for_logical_procs (void) 311 { 312 pal_logical_to_physical_t info; 313 s64 status; 314 315 status = ia64_pal_logical_to_phys(0, &info); 316 if (status == -1) { 317 printk(KERN_INFO "No logical to physical processor mapping " 318 "available\n"); 319 return; 320 } 321 if (status) { 322 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 323 status); 324 return; 325 } 326 /* 327 * Total number of siblings that BSP has. Though not all of them 328 * may have booted successfully. The correct number of siblings 329 * booted is in info.overview_num_log. 330 */ 331 smp_num_siblings = info.overview_tpc; 332 smp_num_cpucores = info.overview_cpp; 333 } 334 #endif 335 336 void __init 337 setup_arch (char **cmdline_p) 338 { 339 unw_init(); 340 341 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 342 343 *cmdline_p = __va(ia64_boot_param->command_line); 344 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 345 346 efi_init(); 347 io_port_init(); 348 349 #ifdef CONFIG_IA64_GENERIC 350 { 351 const char *mvec_name = strstr (*cmdline_p, "machvec="); 352 char str[64]; 353 354 if (mvec_name) { 355 const char *end; 356 size_t len; 357 358 mvec_name += 8; 359 end = strchr (mvec_name, ' '); 360 if (end) 361 len = end - mvec_name; 362 else 363 len = strlen (mvec_name); 364 len = min(len, sizeof (str) - 1); 365 strncpy (str, mvec_name, len); 366 str[len] = '\0'; 367 mvec_name = str; 368 } else 369 mvec_name = acpi_get_sysname(); 370 machvec_init(mvec_name); 371 } 372 #endif 373 374 if (early_console_setup(*cmdline_p) == 0) 375 mark_bsp_online(); 376 377 #ifdef CONFIG_ACPI_BOOT 378 /* Initialize the ACPI boot-time table parser */ 379 acpi_table_init(); 380 # ifdef CONFIG_ACPI_NUMA 381 acpi_numa_init(); 382 # endif 383 #else 384 # ifdef CONFIG_SMP 385 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 386 # endif 387 #endif /* CONFIG_APCI_BOOT */ 388 389 find_memory(); 390 391 /* process SAL system table: */ 392 ia64_sal_init(efi.sal_systab); 393 394 #ifdef CONFIG_SMP 395 cpu_physical_id(0) = hard_smp_processor_id(); 396 397 cpu_set(0, cpu_sibling_map[0]); 398 cpu_set(0, cpu_core_map[0]); 399 400 check_for_logical_procs(); 401 if (smp_num_cpucores > 1) 402 printk(KERN_INFO 403 "cpu package is Multi-Core capable: number of cores=%d\n", 404 smp_num_cpucores); 405 if (smp_num_siblings > 1) 406 printk(KERN_INFO 407 "cpu package is Multi-Threading capable: number of siblings=%d\n", 408 smp_num_siblings); 409 #endif 410 411 cpu_init(); /* initialize the bootstrap CPU */ 412 413 #ifdef CONFIG_ACPI_BOOT 414 acpi_boot_init(); 415 #endif 416 417 #ifdef CONFIG_VT 418 if (!conswitchp) { 419 # if defined(CONFIG_DUMMY_CONSOLE) 420 conswitchp = &dummy_con; 421 # endif 422 # if defined(CONFIG_VGA_CONSOLE) 423 /* 424 * Non-legacy systems may route legacy VGA MMIO range to system 425 * memory. vga_con probes the MMIO hole, so memory looks like 426 * a VGA device to it. The EFI memory map can tell us if it's 427 * memory so we can avoid this problem. 428 */ 429 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 430 conswitchp = &vga_con; 431 # endif 432 } 433 #endif 434 435 /* enable IA-64 Machine Check Abort Handling unless disabled */ 436 if (!strstr(saved_command_line, "nomca")) 437 ia64_mca_init(); 438 439 platform_setup(cmdline_p); 440 paging_init(); 441 } 442 443 /* 444 * Display cpu info for all cpu's. 445 */ 446 static int 447 show_cpuinfo (struct seq_file *m, void *v) 448 { 449 #ifdef CONFIG_SMP 450 # define lpj c->loops_per_jiffy 451 # define cpunum c->cpu 452 #else 453 # define lpj loops_per_jiffy 454 # define cpunum 0 455 #endif 456 static struct { 457 unsigned long mask; 458 const char *feature_name; 459 } feature_bits[] = { 460 { 1UL << 0, "branchlong" }, 461 { 1UL << 1, "spontaneous deferral"}, 462 { 1UL << 2, "16-byte atomic ops" } 463 }; 464 char family[32], features[128], *cp, sep; 465 struct cpuinfo_ia64 *c = v; 466 unsigned long mask; 467 int i; 468 469 mask = c->features; 470 471 switch (c->family) { 472 case 0x07: memcpy(family, "Itanium", 8); break; 473 case 0x1f: memcpy(family, "Itanium 2", 10); break; 474 default: sprintf(family, "%u", c->family); break; 475 } 476 477 /* build the feature string: */ 478 memcpy(features, " standard", 10); 479 cp = features; 480 sep = 0; 481 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 482 if (mask & feature_bits[i].mask) { 483 if (sep) 484 *cp++ = sep; 485 sep = ','; 486 *cp++ = ' '; 487 strcpy(cp, feature_bits[i].feature_name); 488 cp += strlen(feature_bits[i].feature_name); 489 mask &= ~feature_bits[i].mask; 490 } 491 } 492 if (mask) { 493 /* print unknown features as a hex value: */ 494 if (sep) 495 *cp++ = sep; 496 sprintf(cp, " 0x%lx", mask); 497 } 498 499 seq_printf(m, 500 "processor : %d\n" 501 "vendor : %s\n" 502 "arch : IA-64\n" 503 "family : %s\n" 504 "model : %u\n" 505 "revision : %u\n" 506 "archrev : %u\n" 507 "features :%s\n" /* don't change this---it _is_ right! */ 508 "cpu number : %lu\n" 509 "cpu regs : %u\n" 510 "cpu MHz : %lu.%06lu\n" 511 "itc MHz : %lu.%06lu\n" 512 "BogoMIPS : %lu.%02lu\n", 513 cpunum, c->vendor, family, c->model, c->revision, c->archrev, 514 features, c->ppn, c->number, 515 c->proc_freq / 1000000, c->proc_freq % 1000000, 516 c->itc_freq / 1000000, c->itc_freq % 1000000, 517 lpj*HZ/500000, (lpj*HZ/5000) % 100); 518 #ifdef CONFIG_SMP 519 seq_printf(m, "siblings : %u\n", c->num_log); 520 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 521 seq_printf(m, 522 "physical id: %u\n" 523 "core id : %u\n" 524 "thread id : %u\n", 525 c->socket_id, c->core_id, c->thread_id); 526 #endif 527 seq_printf(m,"\n"); 528 529 return 0; 530 } 531 532 static void * 533 c_start (struct seq_file *m, loff_t *pos) 534 { 535 #ifdef CONFIG_SMP 536 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 537 ++*pos; 538 #endif 539 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 540 } 541 542 static void * 543 c_next (struct seq_file *m, void *v, loff_t *pos) 544 { 545 ++*pos; 546 return c_start(m, pos); 547 } 548 549 static void 550 c_stop (struct seq_file *m, void *v) 551 { 552 } 553 554 struct seq_operations cpuinfo_op = { 555 .start = c_start, 556 .next = c_next, 557 .stop = c_stop, 558 .show = show_cpuinfo 559 }; 560 561 void 562 identify_cpu (struct cpuinfo_ia64 *c) 563 { 564 union { 565 unsigned long bits[5]; 566 struct { 567 /* id 0 & 1: */ 568 char vendor[16]; 569 570 /* id 2 */ 571 u64 ppn; /* processor serial number */ 572 573 /* id 3: */ 574 unsigned number : 8; 575 unsigned revision : 8; 576 unsigned model : 8; 577 unsigned family : 8; 578 unsigned archrev : 8; 579 unsigned reserved : 24; 580 581 /* id 4: */ 582 u64 features; 583 } field; 584 } cpuid; 585 pal_vm_info_1_u_t vm1; 586 pal_vm_info_2_u_t vm2; 587 pal_status_t status; 588 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 589 int i; 590 591 for (i = 0; i < 5; ++i) 592 cpuid.bits[i] = ia64_get_cpuid(i); 593 594 memcpy(c->vendor, cpuid.field.vendor, 16); 595 #ifdef CONFIG_SMP 596 c->cpu = smp_processor_id(); 597 598 /* below default values will be overwritten by identify_siblings() 599 * for Multi-Threading/Multi-Core capable cpu's 600 */ 601 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 602 c->socket_id = -1; 603 604 identify_siblings(c); 605 #endif 606 c->ppn = cpuid.field.ppn; 607 c->number = cpuid.field.number; 608 c->revision = cpuid.field.revision; 609 c->model = cpuid.field.model; 610 c->family = cpuid.field.family; 611 c->archrev = cpuid.field.archrev; 612 c->features = cpuid.field.features; 613 614 status = ia64_pal_vm_summary(&vm1, &vm2); 615 if (status == PAL_STATUS_SUCCESS) { 616 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 617 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 618 } 619 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 620 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 621 } 622 623 void 624 setup_per_cpu_areas (void) 625 { 626 /* start_kernel() requires this... */ 627 } 628 629 static void 630 get_max_cacheline_size (void) 631 { 632 unsigned long line_size, max = 1; 633 u64 l, levels, unique_caches; 634 pal_cache_config_info_t cci; 635 s64 status; 636 637 status = ia64_pal_cache_summary(&levels, &unique_caches); 638 if (status != 0) { 639 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 640 __FUNCTION__, status); 641 max = SMP_CACHE_BYTES; 642 goto out; 643 } 644 645 for (l = 0; l < levels; ++l) { 646 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 647 &cci); 648 if (status != 0) { 649 printk(KERN_ERR 650 "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n", 651 __FUNCTION__, l, status); 652 max = SMP_CACHE_BYTES; 653 } 654 line_size = 1 << cci.pcci_line_size; 655 if (line_size > max) 656 max = line_size; 657 } 658 out: 659 if (max > ia64_max_cacheline_size) 660 ia64_max_cacheline_size = max; 661 } 662 663 /* 664 * cpu_init() initializes state that is per-CPU. This function acts 665 * as a 'CPU state barrier', nothing should get across. 666 */ 667 void 668 cpu_init (void) 669 { 670 extern void __devinit ia64_mmu_init (void *); 671 unsigned long num_phys_stacked; 672 pal_vm_info_2_u_t vmi; 673 unsigned int max_ctx; 674 struct cpuinfo_ia64 *cpu_info; 675 void *cpu_data; 676 677 cpu_data = per_cpu_init(); 678 679 /* 680 * We set ar.k3 so that assembly code in MCA handler can compute 681 * physical addresses of per cpu variables with a simple: 682 * phys = ar.k3 + &per_cpu_var 683 */ 684 ia64_set_kr(IA64_KR_PER_CPU_DATA, 685 ia64_tpa(cpu_data) - (long) __per_cpu_start); 686 687 get_max_cacheline_size(); 688 689 /* 690 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 691 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 692 * depends on the data returned by identify_cpu(). We break the dependency by 693 * accessing cpu_data() through the canonical per-CPU address. 694 */ 695 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 696 identify_cpu(cpu_info); 697 698 #ifdef CONFIG_MCKINLEY 699 { 700 # define FEATURE_SET 16 701 struct ia64_pal_retval iprv; 702 703 if (cpu_info->family == 0x1f) { 704 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 705 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 706 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 707 (iprv.v1 | 0x80), FEATURE_SET, 0); 708 } 709 } 710 #endif 711 712 /* Clear the stack memory reserved for pt_regs: */ 713 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs)); 714 715 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 716 717 /* 718 * Initialize the page-table base register to a global 719 * directory with all zeroes. This ensure that we can handle 720 * TLB-misses to user address-space even before we created the 721 * first user address-space. This may happen, e.g., due to 722 * aggressive use of lfetch.fault. 723 */ 724 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 725 726 /* 727 * Initialize default control register to defer speculative faults except 728 * for those arising from TLB misses, which are not deferred. The 729 * kernel MUST NOT depend on a particular setting of these bits (in other words, 730 * the kernel must have recovery code for all speculative accesses). Turn on 731 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 732 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 733 * be fine). 734 */ 735 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 736 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 737 atomic_inc(&init_mm.mm_count); 738 current->active_mm = &init_mm; 739 if (current->mm) 740 BUG(); 741 742 ia64_mmu_init(ia64_imva(cpu_data)); 743 ia64_mca_cpu_init(ia64_imva(cpu_data)); 744 745 #ifdef CONFIG_IA32_SUPPORT 746 ia32_cpu_init(); 747 #endif 748 749 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 750 ia64_set_itc(0); 751 752 /* disable all local interrupt sources: */ 753 ia64_set_itv(1 << 16); 754 ia64_set_lrr0(1 << 16); 755 ia64_set_lrr1(1 << 16); 756 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 757 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 758 759 /* clear TPR & XTP to enable all interrupt classes: */ 760 ia64_setreg(_IA64_REG_CR_TPR, 0); 761 #ifdef CONFIG_SMP 762 normal_xtp(); 763 #endif 764 765 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 766 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 767 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 768 else { 769 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 770 max_ctx = (1U << 15) - 1; /* use architected minimum */ 771 } 772 while (max_ctx < ia64_ctx.max_ctx) { 773 unsigned int old = ia64_ctx.max_ctx; 774 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 775 break; 776 } 777 778 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 779 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 780 "stacked regs\n"); 781 num_phys_stacked = 96; 782 } 783 /* size of physical stacked register partition plus 8 bytes: */ 784 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 785 platform_cpu_init(); 786 } 787 788 void 789 check_bugs (void) 790 { 791 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 792 (unsigned long) __end___mckinley_e9_bundles); 793 } 794