1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Architecture-specific setup. 4 * 5 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * Stephane Eranian <eranian@hpl.hp.com> 8 * Copyright (C) 2000, 2004 Intel Corp 9 * Rohit Seth <rohit.seth@intel.com> 10 * Suresh Siddha <suresh.b.siddha@intel.com> 11 * Gordon Jin <gordon.jin@intel.com> 12 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * 15 * 12/26/04 S.Siddha, G.Jin, R.Seth 16 * Add multi-threading and multi-core detection 17 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 18 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 19 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 20 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 21 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 22 * 01/07/99 S.Eranian added the support for command line argument 23 * 06/24/99 W.Drummond added boot_cpu_data. 24 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 25 */ 26 #include <linux/module.h> 27 #include <linux/init.h> 28 #include <linux/pgtable.h> 29 30 #include <linux/acpi.h> 31 #include <linux/console.h> 32 #include <linux/delay.h> 33 #include <linux/cpu.h> 34 #include <linux/kdev_t.h> 35 #include <linux/kernel.h> 36 #include <linux/memblock.h> 37 #include <linux/reboot.h> 38 #include <linux/sched/mm.h> 39 #include <linux/sched/clock.h> 40 #include <linux/sched/task_stack.h> 41 #include <linux/seq_file.h> 42 #include <linux/string.h> 43 #include <linux/threads.h> 44 #include <linux/screen_info.h> 45 #include <linux/dmi.h> 46 #include <linux/root_dev.h> 47 #include <linux/serial.h> 48 #include <linux/serial_core.h> 49 #include <linux/efi.h> 50 #include <linux/initrd.h> 51 #include <linux/pm.h> 52 #include <linux/cpufreq.h> 53 #include <linux/kexec.h> 54 #include <linux/crash_dump.h> 55 56 #include <asm/mca.h> 57 #include <asm/meminit.h> 58 #include <asm/page.h> 59 #include <asm/patch.h> 60 #include <asm/processor.h> 61 #include <asm/sal.h> 62 #include <asm/sections.h> 63 #include <asm/setup.h> 64 #include <asm/smp.h> 65 #include <asm/tlbflush.h> 66 #include <asm/unistd.h> 67 #include <asm/uv/uv.h> 68 #include <asm/xtp.h> 69 70 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 71 # error "struct cpuinfo_ia64 too big!" 72 #endif 73 74 char ia64_platform_name[64]; 75 76 #ifdef CONFIG_SMP 77 unsigned long __per_cpu_offset[NR_CPUS]; 78 EXPORT_SYMBOL(__per_cpu_offset); 79 #endif 80 81 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 82 EXPORT_SYMBOL(ia64_cpu_info); 83 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 84 #ifdef CONFIG_SMP 85 EXPORT_SYMBOL(local_per_cpu_offset); 86 #endif 87 unsigned long ia64_cycles_per_usec; 88 struct ia64_boot_param *ia64_boot_param; 89 struct screen_info screen_info; 90 unsigned long vga_console_iobase; 91 unsigned long vga_console_membase; 92 93 static struct resource data_resource = { 94 .name = "Kernel data", 95 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 96 }; 97 98 static struct resource code_resource = { 99 .name = "Kernel code", 100 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 101 }; 102 103 static struct resource bss_resource = { 104 .name = "Kernel bss", 105 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 106 }; 107 108 unsigned long ia64_max_cacheline_size; 109 110 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 111 EXPORT_SYMBOL(ia64_iobase); 112 struct io_space io_space[MAX_IO_SPACES]; 113 EXPORT_SYMBOL(io_space); 114 unsigned int num_io_spaces; 115 116 /* 117 * "flush_icache_range()" needs to know what processor dependent stride size to use 118 * when it makes i-cache(s) coherent with d-caches. 119 */ 120 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 121 unsigned long ia64_i_cache_stride_shift = ~0; 122 /* 123 * "clflush_cache_range()" needs to know what processor dependent stride size to 124 * use when it flushes cache lines including both d-cache and i-cache. 125 */ 126 /* Safest way to go: 32 bytes by 32 bytes */ 127 #define CACHE_STRIDE_SHIFT 5 128 unsigned long ia64_cache_stride_shift = ~0; 129 130 /* 131 * We use a special marker for the end of memory and it uses the extra (+1) slot 132 */ 133 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 134 static int num_rsvd_regions __initdata; 135 136 137 /* 138 * Filter incoming memory segments based on the primitive map created from the boot 139 * parameters. Segments contained in the map are removed from the memory ranges. A 140 * caller-specified function is called with the memory ranges that remain after filtering. 141 * This routine does not assume the incoming segments are sorted. 142 */ 143 int __init 144 filter_rsvd_memory (u64 start, u64 end, void *arg) 145 { 146 u64 range_start, range_end, prev_start; 147 void (*func)(unsigned long, unsigned long, int); 148 int i; 149 150 #if IGNORE_PFN0 151 if (start == PAGE_OFFSET) { 152 printk(KERN_WARNING "warning: skipping physical page 0\n"); 153 start += PAGE_SIZE; 154 if (start >= end) return 0; 155 } 156 #endif 157 /* 158 * lowest possible address(walker uses virtual) 159 */ 160 prev_start = PAGE_OFFSET; 161 func = arg; 162 163 for (i = 0; i < num_rsvd_regions; ++i) { 164 range_start = max(start, prev_start); 165 range_end = min(end, rsvd_region[i].start); 166 167 if (range_start < range_end) 168 call_pernode_memory(__pa(range_start), range_end - range_start, func); 169 170 /* nothing more available in this segment */ 171 if (range_end == end) return 0; 172 173 prev_start = rsvd_region[i].end; 174 } 175 /* end of memory marker allows full processing inside loop body */ 176 return 0; 177 } 178 179 /* 180 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 181 * are not filtered out. 182 */ 183 int __init 184 filter_memory(u64 start, u64 end, void *arg) 185 { 186 void (*func)(unsigned long, unsigned long, int); 187 188 #if IGNORE_PFN0 189 if (start == PAGE_OFFSET) { 190 printk(KERN_WARNING "warning: skipping physical page 0\n"); 191 start += PAGE_SIZE; 192 if (start >= end) 193 return 0; 194 } 195 #endif 196 func = arg; 197 if (start < end) 198 call_pernode_memory(__pa(start), end - start, func); 199 return 0; 200 } 201 202 static void __init 203 sort_regions (struct rsvd_region *rsvd_region, int max) 204 { 205 int j; 206 207 /* simple bubble sorting */ 208 while (max--) { 209 for (j = 0; j < max; ++j) { 210 if (rsvd_region[j].start > rsvd_region[j+1].start) { 211 swap(rsvd_region[j], rsvd_region[j + 1]); 212 } 213 } 214 } 215 } 216 217 /* merge overlaps */ 218 static int __init 219 merge_regions (struct rsvd_region *rsvd_region, int max) 220 { 221 int i; 222 for (i = 1; i < max; ++i) { 223 if (rsvd_region[i].start >= rsvd_region[i-1].end) 224 continue; 225 if (rsvd_region[i].end > rsvd_region[i-1].end) 226 rsvd_region[i-1].end = rsvd_region[i].end; 227 --max; 228 memmove(&rsvd_region[i], &rsvd_region[i+1], 229 (max - i) * sizeof(struct rsvd_region)); 230 } 231 return max; 232 } 233 234 /* 235 * Request address space for all standard resources 236 */ 237 static int __init register_memory(void) 238 { 239 code_resource.start = ia64_tpa(_text); 240 code_resource.end = ia64_tpa(_etext) - 1; 241 data_resource.start = ia64_tpa(_etext); 242 data_resource.end = ia64_tpa(_edata) - 1; 243 bss_resource.start = ia64_tpa(__bss_start); 244 bss_resource.end = ia64_tpa(_end) - 1; 245 efi_initialize_iomem_resources(&code_resource, &data_resource, 246 &bss_resource); 247 248 return 0; 249 } 250 251 __initcall(register_memory); 252 253 254 #ifdef CONFIG_KEXEC 255 256 /* 257 * This function checks if the reserved crashkernel is allowed on the specific 258 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 259 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 260 * kernel/dma/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 261 * in kdump case. See the comment in sba_init() in sba_iommu.c. 262 * 263 * So, the only machvec that really supports loading the kdump kernel 264 * over 4 GB is "uv". 265 */ 266 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 267 { 268 if (is_uv_system()) 269 return 1; 270 else 271 return pbase < (1UL << 32); 272 } 273 274 static void __init setup_crashkernel(unsigned long total, int *n) 275 { 276 unsigned long long base = 0, size = 0; 277 int ret; 278 279 ret = parse_crashkernel(boot_command_line, total, 280 &size, &base); 281 if (ret == 0 && size > 0) { 282 if (!base) { 283 sort_regions(rsvd_region, *n); 284 *n = merge_regions(rsvd_region, *n); 285 base = kdump_find_rsvd_region(size, 286 rsvd_region, *n); 287 } 288 289 if (!check_crashkernel_memory(base, size)) { 290 pr_warn("crashkernel: There would be kdump memory " 291 "at %ld GB but this is unusable because it " 292 "must\nbe below 4 GB. Change the memory " 293 "configuration of the machine.\n", 294 (unsigned long)(base >> 30)); 295 return; 296 } 297 298 if (base != ~0UL) { 299 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 300 "for crashkernel (System RAM: %ldMB)\n", 301 (unsigned long)(size >> 20), 302 (unsigned long)(base >> 20), 303 (unsigned long)(total >> 20)); 304 rsvd_region[*n].start = 305 (unsigned long)__va(base); 306 rsvd_region[*n].end = 307 (unsigned long)__va(base + size); 308 (*n)++; 309 crashk_res.start = base; 310 crashk_res.end = base + size - 1; 311 } 312 } 313 efi_memmap_res.start = ia64_boot_param->efi_memmap; 314 efi_memmap_res.end = efi_memmap_res.start + 315 ia64_boot_param->efi_memmap_size; 316 boot_param_res.start = __pa(ia64_boot_param); 317 boot_param_res.end = boot_param_res.start + 318 sizeof(*ia64_boot_param); 319 } 320 #else 321 static inline void __init setup_crashkernel(unsigned long total, int *n) 322 {} 323 #endif 324 325 #ifdef CONFIG_CRASH_DUMP 326 static int __init reserve_elfcorehdr(u64 *start, u64 *end) 327 { 328 u64 length; 329 330 /* We get the address using the kernel command line, 331 * but the size is extracted from the EFI tables. 332 * Both address and size are required for reservation 333 * to work properly. 334 */ 335 336 if (!is_vmcore_usable()) 337 return -EINVAL; 338 339 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 340 vmcore_unusable(); 341 return -EINVAL; 342 } 343 344 *start = (unsigned long)__va(elfcorehdr_addr); 345 *end = *start + length; 346 return 0; 347 } 348 #endif /* CONFIG_CRASH_DUMP */ 349 350 /** 351 * reserve_memory - setup reserved memory areas 352 * 353 * Setup the reserved memory areas set aside for the boot parameters, 354 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 355 * see arch/ia64/include/asm/meminit.h if you need to define more. 356 */ 357 void __init 358 reserve_memory (void) 359 { 360 int n = 0; 361 unsigned long total_memory; 362 363 /* 364 * none of the entries in this table overlap 365 */ 366 rsvd_region[n].start = (unsigned long) ia64_boot_param; 367 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 368 n++; 369 370 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 371 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 372 n++; 373 374 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 375 rsvd_region[n].end = (rsvd_region[n].start 376 + strlen(__va(ia64_boot_param->command_line)) + 1); 377 n++; 378 379 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 380 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 381 n++; 382 383 #ifdef CONFIG_BLK_DEV_INITRD 384 if (ia64_boot_param->initrd_start) { 385 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 386 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 387 n++; 388 } 389 #endif 390 391 #ifdef CONFIG_CRASH_DUMP 392 if (reserve_elfcorehdr(&rsvd_region[n].start, 393 &rsvd_region[n].end) == 0) 394 n++; 395 #endif 396 397 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 398 n++; 399 400 setup_crashkernel(total_memory, &n); 401 402 /* end of memory marker */ 403 rsvd_region[n].start = ~0UL; 404 rsvd_region[n].end = ~0UL; 405 n++; 406 407 num_rsvd_regions = n; 408 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 409 410 sort_regions(rsvd_region, num_rsvd_regions); 411 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions); 412 413 /* reserve all regions except the end of memory marker with memblock */ 414 for (n = 0; n < num_rsvd_regions - 1; n++) { 415 struct rsvd_region *region = &rsvd_region[n]; 416 phys_addr_t addr = __pa(region->start); 417 phys_addr_t size = region->end - region->start; 418 419 memblock_reserve(addr, size); 420 } 421 } 422 423 /** 424 * find_initrd - get initrd parameters from the boot parameter structure 425 * 426 * Grab the initrd start and end from the boot parameter struct given us by 427 * the boot loader. 428 */ 429 void __init 430 find_initrd (void) 431 { 432 #ifdef CONFIG_BLK_DEV_INITRD 433 if (ia64_boot_param->initrd_start) { 434 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 435 initrd_end = initrd_start+ia64_boot_param->initrd_size; 436 437 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 438 initrd_start, ia64_boot_param->initrd_size); 439 } 440 #endif 441 } 442 443 static void __init 444 io_port_init (void) 445 { 446 unsigned long phys_iobase; 447 448 /* 449 * Set `iobase' based on the EFI memory map or, failing that, the 450 * value firmware left in ar.k0. 451 * 452 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 453 * the port's virtual address, so ia32_load_state() loads it with a 454 * user virtual address. But in ia64 mode, glibc uses the 455 * *physical* address in ar.k0 to mmap the appropriate area from 456 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 457 * cases, user-mode can only use the legacy 0-64K I/O port space. 458 * 459 * ar.k0 is not involved in kernel I/O port accesses, which can use 460 * any of the I/O port spaces and are done via MMIO using the 461 * virtual mmio_base from the appropriate io_space[]. 462 */ 463 phys_iobase = efi_get_iobase(); 464 if (!phys_iobase) { 465 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 466 printk(KERN_INFO "No I/O port range found in EFI memory map, " 467 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 468 } 469 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 470 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 471 472 /* setup legacy IO port space */ 473 io_space[0].mmio_base = ia64_iobase; 474 io_space[0].sparse = 1; 475 num_io_spaces = 1; 476 } 477 478 /** 479 * early_console_setup - setup debugging console 480 * 481 * Consoles started here require little enough setup that we can start using 482 * them very early in the boot process, either right after the machine 483 * vector initialization, or even before if the drivers can detect their hw. 484 * 485 * Returns non-zero if a console couldn't be setup. 486 */ 487 static inline int __init 488 early_console_setup (char *cmdline) 489 { 490 #ifdef CONFIG_EFI_PCDP 491 if (!efi_setup_pcdp_console(cmdline)) 492 return 0; 493 #endif 494 return -1; 495 } 496 497 static void __init 498 screen_info_setup(void) 499 { 500 unsigned int orig_x, orig_y, num_cols, num_rows, font_height; 501 502 memset(&screen_info, 0, sizeof(screen_info)); 503 504 if (!ia64_boot_param->console_info.num_rows || 505 !ia64_boot_param->console_info.num_cols) { 506 printk(KERN_WARNING "invalid screen-info, guessing 80x25\n"); 507 orig_x = 0; 508 orig_y = 0; 509 num_cols = 80; 510 num_rows = 25; 511 font_height = 16; 512 } else { 513 orig_x = ia64_boot_param->console_info.orig_x; 514 orig_y = ia64_boot_param->console_info.orig_y; 515 num_cols = ia64_boot_param->console_info.num_cols; 516 num_rows = ia64_boot_param->console_info.num_rows; 517 font_height = 400 / num_rows; 518 } 519 520 screen_info.orig_x = orig_x; 521 screen_info.orig_y = orig_y; 522 screen_info.orig_video_cols = num_cols; 523 screen_info.orig_video_lines = num_rows; 524 screen_info.orig_video_points = font_height; 525 screen_info.orig_video_mode = 3; /* XXX fake */ 526 screen_info.orig_video_isVGA = 1; /* XXX fake */ 527 screen_info.orig_video_ega_bx = 3; /* XXX fake */ 528 } 529 530 static inline void 531 mark_bsp_online (void) 532 { 533 #ifdef CONFIG_SMP 534 /* If we register an early console, allow CPU 0 to printk */ 535 set_cpu_online(smp_processor_id(), true); 536 #endif 537 } 538 539 static __initdata int nomca; 540 static __init int setup_nomca(char *s) 541 { 542 nomca = 1; 543 return 0; 544 } 545 early_param("nomca", setup_nomca); 546 547 void __init 548 setup_arch (char **cmdline_p) 549 { 550 unw_init(); 551 552 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 553 554 *cmdline_p = __va(ia64_boot_param->command_line); 555 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 556 557 efi_init(); 558 io_port_init(); 559 560 uv_probe_system_type(); 561 parse_early_param(); 562 563 if (early_console_setup(*cmdline_p) == 0) 564 mark_bsp_online(); 565 566 /* Initialize the ACPI boot-time table parser */ 567 acpi_table_init(); 568 early_acpi_boot_init(); 569 #ifdef CONFIG_ACPI_NUMA 570 acpi_numa_init(); 571 acpi_numa_fixup(); 572 #ifdef CONFIG_ACPI_HOTPLUG_CPU 573 prefill_possible_map(); 574 #endif 575 per_cpu_scan_finalize((cpumask_empty(&early_cpu_possible_map) ? 576 32 : cpumask_weight(&early_cpu_possible_map)), 577 additional_cpus > 0 ? additional_cpus : 0); 578 #endif /* CONFIG_ACPI_NUMA */ 579 580 #ifdef CONFIG_SMP 581 smp_build_cpu_map(); 582 #endif 583 find_memory(); 584 585 /* process SAL system table: */ 586 ia64_sal_init(__va(sal_systab_phys)); 587 588 #ifdef CONFIG_ITANIUM 589 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 590 #else 591 { 592 unsigned long num_phys_stacked; 593 594 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 595 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 596 } 597 #endif 598 599 #ifdef CONFIG_SMP 600 cpu_physical_id(0) = hard_smp_processor_id(); 601 #endif 602 603 cpu_init(); /* initialize the bootstrap CPU */ 604 mmu_context_init(); /* initialize context_id bitmap */ 605 606 #ifdef CONFIG_VT 607 if (!conswitchp) { 608 # if defined(CONFIG_VGA_CONSOLE) 609 /* 610 * Non-legacy systems may route legacy VGA MMIO range to system 611 * memory. vga_con probes the MMIO hole, so memory looks like 612 * a VGA device to it. The EFI memory map can tell us if it's 613 * memory so we can avoid this problem. 614 */ 615 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 616 conswitchp = &vga_con; 617 # endif 618 } 619 #endif 620 621 /* enable IA-64 Machine Check Abort Handling unless disabled */ 622 if (!nomca) 623 ia64_mca_init(); 624 625 /* 626 * Default to /dev/sda2. This assumes that the EFI partition 627 * is physical disk 1 partition 1 and the Linux root disk is 628 * physical disk 1 partition 2. 629 */ 630 ROOT_DEV = Root_SDA2; /* default to second partition on first drive */ 631 632 if (is_uv_system()) 633 uv_setup(cmdline_p); 634 #ifdef CONFIG_SMP 635 else 636 init_smp_config(); 637 #endif 638 639 screen_info_setup(); 640 paging_init(); 641 642 clear_sched_clock_stable(); 643 } 644 645 /* 646 * Display cpu info for all CPUs. 647 */ 648 static int 649 show_cpuinfo (struct seq_file *m, void *v) 650 { 651 #ifdef CONFIG_SMP 652 # define lpj c->loops_per_jiffy 653 # define cpunum c->cpu 654 #else 655 # define lpj loops_per_jiffy 656 # define cpunum 0 657 #endif 658 static struct { 659 unsigned long mask; 660 const char *feature_name; 661 } feature_bits[] = { 662 { 1UL << 0, "branchlong" }, 663 { 1UL << 1, "spontaneous deferral"}, 664 { 1UL << 2, "16-byte atomic ops" } 665 }; 666 char features[128], *cp, *sep; 667 struct cpuinfo_ia64 *c = v; 668 unsigned long mask; 669 unsigned long proc_freq; 670 int i, size; 671 672 mask = c->features; 673 674 /* build the feature string: */ 675 memcpy(features, "standard", 9); 676 cp = features; 677 size = sizeof(features); 678 sep = ""; 679 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 680 if (mask & feature_bits[i].mask) { 681 cp += snprintf(cp, size, "%s%s", sep, 682 feature_bits[i].feature_name), 683 sep = ", "; 684 mask &= ~feature_bits[i].mask; 685 size = sizeof(features) - (cp - features); 686 } 687 } 688 if (mask && size > 1) { 689 /* print unknown features as a hex value */ 690 snprintf(cp, size, "%s0x%lx", sep, mask); 691 } 692 693 proc_freq = cpufreq_quick_get(cpunum); 694 if (!proc_freq) 695 proc_freq = c->proc_freq / 1000; 696 697 seq_printf(m, 698 "processor : %d\n" 699 "vendor : %s\n" 700 "arch : IA-64\n" 701 "family : %u\n" 702 "model : %u\n" 703 "model name : %s\n" 704 "revision : %u\n" 705 "archrev : %u\n" 706 "features : %s\n" 707 "cpu number : %lu\n" 708 "cpu regs : %u\n" 709 "cpu MHz : %lu.%03lu\n" 710 "itc MHz : %lu.%06lu\n" 711 "BogoMIPS : %lu.%02lu\n", 712 cpunum, c->vendor, c->family, c->model, 713 c->model_name, c->revision, c->archrev, 714 features, c->ppn, c->number, 715 proc_freq / 1000, proc_freq % 1000, 716 c->itc_freq / 1000000, c->itc_freq % 1000000, 717 lpj*HZ/500000, (lpj*HZ/5000) % 100); 718 #ifdef CONFIG_SMP 719 seq_printf(m, "siblings : %u\n", 720 cpumask_weight(&cpu_core_map[cpunum])); 721 if (c->socket_id != -1) 722 seq_printf(m, "physical id: %u\n", c->socket_id); 723 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 724 seq_printf(m, 725 "core id : %u\n" 726 "thread id : %u\n", 727 c->core_id, c->thread_id); 728 #endif 729 seq_printf(m,"\n"); 730 731 return 0; 732 } 733 734 static void * 735 c_start (struct seq_file *m, loff_t *pos) 736 { 737 #ifdef CONFIG_SMP 738 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 739 ++*pos; 740 #endif 741 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 742 } 743 744 static void * 745 c_next (struct seq_file *m, void *v, loff_t *pos) 746 { 747 ++*pos; 748 return c_start(m, pos); 749 } 750 751 static void 752 c_stop (struct seq_file *m, void *v) 753 { 754 } 755 756 const struct seq_operations cpuinfo_op = { 757 .start = c_start, 758 .next = c_next, 759 .stop = c_stop, 760 .show = show_cpuinfo 761 }; 762 763 #define MAX_BRANDS 8 764 static char brandname[MAX_BRANDS][128]; 765 766 static char * 767 get_model_name(__u8 family, __u8 model) 768 { 769 static int overflow; 770 char brand[128]; 771 int i; 772 773 memcpy(brand, "Unknown", 8); 774 if (ia64_pal_get_brand_info(brand)) { 775 if (family == 0x7) 776 memcpy(brand, "Merced", 7); 777 else if (family == 0x1f) switch (model) { 778 case 0: memcpy(brand, "McKinley", 9); break; 779 case 1: memcpy(brand, "Madison", 8); break; 780 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 781 } 782 } 783 for (i = 0; i < MAX_BRANDS; i++) 784 if (strcmp(brandname[i], brand) == 0) 785 return brandname[i]; 786 for (i = 0; i < MAX_BRANDS; i++) 787 if (brandname[i][0] == '\0') 788 return strcpy(brandname[i], brand); 789 if (overflow++ == 0) 790 printk(KERN_ERR 791 "%s: Table overflow. Some processor model information will be missing\n", 792 __func__); 793 return "Unknown"; 794 } 795 796 static void 797 identify_cpu (struct cpuinfo_ia64 *c) 798 { 799 union { 800 unsigned long bits[5]; 801 struct { 802 /* id 0 & 1: */ 803 char vendor[16]; 804 805 /* id 2 */ 806 u64 ppn; /* processor serial number */ 807 808 /* id 3: */ 809 unsigned number : 8; 810 unsigned revision : 8; 811 unsigned model : 8; 812 unsigned family : 8; 813 unsigned archrev : 8; 814 unsigned reserved : 24; 815 816 /* id 4: */ 817 u64 features; 818 } field; 819 } cpuid; 820 pal_vm_info_1_u_t vm1; 821 pal_vm_info_2_u_t vm2; 822 pal_status_t status; 823 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 824 int i; 825 for (i = 0; i < 5; ++i) 826 cpuid.bits[i] = ia64_get_cpuid(i); 827 828 memcpy(c->vendor, cpuid.field.vendor, 16); 829 #ifdef CONFIG_SMP 830 c->cpu = smp_processor_id(); 831 832 /* below default values will be overwritten by identify_siblings() 833 * for Multi-Threading/Multi-Core capable CPUs 834 */ 835 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 836 c->socket_id = -1; 837 838 identify_siblings(c); 839 840 if (c->threads_per_core > smp_num_siblings) 841 smp_num_siblings = c->threads_per_core; 842 #endif 843 c->ppn = cpuid.field.ppn; 844 c->number = cpuid.field.number; 845 c->revision = cpuid.field.revision; 846 c->model = cpuid.field.model; 847 c->family = cpuid.field.family; 848 c->archrev = cpuid.field.archrev; 849 c->features = cpuid.field.features; 850 c->model_name = get_model_name(c->family, c->model); 851 852 status = ia64_pal_vm_summary(&vm1, &vm2); 853 if (status == PAL_STATUS_SUCCESS) { 854 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 855 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 856 } 857 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 858 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 859 } 860 861 /* 862 * Do the following calculations: 863 * 864 * 1. the max. cache line size. 865 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 866 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 867 */ 868 static void 869 get_cache_info(void) 870 { 871 unsigned long line_size, max = 1; 872 unsigned long l, levels, unique_caches; 873 pal_cache_config_info_t cci; 874 long status; 875 876 status = ia64_pal_cache_summary(&levels, &unique_caches); 877 if (status != 0) { 878 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 879 __func__, status); 880 max = SMP_CACHE_BYTES; 881 /* Safest setup for "flush_icache_range()" */ 882 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 883 /* Safest setup for "clflush_cache_range()" */ 884 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 885 goto out; 886 } 887 888 for (l = 0; l < levels; ++l) { 889 /* cache_type (data_or_unified)=2 */ 890 status = ia64_pal_cache_config_info(l, 2, &cci); 891 if (status != 0) { 892 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 893 "(l=%lu, 2) failed (status=%ld)\n", 894 __func__, l, status); 895 max = SMP_CACHE_BYTES; 896 /* The safest setup for "flush_icache_range()" */ 897 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 898 /* The safest setup for "clflush_cache_range()" */ 899 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 900 cci.pcci_unified = 1; 901 } else { 902 if (cci.pcci_stride < ia64_cache_stride_shift) 903 ia64_cache_stride_shift = cci.pcci_stride; 904 905 line_size = 1 << cci.pcci_line_size; 906 if (line_size > max) 907 max = line_size; 908 } 909 910 if (!cci.pcci_unified) { 911 /* cache_type (instruction)=1*/ 912 status = ia64_pal_cache_config_info(l, 1, &cci); 913 if (status != 0) { 914 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 915 "(l=%lu, 1) failed (status=%ld)\n", 916 __func__, l, status); 917 /* The safest setup for flush_icache_range() */ 918 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 919 } 920 } 921 if (cci.pcci_stride < ia64_i_cache_stride_shift) 922 ia64_i_cache_stride_shift = cci.pcci_stride; 923 } 924 out: 925 if (max > ia64_max_cacheline_size) 926 ia64_max_cacheline_size = max; 927 } 928 929 /* 930 * cpu_init() initializes state that is per-CPU. This function acts 931 * as a 'CPU state barrier', nothing should get across. 932 */ 933 void 934 cpu_init (void) 935 { 936 extern void ia64_mmu_init(void *); 937 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 938 unsigned long num_phys_stacked; 939 pal_vm_info_2_u_t vmi; 940 unsigned int max_ctx; 941 struct cpuinfo_ia64 *cpu_info; 942 void *cpu_data; 943 944 cpu_data = per_cpu_init(); 945 #ifdef CONFIG_SMP 946 /* 947 * insert boot cpu into sibling and core mapes 948 * (must be done after per_cpu area is setup) 949 */ 950 if (smp_processor_id() == 0) { 951 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0)); 952 cpumask_set_cpu(0, &cpu_core_map[0]); 953 } else { 954 /* 955 * Set ar.k3 so that assembly code in MCA handler can compute 956 * physical addresses of per cpu variables with a simple: 957 * phys = ar.k3 + &per_cpu_var 958 * and the alt-dtlb-miss handler can set per-cpu mapping into 959 * the TLB when needed. head.S already did this for cpu0. 960 */ 961 ia64_set_kr(IA64_KR_PER_CPU_DATA, 962 ia64_tpa(cpu_data) - (long) __per_cpu_start); 963 } 964 #endif 965 966 get_cache_info(); 967 968 /* 969 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 970 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 971 * depends on the data returned by identify_cpu(). We break the dependency by 972 * accessing cpu_data() through the canonical per-CPU address. 973 */ 974 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 975 identify_cpu(cpu_info); 976 977 #ifdef CONFIG_MCKINLEY 978 { 979 # define FEATURE_SET 16 980 struct ia64_pal_retval iprv; 981 982 if (cpu_info->family == 0x1f) { 983 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 984 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 985 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 986 (iprv.v1 | 0x80), FEATURE_SET, 0); 987 } 988 } 989 #endif 990 991 /* Clear the stack memory reserved for pt_regs: */ 992 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 993 994 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 995 996 /* 997 * Initialize the page-table base register to a global 998 * directory with all zeroes. This ensure that we can handle 999 * TLB-misses to user address-space even before we created the 1000 * first user address-space. This may happen, e.g., due to 1001 * aggressive use of lfetch.fault. 1002 */ 1003 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 1004 1005 /* 1006 * Initialize default control register to defer speculative faults except 1007 * for those arising from TLB misses, which are not deferred. The 1008 * kernel MUST NOT depend on a particular setting of these bits (in other words, 1009 * the kernel must have recovery code for all speculative accesses). Turn on 1010 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 1011 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 1012 * be fine). 1013 */ 1014 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 1015 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 1016 mmgrab(&init_mm); 1017 current->active_mm = &init_mm; 1018 BUG_ON(current->mm); 1019 1020 ia64_mmu_init(ia64_imva(cpu_data)); 1021 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1022 1023 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1024 ia64_set_itc(0); 1025 1026 /* disable all local interrupt sources: */ 1027 ia64_set_itv(1 << 16); 1028 ia64_set_lrr0(1 << 16); 1029 ia64_set_lrr1(1 << 16); 1030 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1031 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1032 1033 /* clear TPR & XTP to enable all interrupt classes: */ 1034 ia64_setreg(_IA64_REG_CR_TPR, 0); 1035 1036 /* Clear any pending interrupts left by SAL/EFI */ 1037 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1038 ia64_eoi(); 1039 1040 #ifdef CONFIG_SMP 1041 normal_xtp(); 1042 #endif 1043 1044 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1045 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1046 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1047 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1048 } else { 1049 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1050 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1051 } 1052 while (max_ctx < ia64_ctx.max_ctx) { 1053 unsigned int old = ia64_ctx.max_ctx; 1054 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1055 break; 1056 } 1057 1058 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1059 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1060 "stacked regs\n"); 1061 num_phys_stacked = 96; 1062 } 1063 /* size of physical stacked register partition plus 8 bytes: */ 1064 if (num_phys_stacked > max_num_phys_stacked) { 1065 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1066 max_num_phys_stacked = num_phys_stacked; 1067 } 1068 } 1069 1070 void __init 1071 check_bugs (void) 1072 { 1073 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1074 (unsigned long) __end___mckinley_e9_bundles); 1075 } 1076 1077 static int __init run_dmi_scan(void) 1078 { 1079 dmi_setup(); 1080 return 0; 1081 } 1082 core_initcall(run_dmi_scan); 1083