1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Architecture-specific setup. 4 * 5 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * Stephane Eranian <eranian@hpl.hp.com> 8 * Copyright (C) 2000, 2004 Intel Corp 9 * Rohit Seth <rohit.seth@intel.com> 10 * Suresh Siddha <suresh.b.siddha@intel.com> 11 * Gordon Jin <gordon.jin@intel.com> 12 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * 15 * 12/26/04 S.Siddha, G.Jin, R.Seth 16 * Add multi-threading and multi-core detection 17 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 18 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 19 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 20 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 21 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 22 * 01/07/99 S.Eranian added the support for command line argument 23 * 06/24/99 W.Drummond added boot_cpu_data. 24 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 25 */ 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/bootmem.h> 31 #include <linux/console.h> 32 #include <linux/delay.h> 33 #include <linux/cpu.h> 34 #include <linux/kernel.h> 35 #include <linux/reboot.h> 36 #include <linux/sched/mm.h> 37 #include <linux/sched/clock.h> 38 #include <linux/sched/task_stack.h> 39 #include <linux/seq_file.h> 40 #include <linux/string.h> 41 #include <linux/threads.h> 42 #include <linux/screen_info.h> 43 #include <linux/dmi.h> 44 #include <linux/serial.h> 45 #include <linux/serial_core.h> 46 #include <linux/efi.h> 47 #include <linux/initrd.h> 48 #include <linux/pm.h> 49 #include <linux/cpufreq.h> 50 #include <linux/kexec.h> 51 #include <linux/crash_dump.h> 52 53 #include <asm/machvec.h> 54 #include <asm/mca.h> 55 #include <asm/meminit.h> 56 #include <asm/page.h> 57 #include <asm/patch.h> 58 #include <asm/pgtable.h> 59 #include <asm/processor.h> 60 #include <asm/sal.h> 61 #include <asm/sections.h> 62 #include <asm/setup.h> 63 #include <asm/smp.h> 64 #include <asm/tlbflush.h> 65 #include <asm/unistd.h> 66 #include <asm/hpsim.h> 67 68 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 69 # error "struct cpuinfo_ia64 too big!" 70 #endif 71 72 #ifdef CONFIG_SMP 73 unsigned long __per_cpu_offset[NR_CPUS]; 74 EXPORT_SYMBOL(__per_cpu_offset); 75 #endif 76 77 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 78 EXPORT_SYMBOL(ia64_cpu_info); 79 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 80 #ifdef CONFIG_SMP 81 EXPORT_SYMBOL(local_per_cpu_offset); 82 #endif 83 unsigned long ia64_cycles_per_usec; 84 struct ia64_boot_param *ia64_boot_param; 85 struct screen_info screen_info; 86 unsigned long vga_console_iobase; 87 unsigned long vga_console_membase; 88 89 static struct resource data_resource = { 90 .name = "Kernel data", 91 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 92 }; 93 94 static struct resource code_resource = { 95 .name = "Kernel code", 96 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 97 }; 98 99 static struct resource bss_resource = { 100 .name = "Kernel bss", 101 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 102 }; 103 104 unsigned long ia64_max_cacheline_size; 105 106 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 107 EXPORT_SYMBOL(ia64_iobase); 108 struct io_space io_space[MAX_IO_SPACES]; 109 EXPORT_SYMBOL(io_space); 110 unsigned int num_io_spaces; 111 112 /* 113 * "flush_icache_range()" needs to know what processor dependent stride size to use 114 * when it makes i-cache(s) coherent with d-caches. 115 */ 116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117 unsigned long ia64_i_cache_stride_shift = ~0; 118 /* 119 * "clflush_cache_range()" needs to know what processor dependent stride size to 120 * use when it flushes cache lines including both d-cache and i-cache. 121 */ 122 /* Safest way to go: 32 bytes by 32 bytes */ 123 #define CACHE_STRIDE_SHIFT 5 124 unsigned long ia64_cache_stride_shift = ~0; 125 126 /* 127 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 128 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 129 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 130 * address of the second buffer must be aligned to (merge_mask+1) in order to be 131 * mergeable). By default, we assume there is no I/O MMU which can merge physically 132 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 133 * page-size of 2^64. 134 */ 135 unsigned long ia64_max_iommu_merge_mask = ~0UL; 136 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 137 138 /* 139 * We use a special marker for the end of memory and it uses the extra (+1) slot 140 */ 141 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 142 int num_rsvd_regions __initdata; 143 144 145 /* 146 * Filter incoming memory segments based on the primitive map created from the boot 147 * parameters. Segments contained in the map are removed from the memory ranges. A 148 * caller-specified function is called with the memory ranges that remain after filtering. 149 * This routine does not assume the incoming segments are sorted. 150 */ 151 int __init 152 filter_rsvd_memory (u64 start, u64 end, void *arg) 153 { 154 u64 range_start, range_end, prev_start; 155 void (*func)(unsigned long, unsigned long, int); 156 int i; 157 158 #if IGNORE_PFN0 159 if (start == PAGE_OFFSET) { 160 printk(KERN_WARNING "warning: skipping physical page 0\n"); 161 start += PAGE_SIZE; 162 if (start >= end) return 0; 163 } 164 #endif 165 /* 166 * lowest possible address(walker uses virtual) 167 */ 168 prev_start = PAGE_OFFSET; 169 func = arg; 170 171 for (i = 0; i < num_rsvd_regions; ++i) { 172 range_start = max(start, prev_start); 173 range_end = min(end, rsvd_region[i].start); 174 175 if (range_start < range_end) 176 call_pernode_memory(__pa(range_start), range_end - range_start, func); 177 178 /* nothing more available in this segment */ 179 if (range_end == end) return 0; 180 181 prev_start = rsvd_region[i].end; 182 } 183 /* end of memory marker allows full processing inside loop body */ 184 return 0; 185 } 186 187 /* 188 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 189 * are not filtered out. 190 */ 191 int __init 192 filter_memory(u64 start, u64 end, void *arg) 193 { 194 void (*func)(unsigned long, unsigned long, int); 195 196 #if IGNORE_PFN0 197 if (start == PAGE_OFFSET) { 198 printk(KERN_WARNING "warning: skipping physical page 0\n"); 199 start += PAGE_SIZE; 200 if (start >= end) 201 return 0; 202 } 203 #endif 204 func = arg; 205 if (start < end) 206 call_pernode_memory(__pa(start), end - start, func); 207 return 0; 208 } 209 210 static void __init 211 sort_regions (struct rsvd_region *rsvd_region, int max) 212 { 213 int j; 214 215 /* simple bubble sorting */ 216 while (max--) { 217 for (j = 0; j < max; ++j) { 218 if (rsvd_region[j].start > rsvd_region[j+1].start) { 219 struct rsvd_region tmp; 220 tmp = rsvd_region[j]; 221 rsvd_region[j] = rsvd_region[j + 1]; 222 rsvd_region[j + 1] = tmp; 223 } 224 } 225 } 226 } 227 228 /* merge overlaps */ 229 static int __init 230 merge_regions (struct rsvd_region *rsvd_region, int max) 231 { 232 int i; 233 for (i = 1; i < max; ++i) { 234 if (rsvd_region[i].start >= rsvd_region[i-1].end) 235 continue; 236 if (rsvd_region[i].end > rsvd_region[i-1].end) 237 rsvd_region[i-1].end = rsvd_region[i].end; 238 --max; 239 memmove(&rsvd_region[i], &rsvd_region[i+1], 240 (max - i) * sizeof(struct rsvd_region)); 241 } 242 return max; 243 } 244 245 /* 246 * Request address space for all standard resources 247 */ 248 static int __init register_memory(void) 249 { 250 code_resource.start = ia64_tpa(_text); 251 code_resource.end = ia64_tpa(_etext) - 1; 252 data_resource.start = ia64_tpa(_etext); 253 data_resource.end = ia64_tpa(_edata) - 1; 254 bss_resource.start = ia64_tpa(__bss_start); 255 bss_resource.end = ia64_tpa(_end) - 1; 256 efi_initialize_iomem_resources(&code_resource, &data_resource, 257 &bss_resource); 258 259 return 0; 260 } 261 262 __initcall(register_memory); 263 264 265 #ifdef CONFIG_KEXEC 266 267 /* 268 * This function checks if the reserved crashkernel is allowed on the specific 269 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 270 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 271 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 272 * in kdump case. See the comment in sba_init() in sba_iommu.c. 273 * 274 * So, the only machvec that really supports loading the kdump kernel 275 * over 4 GB is "sn2". 276 */ 277 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 278 { 279 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 280 return 1; 281 else 282 return pbase < (1UL << 32); 283 } 284 285 static void __init setup_crashkernel(unsigned long total, int *n) 286 { 287 unsigned long long base = 0, size = 0; 288 int ret; 289 290 ret = parse_crashkernel(boot_command_line, total, 291 &size, &base); 292 if (ret == 0 && size > 0) { 293 if (!base) { 294 sort_regions(rsvd_region, *n); 295 *n = merge_regions(rsvd_region, *n); 296 base = kdump_find_rsvd_region(size, 297 rsvd_region, *n); 298 } 299 300 if (!check_crashkernel_memory(base, size)) { 301 pr_warning("crashkernel: There would be kdump memory " 302 "at %ld GB but this is unusable because it " 303 "must\nbe below 4 GB. Change the memory " 304 "configuration of the machine.\n", 305 (unsigned long)(base >> 30)); 306 return; 307 } 308 309 if (base != ~0UL) { 310 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 311 "for crashkernel (System RAM: %ldMB)\n", 312 (unsigned long)(size >> 20), 313 (unsigned long)(base >> 20), 314 (unsigned long)(total >> 20)); 315 rsvd_region[*n].start = 316 (unsigned long)__va(base); 317 rsvd_region[*n].end = 318 (unsigned long)__va(base + size); 319 (*n)++; 320 crashk_res.start = base; 321 crashk_res.end = base + size - 1; 322 } 323 } 324 efi_memmap_res.start = ia64_boot_param->efi_memmap; 325 efi_memmap_res.end = efi_memmap_res.start + 326 ia64_boot_param->efi_memmap_size; 327 boot_param_res.start = __pa(ia64_boot_param); 328 boot_param_res.end = boot_param_res.start + 329 sizeof(*ia64_boot_param); 330 } 331 #else 332 static inline void __init setup_crashkernel(unsigned long total, int *n) 333 {} 334 #endif 335 336 /** 337 * reserve_memory - setup reserved memory areas 338 * 339 * Setup the reserved memory areas set aside for the boot parameters, 340 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 341 * see arch/ia64/include/asm/meminit.h if you need to define more. 342 */ 343 void __init 344 reserve_memory (void) 345 { 346 int n = 0; 347 unsigned long total_memory; 348 349 /* 350 * none of the entries in this table overlap 351 */ 352 rsvd_region[n].start = (unsigned long) ia64_boot_param; 353 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 354 n++; 355 356 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 357 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 358 n++; 359 360 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 361 rsvd_region[n].end = (rsvd_region[n].start 362 + strlen(__va(ia64_boot_param->command_line)) + 1); 363 n++; 364 365 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 366 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 367 n++; 368 369 #ifdef CONFIG_BLK_DEV_INITRD 370 if (ia64_boot_param->initrd_start) { 371 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 372 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 373 n++; 374 } 375 #endif 376 377 #ifdef CONFIG_CRASH_DUMP 378 if (reserve_elfcorehdr(&rsvd_region[n].start, 379 &rsvd_region[n].end) == 0) 380 n++; 381 #endif 382 383 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 384 n++; 385 386 setup_crashkernel(total_memory, &n); 387 388 /* end of memory marker */ 389 rsvd_region[n].start = ~0UL; 390 rsvd_region[n].end = ~0UL; 391 n++; 392 393 num_rsvd_regions = n; 394 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 395 396 sort_regions(rsvd_region, num_rsvd_regions); 397 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions); 398 } 399 400 401 /** 402 * find_initrd - get initrd parameters from the boot parameter structure 403 * 404 * Grab the initrd start and end from the boot parameter struct given us by 405 * the boot loader. 406 */ 407 void __init 408 find_initrd (void) 409 { 410 #ifdef CONFIG_BLK_DEV_INITRD 411 if (ia64_boot_param->initrd_start) { 412 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 413 initrd_end = initrd_start+ia64_boot_param->initrd_size; 414 415 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 416 initrd_start, ia64_boot_param->initrd_size); 417 } 418 #endif 419 } 420 421 static void __init 422 io_port_init (void) 423 { 424 unsigned long phys_iobase; 425 426 /* 427 * Set `iobase' based on the EFI memory map or, failing that, the 428 * value firmware left in ar.k0. 429 * 430 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 431 * the port's virtual address, so ia32_load_state() loads it with a 432 * user virtual address. But in ia64 mode, glibc uses the 433 * *physical* address in ar.k0 to mmap the appropriate area from 434 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 435 * cases, user-mode can only use the legacy 0-64K I/O port space. 436 * 437 * ar.k0 is not involved in kernel I/O port accesses, which can use 438 * any of the I/O port spaces and are done via MMIO using the 439 * virtual mmio_base from the appropriate io_space[]. 440 */ 441 phys_iobase = efi_get_iobase(); 442 if (!phys_iobase) { 443 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 444 printk(KERN_INFO "No I/O port range found in EFI memory map, " 445 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 446 } 447 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 448 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 449 450 /* setup legacy IO port space */ 451 io_space[0].mmio_base = ia64_iobase; 452 io_space[0].sparse = 1; 453 num_io_spaces = 1; 454 } 455 456 /** 457 * early_console_setup - setup debugging console 458 * 459 * Consoles started here require little enough setup that we can start using 460 * them very early in the boot process, either right after the machine 461 * vector initialization, or even before if the drivers can detect their hw. 462 * 463 * Returns non-zero if a console couldn't be setup. 464 */ 465 static inline int __init 466 early_console_setup (char *cmdline) 467 { 468 int earlycons = 0; 469 470 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 471 { 472 extern int sn_serial_console_early_setup(void); 473 if (!sn_serial_console_early_setup()) 474 earlycons++; 475 } 476 #endif 477 #ifdef CONFIG_EFI_PCDP 478 if (!efi_setup_pcdp_console(cmdline)) 479 earlycons++; 480 #endif 481 if (!simcons_register()) 482 earlycons++; 483 484 return (earlycons) ? 0 : -1; 485 } 486 487 static inline void 488 mark_bsp_online (void) 489 { 490 #ifdef CONFIG_SMP 491 /* If we register an early console, allow CPU 0 to printk */ 492 set_cpu_online(smp_processor_id(), true); 493 #endif 494 } 495 496 static __initdata int nomca; 497 static __init int setup_nomca(char *s) 498 { 499 nomca = 1; 500 return 0; 501 } 502 early_param("nomca", setup_nomca); 503 504 #ifdef CONFIG_CRASH_DUMP 505 int __init reserve_elfcorehdr(u64 *start, u64 *end) 506 { 507 u64 length; 508 509 /* We get the address using the kernel command line, 510 * but the size is extracted from the EFI tables. 511 * Both address and size are required for reservation 512 * to work properly. 513 */ 514 515 if (!is_vmcore_usable()) 516 return -EINVAL; 517 518 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 519 vmcore_unusable(); 520 return -EINVAL; 521 } 522 523 *start = (unsigned long)__va(elfcorehdr_addr); 524 *end = *start + length; 525 return 0; 526 } 527 528 #endif /* CONFIG_PROC_VMCORE */ 529 530 void __init 531 setup_arch (char **cmdline_p) 532 { 533 unw_init(); 534 535 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 536 537 *cmdline_p = __va(ia64_boot_param->command_line); 538 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 539 540 efi_init(); 541 io_port_init(); 542 543 #ifdef CONFIG_IA64_GENERIC 544 /* machvec needs to be parsed from the command line 545 * before parse_early_param() is called to ensure 546 * that ia64_mv is initialised before any command line 547 * settings may cause console setup to occur 548 */ 549 machvec_init_from_cmdline(*cmdline_p); 550 #endif 551 552 parse_early_param(); 553 554 if (early_console_setup(*cmdline_p) == 0) 555 mark_bsp_online(); 556 557 #ifdef CONFIG_ACPI 558 /* Initialize the ACPI boot-time table parser */ 559 acpi_table_init(); 560 early_acpi_boot_init(); 561 # ifdef CONFIG_ACPI_NUMA 562 acpi_numa_init(); 563 acpi_numa_fixup(); 564 # ifdef CONFIG_ACPI_HOTPLUG_CPU 565 prefill_possible_map(); 566 # endif 567 per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ? 568 32 : cpumask_weight(&early_cpu_possible_map)), 569 additional_cpus > 0 ? additional_cpus : 0); 570 # endif 571 #endif /* CONFIG_APCI_BOOT */ 572 573 #ifdef CONFIG_SMP 574 smp_build_cpu_map(); 575 #endif 576 find_memory(); 577 578 /* process SAL system table: */ 579 ia64_sal_init(__va(efi.sal_systab)); 580 581 #ifdef CONFIG_ITANIUM 582 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 583 #else 584 { 585 unsigned long num_phys_stacked; 586 587 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 588 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 589 } 590 #endif 591 592 #ifdef CONFIG_SMP 593 cpu_physical_id(0) = hard_smp_processor_id(); 594 #endif 595 596 cpu_init(); /* initialize the bootstrap CPU */ 597 mmu_context_init(); /* initialize context_id bitmap */ 598 599 #ifdef CONFIG_VT 600 if (!conswitchp) { 601 # if defined(CONFIG_DUMMY_CONSOLE) 602 conswitchp = &dummy_con; 603 # endif 604 # if defined(CONFIG_VGA_CONSOLE) 605 /* 606 * Non-legacy systems may route legacy VGA MMIO range to system 607 * memory. vga_con probes the MMIO hole, so memory looks like 608 * a VGA device to it. The EFI memory map can tell us if it's 609 * memory so we can avoid this problem. 610 */ 611 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 612 conswitchp = &vga_con; 613 # endif 614 } 615 #endif 616 617 /* enable IA-64 Machine Check Abort Handling unless disabled */ 618 if (!nomca) 619 ia64_mca_init(); 620 621 platform_setup(cmdline_p); 622 #ifndef CONFIG_IA64_HP_SIM 623 check_sal_cache_flush(); 624 #endif 625 paging_init(); 626 627 clear_sched_clock_stable(); 628 } 629 630 /* 631 * Display cpu info for all CPUs. 632 */ 633 static int 634 show_cpuinfo (struct seq_file *m, void *v) 635 { 636 #ifdef CONFIG_SMP 637 # define lpj c->loops_per_jiffy 638 # define cpunum c->cpu 639 #else 640 # define lpj loops_per_jiffy 641 # define cpunum 0 642 #endif 643 static struct { 644 unsigned long mask; 645 const char *feature_name; 646 } feature_bits[] = { 647 { 1UL << 0, "branchlong" }, 648 { 1UL << 1, "spontaneous deferral"}, 649 { 1UL << 2, "16-byte atomic ops" } 650 }; 651 char features[128], *cp, *sep; 652 struct cpuinfo_ia64 *c = v; 653 unsigned long mask; 654 unsigned long proc_freq; 655 int i, size; 656 657 mask = c->features; 658 659 /* build the feature string: */ 660 memcpy(features, "standard", 9); 661 cp = features; 662 size = sizeof(features); 663 sep = ""; 664 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 665 if (mask & feature_bits[i].mask) { 666 cp += snprintf(cp, size, "%s%s", sep, 667 feature_bits[i].feature_name), 668 sep = ", "; 669 mask &= ~feature_bits[i].mask; 670 size = sizeof(features) - (cp - features); 671 } 672 } 673 if (mask && size > 1) { 674 /* print unknown features as a hex value */ 675 snprintf(cp, size, "%s0x%lx", sep, mask); 676 } 677 678 proc_freq = cpufreq_quick_get(cpunum); 679 if (!proc_freq) 680 proc_freq = c->proc_freq / 1000; 681 682 seq_printf(m, 683 "processor : %d\n" 684 "vendor : %s\n" 685 "arch : IA-64\n" 686 "family : %u\n" 687 "model : %u\n" 688 "model name : %s\n" 689 "revision : %u\n" 690 "archrev : %u\n" 691 "features : %s\n" 692 "cpu number : %lu\n" 693 "cpu regs : %u\n" 694 "cpu MHz : %lu.%03lu\n" 695 "itc MHz : %lu.%06lu\n" 696 "BogoMIPS : %lu.%02lu\n", 697 cpunum, c->vendor, c->family, c->model, 698 c->model_name, c->revision, c->archrev, 699 features, c->ppn, c->number, 700 proc_freq / 1000, proc_freq % 1000, 701 c->itc_freq / 1000000, c->itc_freq % 1000000, 702 lpj*HZ/500000, (lpj*HZ/5000) % 100); 703 #ifdef CONFIG_SMP 704 seq_printf(m, "siblings : %u\n", 705 cpumask_weight(&cpu_core_map[cpunum])); 706 if (c->socket_id != -1) 707 seq_printf(m, "physical id: %u\n", c->socket_id); 708 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 709 seq_printf(m, 710 "core id : %u\n" 711 "thread id : %u\n", 712 c->core_id, c->thread_id); 713 #endif 714 seq_printf(m,"\n"); 715 716 return 0; 717 } 718 719 static void * 720 c_start (struct seq_file *m, loff_t *pos) 721 { 722 #ifdef CONFIG_SMP 723 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 724 ++*pos; 725 #endif 726 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 727 } 728 729 static void * 730 c_next (struct seq_file *m, void *v, loff_t *pos) 731 { 732 ++*pos; 733 return c_start(m, pos); 734 } 735 736 static void 737 c_stop (struct seq_file *m, void *v) 738 { 739 } 740 741 const struct seq_operations cpuinfo_op = { 742 .start = c_start, 743 .next = c_next, 744 .stop = c_stop, 745 .show = show_cpuinfo 746 }; 747 748 #define MAX_BRANDS 8 749 static char brandname[MAX_BRANDS][128]; 750 751 static char * 752 get_model_name(__u8 family, __u8 model) 753 { 754 static int overflow; 755 char brand[128]; 756 int i; 757 758 memcpy(brand, "Unknown", 8); 759 if (ia64_pal_get_brand_info(brand)) { 760 if (family == 0x7) 761 memcpy(brand, "Merced", 7); 762 else if (family == 0x1f) switch (model) { 763 case 0: memcpy(brand, "McKinley", 9); break; 764 case 1: memcpy(brand, "Madison", 8); break; 765 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 766 } 767 } 768 for (i = 0; i < MAX_BRANDS; i++) 769 if (strcmp(brandname[i], brand) == 0) 770 return brandname[i]; 771 for (i = 0; i < MAX_BRANDS; i++) 772 if (brandname[i][0] == '\0') 773 return strcpy(brandname[i], brand); 774 if (overflow++ == 0) 775 printk(KERN_ERR 776 "%s: Table overflow. Some processor model information will be missing\n", 777 __func__); 778 return "Unknown"; 779 } 780 781 static void 782 identify_cpu (struct cpuinfo_ia64 *c) 783 { 784 union { 785 unsigned long bits[5]; 786 struct { 787 /* id 0 & 1: */ 788 char vendor[16]; 789 790 /* id 2 */ 791 u64 ppn; /* processor serial number */ 792 793 /* id 3: */ 794 unsigned number : 8; 795 unsigned revision : 8; 796 unsigned model : 8; 797 unsigned family : 8; 798 unsigned archrev : 8; 799 unsigned reserved : 24; 800 801 /* id 4: */ 802 u64 features; 803 } field; 804 } cpuid; 805 pal_vm_info_1_u_t vm1; 806 pal_vm_info_2_u_t vm2; 807 pal_status_t status; 808 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 809 int i; 810 for (i = 0; i < 5; ++i) 811 cpuid.bits[i] = ia64_get_cpuid(i); 812 813 memcpy(c->vendor, cpuid.field.vendor, 16); 814 #ifdef CONFIG_SMP 815 c->cpu = smp_processor_id(); 816 817 /* below default values will be overwritten by identify_siblings() 818 * for Multi-Threading/Multi-Core capable CPUs 819 */ 820 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 821 c->socket_id = -1; 822 823 identify_siblings(c); 824 825 if (c->threads_per_core > smp_num_siblings) 826 smp_num_siblings = c->threads_per_core; 827 #endif 828 c->ppn = cpuid.field.ppn; 829 c->number = cpuid.field.number; 830 c->revision = cpuid.field.revision; 831 c->model = cpuid.field.model; 832 c->family = cpuid.field.family; 833 c->archrev = cpuid.field.archrev; 834 c->features = cpuid.field.features; 835 c->model_name = get_model_name(c->family, c->model); 836 837 status = ia64_pal_vm_summary(&vm1, &vm2); 838 if (status == PAL_STATUS_SUCCESS) { 839 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 840 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 841 } 842 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 843 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 844 } 845 846 /* 847 * Do the following calculations: 848 * 849 * 1. the max. cache line size. 850 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 851 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 852 */ 853 static void 854 get_cache_info(void) 855 { 856 unsigned long line_size, max = 1; 857 unsigned long l, levels, unique_caches; 858 pal_cache_config_info_t cci; 859 long status; 860 861 status = ia64_pal_cache_summary(&levels, &unique_caches); 862 if (status != 0) { 863 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 864 __func__, status); 865 max = SMP_CACHE_BYTES; 866 /* Safest setup for "flush_icache_range()" */ 867 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 868 /* Safest setup for "clflush_cache_range()" */ 869 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 870 goto out; 871 } 872 873 for (l = 0; l < levels; ++l) { 874 /* cache_type (data_or_unified)=2 */ 875 status = ia64_pal_cache_config_info(l, 2, &cci); 876 if (status != 0) { 877 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 878 "(l=%lu, 2) failed (status=%ld)\n", 879 __func__, l, status); 880 max = SMP_CACHE_BYTES; 881 /* The safest setup for "flush_icache_range()" */ 882 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 883 /* The safest setup for "clflush_cache_range()" */ 884 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 885 cci.pcci_unified = 1; 886 } else { 887 if (cci.pcci_stride < ia64_cache_stride_shift) 888 ia64_cache_stride_shift = cci.pcci_stride; 889 890 line_size = 1 << cci.pcci_line_size; 891 if (line_size > max) 892 max = line_size; 893 } 894 895 if (!cci.pcci_unified) { 896 /* cache_type (instruction)=1*/ 897 status = ia64_pal_cache_config_info(l, 1, &cci); 898 if (status != 0) { 899 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 900 "(l=%lu, 1) failed (status=%ld)\n", 901 __func__, l, status); 902 /* The safest setup for flush_icache_range() */ 903 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 904 } 905 } 906 if (cci.pcci_stride < ia64_i_cache_stride_shift) 907 ia64_i_cache_stride_shift = cci.pcci_stride; 908 } 909 out: 910 if (max > ia64_max_cacheline_size) 911 ia64_max_cacheline_size = max; 912 } 913 914 /* 915 * cpu_init() initializes state that is per-CPU. This function acts 916 * as a 'CPU state barrier', nothing should get across. 917 */ 918 void 919 cpu_init (void) 920 { 921 extern void ia64_mmu_init(void *); 922 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 923 unsigned long num_phys_stacked; 924 pal_vm_info_2_u_t vmi; 925 unsigned int max_ctx; 926 struct cpuinfo_ia64 *cpu_info; 927 void *cpu_data; 928 929 cpu_data = per_cpu_init(); 930 #ifdef CONFIG_SMP 931 /* 932 * insert boot cpu into sibling and core mapes 933 * (must be done after per_cpu area is setup) 934 */ 935 if (smp_processor_id() == 0) { 936 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0)); 937 cpumask_set_cpu(0, &cpu_core_map[0]); 938 } else { 939 /* 940 * Set ar.k3 so that assembly code in MCA handler can compute 941 * physical addresses of per cpu variables with a simple: 942 * phys = ar.k3 + &per_cpu_var 943 * and the alt-dtlb-miss handler can set per-cpu mapping into 944 * the TLB when needed. head.S already did this for cpu0. 945 */ 946 ia64_set_kr(IA64_KR_PER_CPU_DATA, 947 ia64_tpa(cpu_data) - (long) __per_cpu_start); 948 } 949 #endif 950 951 get_cache_info(); 952 953 /* 954 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 955 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 956 * depends on the data returned by identify_cpu(). We break the dependency by 957 * accessing cpu_data() through the canonical per-CPU address. 958 */ 959 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 960 identify_cpu(cpu_info); 961 962 #ifdef CONFIG_MCKINLEY 963 { 964 # define FEATURE_SET 16 965 struct ia64_pal_retval iprv; 966 967 if (cpu_info->family == 0x1f) { 968 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 969 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 970 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 971 (iprv.v1 | 0x80), FEATURE_SET, 0); 972 } 973 } 974 #endif 975 976 /* Clear the stack memory reserved for pt_regs: */ 977 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 978 979 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 980 981 /* 982 * Initialize the page-table base register to a global 983 * directory with all zeroes. This ensure that we can handle 984 * TLB-misses to user address-space even before we created the 985 * first user address-space. This may happen, e.g., due to 986 * aggressive use of lfetch.fault. 987 */ 988 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 989 990 /* 991 * Initialize default control register to defer speculative faults except 992 * for those arising from TLB misses, which are not deferred. The 993 * kernel MUST NOT depend on a particular setting of these bits (in other words, 994 * the kernel must have recovery code for all speculative accesses). Turn on 995 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 996 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 997 * be fine). 998 */ 999 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 1000 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 1001 mmgrab(&init_mm); 1002 current->active_mm = &init_mm; 1003 BUG_ON(current->mm); 1004 1005 ia64_mmu_init(ia64_imva(cpu_data)); 1006 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1007 1008 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1009 ia64_set_itc(0); 1010 1011 /* disable all local interrupt sources: */ 1012 ia64_set_itv(1 << 16); 1013 ia64_set_lrr0(1 << 16); 1014 ia64_set_lrr1(1 << 16); 1015 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1016 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1017 1018 /* clear TPR & XTP to enable all interrupt classes: */ 1019 ia64_setreg(_IA64_REG_CR_TPR, 0); 1020 1021 /* Clear any pending interrupts left by SAL/EFI */ 1022 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1023 ia64_eoi(); 1024 1025 #ifdef CONFIG_SMP 1026 normal_xtp(); 1027 #endif 1028 1029 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1030 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1031 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1032 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1033 } else { 1034 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1035 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1036 } 1037 while (max_ctx < ia64_ctx.max_ctx) { 1038 unsigned int old = ia64_ctx.max_ctx; 1039 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1040 break; 1041 } 1042 1043 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1044 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1045 "stacked regs\n"); 1046 num_phys_stacked = 96; 1047 } 1048 /* size of physical stacked register partition plus 8 bytes: */ 1049 if (num_phys_stacked > max_num_phys_stacked) { 1050 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1051 max_num_phys_stacked = num_phys_stacked; 1052 } 1053 platform_cpu_init(); 1054 } 1055 1056 void __init 1057 check_bugs (void) 1058 { 1059 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1060 (unsigned long) __end___mckinley_e9_bundles); 1061 } 1062 1063 static int __init run_dmi_scan(void) 1064 { 1065 dmi_scan_machine(); 1066 dmi_memdev_walk(); 1067 dmi_set_dump_stack_arch_desc(); 1068 return 0; 1069 } 1070 core_initcall(run_dmi_scan); 1071