1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/system.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 extern void ia64_setup_printk_clock(void); 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 79 unsigned long ia64_cycles_per_usec; 80 struct ia64_boot_param *ia64_boot_param; 81 struct screen_info screen_info; 82 unsigned long vga_console_iobase; 83 unsigned long vga_console_membase; 84 85 static struct resource data_resource = { 86 .name = "Kernel data", 87 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 88 }; 89 90 static struct resource code_resource = { 91 .name = "Kernel code", 92 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 93 }; 94 extern void efi_initialize_iomem_resources(struct resource *, 95 struct resource *); 96 extern char _text[], _end[], _etext[]; 97 98 unsigned long ia64_max_cacheline_size; 99 100 int dma_get_cache_alignment(void) 101 { 102 return ia64_max_cacheline_size; 103 } 104 EXPORT_SYMBOL(dma_get_cache_alignment); 105 106 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 107 EXPORT_SYMBOL(ia64_iobase); 108 struct io_space io_space[MAX_IO_SPACES]; 109 EXPORT_SYMBOL(io_space); 110 unsigned int num_io_spaces; 111 112 /* 113 * "flush_icache_range()" needs to know what processor dependent stride size to use 114 * when it makes i-cache(s) coherent with d-caches. 115 */ 116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117 unsigned long ia64_i_cache_stride_shift = ~0; 118 119 /* 120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 123 * address of the second buffer must be aligned to (merge_mask+1) in order to be 124 * mergeable). By default, we assume there is no I/O MMU which can merge physically 125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 126 * page-size of 2^64. 127 */ 128 unsigned long ia64_max_iommu_merge_mask = ~0UL; 129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 130 131 /* 132 * We use a special marker for the end of memory and it uses the extra (+1) slot 133 */ 134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 135 int num_rsvd_regions __initdata; 136 137 138 /* 139 * Filter incoming memory segments based on the primitive map created from the boot 140 * parameters. Segments contained in the map are removed from the memory ranges. A 141 * caller-specified function is called with the memory ranges that remain after filtering. 142 * This routine does not assume the incoming segments are sorted. 143 */ 144 int __init 145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 146 { 147 unsigned long range_start, range_end, prev_start; 148 void (*func)(unsigned long, unsigned long, int); 149 int i; 150 151 #if IGNORE_PFN0 152 if (start == PAGE_OFFSET) { 153 printk(KERN_WARNING "warning: skipping physical page 0\n"); 154 start += PAGE_SIZE; 155 if (start >= end) return 0; 156 } 157 #endif 158 /* 159 * lowest possible address(walker uses virtual) 160 */ 161 prev_start = PAGE_OFFSET; 162 func = arg; 163 164 for (i = 0; i < num_rsvd_regions; ++i) { 165 range_start = max(start, prev_start); 166 range_end = min(end, rsvd_region[i].start); 167 168 if (range_start < range_end) 169 call_pernode_memory(__pa(range_start), range_end - range_start, func); 170 171 /* nothing more available in this segment */ 172 if (range_end == end) return 0; 173 174 prev_start = rsvd_region[i].end; 175 } 176 /* end of memory marker allows full processing inside loop body */ 177 return 0; 178 } 179 180 static void __init 181 sort_regions (struct rsvd_region *rsvd_region, int max) 182 { 183 int j; 184 185 /* simple bubble sorting */ 186 while (max--) { 187 for (j = 0; j < max; ++j) { 188 if (rsvd_region[j].start > rsvd_region[j+1].start) { 189 struct rsvd_region tmp; 190 tmp = rsvd_region[j]; 191 rsvd_region[j] = rsvd_region[j + 1]; 192 rsvd_region[j + 1] = tmp; 193 } 194 } 195 } 196 } 197 198 /* 199 * Request address space for all standard resources 200 */ 201 static int __init register_memory(void) 202 { 203 code_resource.start = ia64_tpa(_text); 204 code_resource.end = ia64_tpa(_etext) - 1; 205 data_resource.start = ia64_tpa(_etext); 206 data_resource.end = ia64_tpa(_end) - 1; 207 efi_initialize_iomem_resources(&code_resource, &data_resource); 208 209 return 0; 210 } 211 212 __initcall(register_memory); 213 214 /** 215 * reserve_memory - setup reserved memory areas 216 * 217 * Setup the reserved memory areas set aside for the boot parameters, 218 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 219 * see include/asm-ia64/meminit.h if you need to define more. 220 */ 221 void __init 222 reserve_memory (void) 223 { 224 int n = 0; 225 226 /* 227 * none of the entries in this table overlap 228 */ 229 rsvd_region[n].start = (unsigned long) ia64_boot_param; 230 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 231 n++; 232 233 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 234 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 235 n++; 236 237 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 238 rsvd_region[n].end = (rsvd_region[n].start 239 + strlen(__va(ia64_boot_param->command_line)) + 1); 240 n++; 241 242 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 243 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 244 n++; 245 246 #ifdef CONFIG_BLK_DEV_INITRD 247 if (ia64_boot_param->initrd_start) { 248 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 249 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 250 n++; 251 } 252 #endif 253 254 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 255 n++; 256 257 #ifdef CONFIG_KEXEC 258 /* crashkernel=size@offset specifies the size to reserve for a crash 259 * kernel.(offset is ingored for keep compatibility with other archs) 260 * By reserving this memory we guarantee that linux never set's it 261 * up as a DMA target.Useful for holding code to do something 262 * appropriate after a kernel panic. 263 */ 264 { 265 char *from = strstr(saved_command_line, "crashkernel="); 266 unsigned long base, size; 267 if (from) { 268 size = memparse(from + 12, &from); 269 if (size) { 270 sort_regions(rsvd_region, n); 271 base = kdump_find_rsvd_region(size, 272 rsvd_region, n); 273 if (base != ~0UL) { 274 rsvd_region[n].start = 275 (unsigned long)__va(base); 276 rsvd_region[n].end = 277 (unsigned long)__va(base + size); 278 n++; 279 crashk_res.start = base; 280 crashk_res.end = base + size - 1; 281 } 282 } 283 } 284 efi_memmap_res.start = ia64_boot_param->efi_memmap; 285 efi_memmap_res.end = efi_memmap_res.start + 286 ia64_boot_param->efi_memmap_size; 287 boot_param_res.start = __pa(ia64_boot_param); 288 boot_param_res.end = boot_param_res.start + 289 sizeof(*ia64_boot_param); 290 } 291 #endif 292 /* end of memory marker */ 293 rsvd_region[n].start = ~0UL; 294 rsvd_region[n].end = ~0UL; 295 n++; 296 297 num_rsvd_regions = n; 298 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 299 300 sort_regions(rsvd_region, num_rsvd_regions); 301 } 302 303 304 /** 305 * find_initrd - get initrd parameters from the boot parameter structure 306 * 307 * Grab the initrd start and end from the boot parameter struct given us by 308 * the boot loader. 309 */ 310 void __init 311 find_initrd (void) 312 { 313 #ifdef CONFIG_BLK_DEV_INITRD 314 if (ia64_boot_param->initrd_start) { 315 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 316 initrd_end = initrd_start+ia64_boot_param->initrd_size; 317 318 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 319 initrd_start, ia64_boot_param->initrd_size); 320 } 321 #endif 322 } 323 324 static void __init 325 io_port_init (void) 326 { 327 unsigned long phys_iobase; 328 329 /* 330 * Set `iobase' based on the EFI memory map or, failing that, the 331 * value firmware left in ar.k0. 332 * 333 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 334 * the port's virtual address, so ia32_load_state() loads it with a 335 * user virtual address. But in ia64 mode, glibc uses the 336 * *physical* address in ar.k0 to mmap the appropriate area from 337 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 338 * cases, user-mode can only use the legacy 0-64K I/O port space. 339 * 340 * ar.k0 is not involved in kernel I/O port accesses, which can use 341 * any of the I/O port spaces and are done via MMIO using the 342 * virtual mmio_base from the appropriate io_space[]. 343 */ 344 phys_iobase = efi_get_iobase(); 345 if (!phys_iobase) { 346 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 347 printk(KERN_INFO "No I/O port range found in EFI memory map, " 348 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 349 } 350 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 351 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 352 353 /* setup legacy IO port space */ 354 io_space[0].mmio_base = ia64_iobase; 355 io_space[0].sparse = 1; 356 num_io_spaces = 1; 357 } 358 359 /** 360 * early_console_setup - setup debugging console 361 * 362 * Consoles started here require little enough setup that we can start using 363 * them very early in the boot process, either right after the machine 364 * vector initialization, or even before if the drivers can detect their hw. 365 * 366 * Returns non-zero if a console couldn't be setup. 367 */ 368 static inline int __init 369 early_console_setup (char *cmdline) 370 { 371 int earlycons = 0; 372 373 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 374 { 375 extern int sn_serial_console_early_setup(void); 376 if (!sn_serial_console_early_setup()) 377 earlycons++; 378 } 379 #endif 380 #ifdef CONFIG_EFI_PCDP 381 if (!efi_setup_pcdp_console(cmdline)) 382 earlycons++; 383 #endif 384 #ifdef CONFIG_SERIAL_8250_CONSOLE 385 if (!early_serial_console_init(cmdline)) 386 earlycons++; 387 #endif 388 389 return (earlycons) ? 0 : -1; 390 } 391 392 static inline void 393 mark_bsp_online (void) 394 { 395 #ifdef CONFIG_SMP 396 /* If we register an early console, allow CPU 0 to printk */ 397 cpu_set(smp_processor_id(), cpu_online_map); 398 #endif 399 } 400 401 #ifdef CONFIG_SMP 402 static void __init 403 check_for_logical_procs (void) 404 { 405 pal_logical_to_physical_t info; 406 s64 status; 407 408 status = ia64_pal_logical_to_phys(0, &info); 409 if (status == -1) { 410 printk(KERN_INFO "No logical to physical processor mapping " 411 "available\n"); 412 return; 413 } 414 if (status) { 415 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 416 status); 417 return; 418 } 419 /* 420 * Total number of siblings that BSP has. Though not all of them 421 * may have booted successfully. The correct number of siblings 422 * booted is in info.overview_num_log. 423 */ 424 smp_num_siblings = info.overview_tpc; 425 smp_num_cpucores = info.overview_cpp; 426 } 427 #endif 428 429 static __initdata int nomca; 430 static __init int setup_nomca(char *s) 431 { 432 nomca = 1; 433 return 0; 434 } 435 early_param("nomca", setup_nomca); 436 437 #ifdef CONFIG_PROC_VMCORE 438 /* elfcorehdr= specifies the location of elf core header 439 * stored by the crashed kernel. 440 */ 441 static int __init parse_elfcorehdr(char *arg) 442 { 443 if (!arg) 444 return -EINVAL; 445 446 elfcorehdr_addr = memparse(arg, &arg); 447 return 0; 448 } 449 early_param("elfcorehdr", parse_elfcorehdr); 450 #endif /* CONFIG_PROC_VMCORE */ 451 452 void __init 453 setup_arch (char **cmdline_p) 454 { 455 unw_init(); 456 457 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 458 459 *cmdline_p = __va(ia64_boot_param->command_line); 460 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 461 462 efi_init(); 463 io_port_init(); 464 465 parse_early_param(); 466 467 #ifdef CONFIG_IA64_GENERIC 468 machvec_init(NULL); 469 #endif 470 471 if (early_console_setup(*cmdline_p) == 0) 472 mark_bsp_online(); 473 474 #ifdef CONFIG_ACPI 475 /* Initialize the ACPI boot-time table parser */ 476 acpi_table_init(); 477 # ifdef CONFIG_ACPI_NUMA 478 acpi_numa_init(); 479 # endif 480 #else 481 # ifdef CONFIG_SMP 482 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 483 # endif 484 #endif /* CONFIG_APCI_BOOT */ 485 486 find_memory(); 487 488 /* process SAL system table: */ 489 ia64_sal_init(__va(efi.sal_systab)); 490 491 ia64_setup_printk_clock(); 492 493 #ifdef CONFIG_SMP 494 cpu_physical_id(0) = hard_smp_processor_id(); 495 496 cpu_set(0, cpu_sibling_map[0]); 497 cpu_set(0, cpu_core_map[0]); 498 499 check_for_logical_procs(); 500 if (smp_num_cpucores > 1) 501 printk(KERN_INFO 502 "cpu package is Multi-Core capable: number of cores=%d\n", 503 smp_num_cpucores); 504 if (smp_num_siblings > 1) 505 printk(KERN_INFO 506 "cpu package is Multi-Threading capable: number of siblings=%d\n", 507 smp_num_siblings); 508 #endif 509 510 cpu_init(); /* initialize the bootstrap CPU */ 511 mmu_context_init(); /* initialize context_id bitmap */ 512 513 check_sal_cache_flush(); 514 515 #ifdef CONFIG_ACPI 516 acpi_boot_init(); 517 #endif 518 519 #ifdef CONFIG_VT 520 if (!conswitchp) { 521 # if defined(CONFIG_DUMMY_CONSOLE) 522 conswitchp = &dummy_con; 523 # endif 524 # if defined(CONFIG_VGA_CONSOLE) 525 /* 526 * Non-legacy systems may route legacy VGA MMIO range to system 527 * memory. vga_con probes the MMIO hole, so memory looks like 528 * a VGA device to it. The EFI memory map can tell us if it's 529 * memory so we can avoid this problem. 530 */ 531 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 532 conswitchp = &vga_con; 533 # endif 534 } 535 #endif 536 537 /* enable IA-64 Machine Check Abort Handling unless disabled */ 538 if (!nomca) 539 ia64_mca_init(); 540 541 platform_setup(cmdline_p); 542 paging_init(); 543 } 544 545 /* 546 * Display cpu info for all cpu's. 547 */ 548 static int 549 show_cpuinfo (struct seq_file *m, void *v) 550 { 551 #ifdef CONFIG_SMP 552 # define lpj c->loops_per_jiffy 553 # define cpunum c->cpu 554 #else 555 # define lpj loops_per_jiffy 556 # define cpunum 0 557 #endif 558 static struct { 559 unsigned long mask; 560 const char *feature_name; 561 } feature_bits[] = { 562 { 1UL << 0, "branchlong" }, 563 { 1UL << 1, "spontaneous deferral"}, 564 { 1UL << 2, "16-byte atomic ops" } 565 }; 566 char features[128], *cp, sep; 567 struct cpuinfo_ia64 *c = v; 568 unsigned long mask; 569 unsigned long proc_freq; 570 int i; 571 572 mask = c->features; 573 574 /* build the feature string: */ 575 memcpy(features, " standard", 10); 576 cp = features; 577 sep = 0; 578 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 579 if (mask & feature_bits[i].mask) { 580 if (sep) 581 *cp++ = sep; 582 sep = ','; 583 *cp++ = ' '; 584 strcpy(cp, feature_bits[i].feature_name); 585 cp += strlen(feature_bits[i].feature_name); 586 mask &= ~feature_bits[i].mask; 587 } 588 } 589 if (mask) { 590 /* print unknown features as a hex value: */ 591 if (sep) 592 *cp++ = sep; 593 sprintf(cp, " 0x%lx", mask); 594 } 595 596 proc_freq = cpufreq_quick_get(cpunum); 597 if (!proc_freq) 598 proc_freq = c->proc_freq / 1000; 599 600 seq_printf(m, 601 "processor : %d\n" 602 "vendor : %s\n" 603 "arch : IA-64\n" 604 "family : %u\n" 605 "model : %u\n" 606 "model name : %s\n" 607 "revision : %u\n" 608 "archrev : %u\n" 609 "features :%s\n" /* don't change this---it _is_ right! */ 610 "cpu number : %lu\n" 611 "cpu regs : %u\n" 612 "cpu MHz : %lu.%06lu\n" 613 "itc MHz : %lu.%06lu\n" 614 "BogoMIPS : %lu.%02lu\n", 615 cpunum, c->vendor, c->family, c->model, 616 c->model_name, c->revision, c->archrev, 617 features, c->ppn, c->number, 618 proc_freq / 1000, proc_freq % 1000, 619 c->itc_freq / 1000000, c->itc_freq % 1000000, 620 lpj*HZ/500000, (lpj*HZ/5000) % 100); 621 #ifdef CONFIG_SMP 622 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 623 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 624 seq_printf(m, 625 "physical id: %u\n" 626 "core id : %u\n" 627 "thread id : %u\n", 628 c->socket_id, c->core_id, c->thread_id); 629 #endif 630 seq_printf(m,"\n"); 631 632 return 0; 633 } 634 635 static void * 636 c_start (struct seq_file *m, loff_t *pos) 637 { 638 #ifdef CONFIG_SMP 639 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 640 ++*pos; 641 #endif 642 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 643 } 644 645 static void * 646 c_next (struct seq_file *m, void *v, loff_t *pos) 647 { 648 ++*pos; 649 return c_start(m, pos); 650 } 651 652 static void 653 c_stop (struct seq_file *m, void *v) 654 { 655 } 656 657 struct seq_operations cpuinfo_op = { 658 .start = c_start, 659 .next = c_next, 660 .stop = c_stop, 661 .show = show_cpuinfo 662 }; 663 664 static char brandname[128]; 665 666 static char * __cpuinit 667 get_model_name(__u8 family, __u8 model) 668 { 669 char brand[128]; 670 671 if (ia64_pal_get_brand_info(brand)) { 672 if (family == 0x7) 673 memcpy(brand, "Merced", 7); 674 else if (family == 0x1f) switch (model) { 675 case 0: memcpy(brand, "McKinley", 9); break; 676 case 1: memcpy(brand, "Madison", 8); break; 677 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 678 } else 679 memcpy(brand, "Unknown", 8); 680 } 681 if (brandname[0] == '\0') 682 return strcpy(brandname, brand); 683 else if (strcmp(brandname, brand) == 0) 684 return brandname; 685 else 686 return kstrdup(brand, GFP_KERNEL); 687 } 688 689 static void __cpuinit 690 identify_cpu (struct cpuinfo_ia64 *c) 691 { 692 union { 693 unsigned long bits[5]; 694 struct { 695 /* id 0 & 1: */ 696 char vendor[16]; 697 698 /* id 2 */ 699 u64 ppn; /* processor serial number */ 700 701 /* id 3: */ 702 unsigned number : 8; 703 unsigned revision : 8; 704 unsigned model : 8; 705 unsigned family : 8; 706 unsigned archrev : 8; 707 unsigned reserved : 24; 708 709 /* id 4: */ 710 u64 features; 711 } field; 712 } cpuid; 713 pal_vm_info_1_u_t vm1; 714 pal_vm_info_2_u_t vm2; 715 pal_status_t status; 716 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 717 int i; 718 for (i = 0; i < 5; ++i) 719 cpuid.bits[i] = ia64_get_cpuid(i); 720 721 memcpy(c->vendor, cpuid.field.vendor, 16); 722 #ifdef CONFIG_SMP 723 c->cpu = smp_processor_id(); 724 725 /* below default values will be overwritten by identify_siblings() 726 * for Multi-Threading/Multi-Core capable cpu's 727 */ 728 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 729 c->socket_id = -1; 730 731 identify_siblings(c); 732 #endif 733 c->ppn = cpuid.field.ppn; 734 c->number = cpuid.field.number; 735 c->revision = cpuid.field.revision; 736 c->model = cpuid.field.model; 737 c->family = cpuid.field.family; 738 c->archrev = cpuid.field.archrev; 739 c->features = cpuid.field.features; 740 c->model_name = get_model_name(c->family, c->model); 741 742 status = ia64_pal_vm_summary(&vm1, &vm2); 743 if (status == PAL_STATUS_SUCCESS) { 744 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 745 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 746 } 747 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 748 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 749 } 750 751 void 752 setup_per_cpu_areas (void) 753 { 754 /* start_kernel() requires this... */ 755 #ifdef CONFIG_ACPI_HOTPLUG_CPU 756 prefill_possible_map(); 757 #endif 758 } 759 760 /* 761 * Calculate the max. cache line size. 762 * 763 * In addition, the minimum of the i-cache stride sizes is calculated for 764 * "flush_icache_range()". 765 */ 766 static void __cpuinit 767 get_max_cacheline_size (void) 768 { 769 unsigned long line_size, max = 1; 770 unsigned int cache_size = 0; 771 u64 l, levels, unique_caches; 772 pal_cache_config_info_t cci; 773 s64 status; 774 775 status = ia64_pal_cache_summary(&levels, &unique_caches); 776 if (status != 0) { 777 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 778 __FUNCTION__, status); 779 max = SMP_CACHE_BYTES; 780 /* Safest setup for "flush_icache_range()" */ 781 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 782 goto out; 783 } 784 785 for (l = 0; l < levels; ++l) { 786 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 787 &cci); 788 if (status != 0) { 789 printk(KERN_ERR 790 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 791 __FUNCTION__, l, status); 792 max = SMP_CACHE_BYTES; 793 /* The safest setup for "flush_icache_range()" */ 794 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 795 cci.pcci_unified = 1; 796 } 797 line_size = 1 << cci.pcci_line_size; 798 if (line_size > max) 799 max = line_size; 800 if (cache_size < cci.pcci_cache_size) 801 cache_size = cci.pcci_cache_size; 802 if (!cci.pcci_unified) { 803 status = ia64_pal_cache_config_info(l, 804 /* cache_type (instruction)= */ 1, 805 &cci); 806 if (status != 0) { 807 printk(KERN_ERR 808 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 809 __FUNCTION__, l, status); 810 /* The safest setup for "flush_icache_range()" */ 811 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 812 } 813 } 814 if (cci.pcci_stride < ia64_i_cache_stride_shift) 815 ia64_i_cache_stride_shift = cci.pcci_stride; 816 } 817 out: 818 #ifdef CONFIG_SMP 819 max_cache_size = max(max_cache_size, cache_size); 820 #endif 821 if (max > ia64_max_cacheline_size) 822 ia64_max_cacheline_size = max; 823 } 824 825 /* 826 * cpu_init() initializes state that is per-CPU. This function acts 827 * as a 'CPU state barrier', nothing should get across. 828 */ 829 void __cpuinit 830 cpu_init (void) 831 { 832 extern void __cpuinit ia64_mmu_init (void *); 833 unsigned long num_phys_stacked; 834 pal_vm_info_2_u_t vmi; 835 unsigned int max_ctx; 836 struct cpuinfo_ia64 *cpu_info; 837 void *cpu_data; 838 839 cpu_data = per_cpu_init(); 840 841 /* 842 * We set ar.k3 so that assembly code in MCA handler can compute 843 * physical addresses of per cpu variables with a simple: 844 * phys = ar.k3 + &per_cpu_var 845 */ 846 ia64_set_kr(IA64_KR_PER_CPU_DATA, 847 ia64_tpa(cpu_data) - (long) __per_cpu_start); 848 849 get_max_cacheline_size(); 850 851 /* 852 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 853 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 854 * depends on the data returned by identify_cpu(). We break the dependency by 855 * accessing cpu_data() through the canonical per-CPU address. 856 */ 857 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 858 identify_cpu(cpu_info); 859 860 #ifdef CONFIG_MCKINLEY 861 { 862 # define FEATURE_SET 16 863 struct ia64_pal_retval iprv; 864 865 if (cpu_info->family == 0x1f) { 866 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 867 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 868 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 869 (iprv.v1 | 0x80), FEATURE_SET, 0); 870 } 871 } 872 #endif 873 874 /* Clear the stack memory reserved for pt_regs: */ 875 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 876 877 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 878 879 /* 880 * Initialize the page-table base register to a global 881 * directory with all zeroes. This ensure that we can handle 882 * TLB-misses to user address-space even before we created the 883 * first user address-space. This may happen, e.g., due to 884 * aggressive use of lfetch.fault. 885 */ 886 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 887 888 /* 889 * Initialize default control register to defer speculative faults except 890 * for those arising from TLB misses, which are not deferred. The 891 * kernel MUST NOT depend on a particular setting of these bits (in other words, 892 * the kernel must have recovery code for all speculative accesses). Turn on 893 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 894 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 895 * be fine). 896 */ 897 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 898 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 899 atomic_inc(&init_mm.mm_count); 900 current->active_mm = &init_mm; 901 if (current->mm) 902 BUG(); 903 904 ia64_mmu_init(ia64_imva(cpu_data)); 905 ia64_mca_cpu_init(ia64_imva(cpu_data)); 906 907 #ifdef CONFIG_IA32_SUPPORT 908 ia32_cpu_init(); 909 #endif 910 911 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 912 ia64_set_itc(0); 913 914 /* disable all local interrupt sources: */ 915 ia64_set_itv(1 << 16); 916 ia64_set_lrr0(1 << 16); 917 ia64_set_lrr1(1 << 16); 918 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 919 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 920 921 /* clear TPR & XTP to enable all interrupt classes: */ 922 ia64_setreg(_IA64_REG_CR_TPR, 0); 923 #ifdef CONFIG_SMP 924 normal_xtp(); 925 #endif 926 927 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 928 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 929 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 930 else { 931 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 932 max_ctx = (1U << 15) - 1; /* use architected minimum */ 933 } 934 while (max_ctx < ia64_ctx.max_ctx) { 935 unsigned int old = ia64_ctx.max_ctx; 936 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 937 break; 938 } 939 940 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 941 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 942 "stacked regs\n"); 943 num_phys_stacked = 96; 944 } 945 /* size of physical stacked register partition plus 8 bytes: */ 946 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 947 platform_cpu_init(); 948 pm_idle = default_idle; 949 } 950 951 /* 952 * On SMP systems, when the scheduler does migration-cost autodetection, 953 * it needs a way to flush as much of the CPU's caches as possible. 954 */ 955 void sched_cacheflush(void) 956 { 957 ia64_sal_cache_flush(3); 958 } 959 960 void __init 961 check_bugs (void) 962 { 963 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 964 (unsigned long) __end___mckinley_e9_bundles); 965 } 966 967 static int __init run_dmi_scan(void) 968 { 969 dmi_scan_machine(); 970 return 0; 971 } 972 core_initcall(run_dmi_scan); 973