1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Architecture-specific setup. 4 * 5 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * Stephane Eranian <eranian@hpl.hp.com> 8 * Copyright (C) 2000, 2004 Intel Corp 9 * Rohit Seth <rohit.seth@intel.com> 10 * Suresh Siddha <suresh.b.siddha@intel.com> 11 * Gordon Jin <gordon.jin@intel.com> 12 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * 15 * 12/26/04 S.Siddha, G.Jin, R.Seth 16 * Add multi-threading and multi-core detection 17 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 18 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 19 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 20 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 21 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 22 * 01/07/99 S.Eranian added the support for command line argument 23 * 06/24/99 W.Drummond added boot_cpu_data. 24 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 25 */ 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/cpu.h> 33 #include <linux/kernel.h> 34 #include <linux/memblock.h> 35 #include <linux/reboot.h> 36 #include <linux/sched/mm.h> 37 #include <linux/sched/clock.h> 38 #include <linux/sched/task_stack.h> 39 #include <linux/seq_file.h> 40 #include <linux/string.h> 41 #include <linux/threads.h> 42 #include <linux/screen_info.h> 43 #include <linux/dmi.h> 44 #include <linux/serial.h> 45 #include <linux/serial_core.h> 46 #include <linux/efi.h> 47 #include <linux/initrd.h> 48 #include <linux/pm.h> 49 #include <linux/cpufreq.h> 50 #include <linux/kexec.h> 51 #include <linux/crash_dump.h> 52 53 #include <asm/machvec.h> 54 #include <asm/mca.h> 55 #include <asm/meminit.h> 56 #include <asm/page.h> 57 #include <asm/patch.h> 58 #include <asm/pgtable.h> 59 #include <asm/processor.h> 60 #include <asm/sal.h> 61 #include <asm/sections.h> 62 #include <asm/setup.h> 63 #include <asm/smp.h> 64 #include <asm/tlbflush.h> 65 #include <asm/unistd.h> 66 #include <asm/hpsim.h> 67 68 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 69 # error "struct cpuinfo_ia64 too big!" 70 #endif 71 72 #ifdef CONFIG_SMP 73 unsigned long __per_cpu_offset[NR_CPUS]; 74 EXPORT_SYMBOL(__per_cpu_offset); 75 #endif 76 77 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 78 EXPORT_SYMBOL(ia64_cpu_info); 79 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 80 #ifdef CONFIG_SMP 81 EXPORT_SYMBOL(local_per_cpu_offset); 82 #endif 83 unsigned long ia64_cycles_per_usec; 84 struct ia64_boot_param *ia64_boot_param; 85 struct screen_info screen_info; 86 unsigned long vga_console_iobase; 87 unsigned long vga_console_membase; 88 89 static struct resource data_resource = { 90 .name = "Kernel data", 91 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 92 }; 93 94 static struct resource code_resource = { 95 .name = "Kernel code", 96 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 97 }; 98 99 static struct resource bss_resource = { 100 .name = "Kernel bss", 101 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 102 }; 103 104 unsigned long ia64_max_cacheline_size; 105 106 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 107 EXPORT_SYMBOL(ia64_iobase); 108 struct io_space io_space[MAX_IO_SPACES]; 109 EXPORT_SYMBOL(io_space); 110 unsigned int num_io_spaces; 111 112 /* 113 * "flush_icache_range()" needs to know what processor dependent stride size to use 114 * when it makes i-cache(s) coherent with d-caches. 115 */ 116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117 unsigned long ia64_i_cache_stride_shift = ~0; 118 /* 119 * "clflush_cache_range()" needs to know what processor dependent stride size to 120 * use when it flushes cache lines including both d-cache and i-cache. 121 */ 122 /* Safest way to go: 32 bytes by 32 bytes */ 123 #define CACHE_STRIDE_SHIFT 5 124 unsigned long ia64_cache_stride_shift = ~0; 125 126 /* 127 * We use a special marker for the end of memory and it uses the extra (+1) slot 128 */ 129 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 130 int num_rsvd_regions __initdata; 131 132 133 /* 134 * Filter incoming memory segments based on the primitive map created from the boot 135 * parameters. Segments contained in the map are removed from the memory ranges. A 136 * caller-specified function is called with the memory ranges that remain after filtering. 137 * This routine does not assume the incoming segments are sorted. 138 */ 139 int __init 140 filter_rsvd_memory (u64 start, u64 end, void *arg) 141 { 142 u64 range_start, range_end, prev_start; 143 void (*func)(unsigned long, unsigned long, int); 144 int i; 145 146 #if IGNORE_PFN0 147 if (start == PAGE_OFFSET) { 148 printk(KERN_WARNING "warning: skipping physical page 0\n"); 149 start += PAGE_SIZE; 150 if (start >= end) return 0; 151 } 152 #endif 153 /* 154 * lowest possible address(walker uses virtual) 155 */ 156 prev_start = PAGE_OFFSET; 157 func = arg; 158 159 for (i = 0; i < num_rsvd_regions; ++i) { 160 range_start = max(start, prev_start); 161 range_end = min(end, rsvd_region[i].start); 162 163 if (range_start < range_end) 164 call_pernode_memory(__pa(range_start), range_end - range_start, func); 165 166 /* nothing more available in this segment */ 167 if (range_end == end) return 0; 168 169 prev_start = rsvd_region[i].end; 170 } 171 /* end of memory marker allows full processing inside loop body */ 172 return 0; 173 } 174 175 /* 176 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 177 * are not filtered out. 178 */ 179 int __init 180 filter_memory(u64 start, u64 end, void *arg) 181 { 182 void (*func)(unsigned long, unsigned long, int); 183 184 #if IGNORE_PFN0 185 if (start == PAGE_OFFSET) { 186 printk(KERN_WARNING "warning: skipping physical page 0\n"); 187 start += PAGE_SIZE; 188 if (start >= end) 189 return 0; 190 } 191 #endif 192 func = arg; 193 if (start < end) 194 call_pernode_memory(__pa(start), end - start, func); 195 return 0; 196 } 197 198 static void __init 199 sort_regions (struct rsvd_region *rsvd_region, int max) 200 { 201 int j; 202 203 /* simple bubble sorting */ 204 while (max--) { 205 for (j = 0; j < max; ++j) { 206 if (rsvd_region[j].start > rsvd_region[j+1].start) { 207 struct rsvd_region tmp; 208 tmp = rsvd_region[j]; 209 rsvd_region[j] = rsvd_region[j + 1]; 210 rsvd_region[j + 1] = tmp; 211 } 212 } 213 } 214 } 215 216 /* merge overlaps */ 217 static int __init 218 merge_regions (struct rsvd_region *rsvd_region, int max) 219 { 220 int i; 221 for (i = 1; i < max; ++i) { 222 if (rsvd_region[i].start >= rsvd_region[i-1].end) 223 continue; 224 if (rsvd_region[i].end > rsvd_region[i-1].end) 225 rsvd_region[i-1].end = rsvd_region[i].end; 226 --max; 227 memmove(&rsvd_region[i], &rsvd_region[i+1], 228 (max - i) * sizeof(struct rsvd_region)); 229 } 230 return max; 231 } 232 233 /* 234 * Request address space for all standard resources 235 */ 236 static int __init register_memory(void) 237 { 238 code_resource.start = ia64_tpa(_text); 239 code_resource.end = ia64_tpa(_etext) - 1; 240 data_resource.start = ia64_tpa(_etext); 241 data_resource.end = ia64_tpa(_edata) - 1; 242 bss_resource.start = ia64_tpa(__bss_start); 243 bss_resource.end = ia64_tpa(_end) - 1; 244 efi_initialize_iomem_resources(&code_resource, &data_resource, 245 &bss_resource); 246 247 return 0; 248 } 249 250 __initcall(register_memory); 251 252 253 #ifdef CONFIG_KEXEC 254 255 /* 256 * This function checks if the reserved crashkernel is allowed on the specific 257 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 258 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 259 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 260 * in kdump case. See the comment in sba_init() in sba_iommu.c. 261 * 262 * So, the only machvec that really supports loading the kdump kernel 263 * over 4 GB is "sn2". 264 */ 265 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 266 { 267 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 268 return 1; 269 else 270 return pbase < (1UL << 32); 271 } 272 273 static void __init setup_crashkernel(unsigned long total, int *n) 274 { 275 unsigned long long base = 0, size = 0; 276 int ret; 277 278 ret = parse_crashkernel(boot_command_line, total, 279 &size, &base); 280 if (ret == 0 && size > 0) { 281 if (!base) { 282 sort_regions(rsvd_region, *n); 283 *n = merge_regions(rsvd_region, *n); 284 base = kdump_find_rsvd_region(size, 285 rsvd_region, *n); 286 } 287 288 if (!check_crashkernel_memory(base, size)) { 289 pr_warning("crashkernel: There would be kdump memory " 290 "at %ld GB but this is unusable because it " 291 "must\nbe below 4 GB. Change the memory " 292 "configuration of the machine.\n", 293 (unsigned long)(base >> 30)); 294 return; 295 } 296 297 if (base != ~0UL) { 298 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 299 "for crashkernel (System RAM: %ldMB)\n", 300 (unsigned long)(size >> 20), 301 (unsigned long)(base >> 20), 302 (unsigned long)(total >> 20)); 303 rsvd_region[*n].start = 304 (unsigned long)__va(base); 305 rsvd_region[*n].end = 306 (unsigned long)__va(base + size); 307 (*n)++; 308 crashk_res.start = base; 309 crashk_res.end = base + size - 1; 310 } 311 } 312 efi_memmap_res.start = ia64_boot_param->efi_memmap; 313 efi_memmap_res.end = efi_memmap_res.start + 314 ia64_boot_param->efi_memmap_size; 315 boot_param_res.start = __pa(ia64_boot_param); 316 boot_param_res.end = boot_param_res.start + 317 sizeof(*ia64_boot_param); 318 } 319 #else 320 static inline void __init setup_crashkernel(unsigned long total, int *n) 321 {} 322 #endif 323 324 /** 325 * reserve_memory - setup reserved memory areas 326 * 327 * Setup the reserved memory areas set aside for the boot parameters, 328 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 329 * see arch/ia64/include/asm/meminit.h if you need to define more. 330 */ 331 void __init 332 reserve_memory (void) 333 { 334 int n = 0; 335 unsigned long total_memory; 336 337 /* 338 * none of the entries in this table overlap 339 */ 340 rsvd_region[n].start = (unsigned long) ia64_boot_param; 341 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 342 n++; 343 344 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 345 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 346 n++; 347 348 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 349 rsvd_region[n].end = (rsvd_region[n].start 350 + strlen(__va(ia64_boot_param->command_line)) + 1); 351 n++; 352 353 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 354 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 355 n++; 356 357 #ifdef CONFIG_BLK_DEV_INITRD 358 if (ia64_boot_param->initrd_start) { 359 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 360 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 361 n++; 362 } 363 #endif 364 365 #ifdef CONFIG_CRASH_DUMP 366 if (reserve_elfcorehdr(&rsvd_region[n].start, 367 &rsvd_region[n].end) == 0) 368 n++; 369 #endif 370 371 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 372 n++; 373 374 setup_crashkernel(total_memory, &n); 375 376 /* end of memory marker */ 377 rsvd_region[n].start = ~0UL; 378 rsvd_region[n].end = ~0UL; 379 n++; 380 381 num_rsvd_regions = n; 382 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 383 384 sort_regions(rsvd_region, num_rsvd_regions); 385 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions); 386 387 /* reserve all regions except the end of memory marker with memblock */ 388 for (n = 0; n < num_rsvd_regions - 1; n++) { 389 struct rsvd_region *region = &rsvd_region[n]; 390 phys_addr_t addr = __pa(region->start); 391 phys_addr_t size = region->end - region->start; 392 393 memblock_reserve(addr, size); 394 } 395 } 396 397 /** 398 * find_initrd - get initrd parameters from the boot parameter structure 399 * 400 * Grab the initrd start and end from the boot parameter struct given us by 401 * the boot loader. 402 */ 403 void __init 404 find_initrd (void) 405 { 406 #ifdef CONFIG_BLK_DEV_INITRD 407 if (ia64_boot_param->initrd_start) { 408 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 409 initrd_end = initrd_start+ia64_boot_param->initrd_size; 410 411 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 412 initrd_start, ia64_boot_param->initrd_size); 413 } 414 #endif 415 } 416 417 static void __init 418 io_port_init (void) 419 { 420 unsigned long phys_iobase; 421 422 /* 423 * Set `iobase' based on the EFI memory map or, failing that, the 424 * value firmware left in ar.k0. 425 * 426 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 427 * the port's virtual address, so ia32_load_state() loads it with a 428 * user virtual address. But in ia64 mode, glibc uses the 429 * *physical* address in ar.k0 to mmap the appropriate area from 430 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 431 * cases, user-mode can only use the legacy 0-64K I/O port space. 432 * 433 * ar.k0 is not involved in kernel I/O port accesses, which can use 434 * any of the I/O port spaces and are done via MMIO using the 435 * virtual mmio_base from the appropriate io_space[]. 436 */ 437 phys_iobase = efi_get_iobase(); 438 if (!phys_iobase) { 439 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 440 printk(KERN_INFO "No I/O port range found in EFI memory map, " 441 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 442 } 443 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 444 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 445 446 /* setup legacy IO port space */ 447 io_space[0].mmio_base = ia64_iobase; 448 io_space[0].sparse = 1; 449 num_io_spaces = 1; 450 } 451 452 /** 453 * early_console_setup - setup debugging console 454 * 455 * Consoles started here require little enough setup that we can start using 456 * them very early in the boot process, either right after the machine 457 * vector initialization, or even before if the drivers can detect their hw. 458 * 459 * Returns non-zero if a console couldn't be setup. 460 */ 461 static inline int __init 462 early_console_setup (char *cmdline) 463 { 464 int earlycons = 0; 465 466 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 467 { 468 extern int sn_serial_console_early_setup(void); 469 if (!sn_serial_console_early_setup()) 470 earlycons++; 471 } 472 #endif 473 #ifdef CONFIG_EFI_PCDP 474 if (!efi_setup_pcdp_console(cmdline)) 475 earlycons++; 476 #endif 477 if (!simcons_register()) 478 earlycons++; 479 480 return (earlycons) ? 0 : -1; 481 } 482 483 static inline void 484 mark_bsp_online (void) 485 { 486 #ifdef CONFIG_SMP 487 /* If we register an early console, allow CPU 0 to printk */ 488 set_cpu_online(smp_processor_id(), true); 489 #endif 490 } 491 492 static __initdata int nomca; 493 static __init int setup_nomca(char *s) 494 { 495 nomca = 1; 496 return 0; 497 } 498 early_param("nomca", setup_nomca); 499 500 #ifdef CONFIG_CRASH_DUMP 501 int __init reserve_elfcorehdr(u64 *start, u64 *end) 502 { 503 u64 length; 504 505 /* We get the address using the kernel command line, 506 * but the size is extracted from the EFI tables. 507 * Both address and size are required for reservation 508 * to work properly. 509 */ 510 511 if (!is_vmcore_usable()) 512 return -EINVAL; 513 514 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 515 vmcore_unusable(); 516 return -EINVAL; 517 } 518 519 *start = (unsigned long)__va(elfcorehdr_addr); 520 *end = *start + length; 521 return 0; 522 } 523 524 #endif /* CONFIG_PROC_VMCORE */ 525 526 void __init 527 setup_arch (char **cmdline_p) 528 { 529 unw_init(); 530 531 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 532 533 *cmdline_p = __va(ia64_boot_param->command_line); 534 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 535 536 efi_init(); 537 io_port_init(); 538 539 #ifdef CONFIG_IA64_GENERIC 540 /* machvec needs to be parsed from the command line 541 * before parse_early_param() is called to ensure 542 * that ia64_mv is initialised before any command line 543 * settings may cause console setup to occur 544 */ 545 machvec_init_from_cmdline(*cmdline_p); 546 #endif 547 548 parse_early_param(); 549 550 if (early_console_setup(*cmdline_p) == 0) 551 mark_bsp_online(); 552 553 #ifdef CONFIG_ACPI 554 /* Initialize the ACPI boot-time table parser */ 555 acpi_table_init(); 556 early_acpi_boot_init(); 557 # ifdef CONFIG_ACPI_NUMA 558 acpi_numa_init(); 559 acpi_numa_fixup(); 560 # ifdef CONFIG_ACPI_HOTPLUG_CPU 561 prefill_possible_map(); 562 # endif 563 per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ? 564 32 : cpumask_weight(&early_cpu_possible_map)), 565 additional_cpus > 0 ? additional_cpus : 0); 566 # endif 567 #endif /* CONFIG_APCI_BOOT */ 568 569 #ifdef CONFIG_SMP 570 smp_build_cpu_map(); 571 #endif 572 find_memory(); 573 574 /* process SAL system table: */ 575 ia64_sal_init(__va(efi.sal_systab)); 576 577 #ifdef CONFIG_ITANIUM 578 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 579 #else 580 { 581 unsigned long num_phys_stacked; 582 583 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 584 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 585 } 586 #endif 587 588 #ifdef CONFIG_SMP 589 cpu_physical_id(0) = hard_smp_processor_id(); 590 #endif 591 592 cpu_init(); /* initialize the bootstrap CPU */ 593 mmu_context_init(); /* initialize context_id bitmap */ 594 595 #ifdef CONFIG_VT 596 if (!conswitchp) { 597 # if defined(CONFIG_DUMMY_CONSOLE) 598 conswitchp = &dummy_con; 599 # endif 600 # if defined(CONFIG_VGA_CONSOLE) 601 /* 602 * Non-legacy systems may route legacy VGA MMIO range to system 603 * memory. vga_con probes the MMIO hole, so memory looks like 604 * a VGA device to it. The EFI memory map can tell us if it's 605 * memory so we can avoid this problem. 606 */ 607 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 608 conswitchp = &vga_con; 609 # endif 610 } 611 #endif 612 613 /* enable IA-64 Machine Check Abort Handling unless disabled */ 614 if (!nomca) 615 ia64_mca_init(); 616 617 platform_setup(cmdline_p); 618 #ifndef CONFIG_IA64_HP_SIM 619 check_sal_cache_flush(); 620 #endif 621 paging_init(); 622 623 clear_sched_clock_stable(); 624 } 625 626 /* 627 * Display cpu info for all CPUs. 628 */ 629 static int 630 show_cpuinfo (struct seq_file *m, void *v) 631 { 632 #ifdef CONFIG_SMP 633 # define lpj c->loops_per_jiffy 634 # define cpunum c->cpu 635 #else 636 # define lpj loops_per_jiffy 637 # define cpunum 0 638 #endif 639 static struct { 640 unsigned long mask; 641 const char *feature_name; 642 } feature_bits[] = { 643 { 1UL << 0, "branchlong" }, 644 { 1UL << 1, "spontaneous deferral"}, 645 { 1UL << 2, "16-byte atomic ops" } 646 }; 647 char features[128], *cp, *sep; 648 struct cpuinfo_ia64 *c = v; 649 unsigned long mask; 650 unsigned long proc_freq; 651 int i, size; 652 653 mask = c->features; 654 655 /* build the feature string: */ 656 memcpy(features, "standard", 9); 657 cp = features; 658 size = sizeof(features); 659 sep = ""; 660 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 661 if (mask & feature_bits[i].mask) { 662 cp += snprintf(cp, size, "%s%s", sep, 663 feature_bits[i].feature_name), 664 sep = ", "; 665 mask &= ~feature_bits[i].mask; 666 size = sizeof(features) - (cp - features); 667 } 668 } 669 if (mask && size > 1) { 670 /* print unknown features as a hex value */ 671 snprintf(cp, size, "%s0x%lx", sep, mask); 672 } 673 674 proc_freq = cpufreq_quick_get(cpunum); 675 if (!proc_freq) 676 proc_freq = c->proc_freq / 1000; 677 678 seq_printf(m, 679 "processor : %d\n" 680 "vendor : %s\n" 681 "arch : IA-64\n" 682 "family : %u\n" 683 "model : %u\n" 684 "model name : %s\n" 685 "revision : %u\n" 686 "archrev : %u\n" 687 "features : %s\n" 688 "cpu number : %lu\n" 689 "cpu regs : %u\n" 690 "cpu MHz : %lu.%03lu\n" 691 "itc MHz : %lu.%06lu\n" 692 "BogoMIPS : %lu.%02lu\n", 693 cpunum, c->vendor, c->family, c->model, 694 c->model_name, c->revision, c->archrev, 695 features, c->ppn, c->number, 696 proc_freq / 1000, proc_freq % 1000, 697 c->itc_freq / 1000000, c->itc_freq % 1000000, 698 lpj*HZ/500000, (lpj*HZ/5000) % 100); 699 #ifdef CONFIG_SMP 700 seq_printf(m, "siblings : %u\n", 701 cpumask_weight(&cpu_core_map[cpunum])); 702 if (c->socket_id != -1) 703 seq_printf(m, "physical id: %u\n", c->socket_id); 704 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 705 seq_printf(m, 706 "core id : %u\n" 707 "thread id : %u\n", 708 c->core_id, c->thread_id); 709 #endif 710 seq_printf(m,"\n"); 711 712 return 0; 713 } 714 715 static void * 716 c_start (struct seq_file *m, loff_t *pos) 717 { 718 #ifdef CONFIG_SMP 719 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 720 ++*pos; 721 #endif 722 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 723 } 724 725 static void * 726 c_next (struct seq_file *m, void *v, loff_t *pos) 727 { 728 ++*pos; 729 return c_start(m, pos); 730 } 731 732 static void 733 c_stop (struct seq_file *m, void *v) 734 { 735 } 736 737 const struct seq_operations cpuinfo_op = { 738 .start = c_start, 739 .next = c_next, 740 .stop = c_stop, 741 .show = show_cpuinfo 742 }; 743 744 #define MAX_BRANDS 8 745 static char brandname[MAX_BRANDS][128]; 746 747 static char * 748 get_model_name(__u8 family, __u8 model) 749 { 750 static int overflow; 751 char brand[128]; 752 int i; 753 754 memcpy(brand, "Unknown", 8); 755 if (ia64_pal_get_brand_info(brand)) { 756 if (family == 0x7) 757 memcpy(brand, "Merced", 7); 758 else if (family == 0x1f) switch (model) { 759 case 0: memcpy(brand, "McKinley", 9); break; 760 case 1: memcpy(brand, "Madison", 8); break; 761 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 762 } 763 } 764 for (i = 0; i < MAX_BRANDS; i++) 765 if (strcmp(brandname[i], brand) == 0) 766 return brandname[i]; 767 for (i = 0; i < MAX_BRANDS; i++) 768 if (brandname[i][0] == '\0') 769 return strcpy(brandname[i], brand); 770 if (overflow++ == 0) 771 printk(KERN_ERR 772 "%s: Table overflow. Some processor model information will be missing\n", 773 __func__); 774 return "Unknown"; 775 } 776 777 static void 778 identify_cpu (struct cpuinfo_ia64 *c) 779 { 780 union { 781 unsigned long bits[5]; 782 struct { 783 /* id 0 & 1: */ 784 char vendor[16]; 785 786 /* id 2 */ 787 u64 ppn; /* processor serial number */ 788 789 /* id 3: */ 790 unsigned number : 8; 791 unsigned revision : 8; 792 unsigned model : 8; 793 unsigned family : 8; 794 unsigned archrev : 8; 795 unsigned reserved : 24; 796 797 /* id 4: */ 798 u64 features; 799 } field; 800 } cpuid; 801 pal_vm_info_1_u_t vm1; 802 pal_vm_info_2_u_t vm2; 803 pal_status_t status; 804 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 805 int i; 806 for (i = 0; i < 5; ++i) 807 cpuid.bits[i] = ia64_get_cpuid(i); 808 809 memcpy(c->vendor, cpuid.field.vendor, 16); 810 #ifdef CONFIG_SMP 811 c->cpu = smp_processor_id(); 812 813 /* below default values will be overwritten by identify_siblings() 814 * for Multi-Threading/Multi-Core capable CPUs 815 */ 816 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 817 c->socket_id = -1; 818 819 identify_siblings(c); 820 821 if (c->threads_per_core > smp_num_siblings) 822 smp_num_siblings = c->threads_per_core; 823 #endif 824 c->ppn = cpuid.field.ppn; 825 c->number = cpuid.field.number; 826 c->revision = cpuid.field.revision; 827 c->model = cpuid.field.model; 828 c->family = cpuid.field.family; 829 c->archrev = cpuid.field.archrev; 830 c->features = cpuid.field.features; 831 c->model_name = get_model_name(c->family, c->model); 832 833 status = ia64_pal_vm_summary(&vm1, &vm2); 834 if (status == PAL_STATUS_SUCCESS) { 835 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 836 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 837 } 838 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 839 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 840 } 841 842 /* 843 * Do the following calculations: 844 * 845 * 1. the max. cache line size. 846 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 847 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 848 */ 849 static void 850 get_cache_info(void) 851 { 852 unsigned long line_size, max = 1; 853 unsigned long l, levels, unique_caches; 854 pal_cache_config_info_t cci; 855 long status; 856 857 status = ia64_pal_cache_summary(&levels, &unique_caches); 858 if (status != 0) { 859 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 860 __func__, status); 861 max = SMP_CACHE_BYTES; 862 /* Safest setup for "flush_icache_range()" */ 863 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 864 /* Safest setup for "clflush_cache_range()" */ 865 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 866 goto out; 867 } 868 869 for (l = 0; l < levels; ++l) { 870 /* cache_type (data_or_unified)=2 */ 871 status = ia64_pal_cache_config_info(l, 2, &cci); 872 if (status != 0) { 873 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 874 "(l=%lu, 2) failed (status=%ld)\n", 875 __func__, l, status); 876 max = SMP_CACHE_BYTES; 877 /* The safest setup for "flush_icache_range()" */ 878 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 879 /* The safest setup for "clflush_cache_range()" */ 880 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 881 cci.pcci_unified = 1; 882 } else { 883 if (cci.pcci_stride < ia64_cache_stride_shift) 884 ia64_cache_stride_shift = cci.pcci_stride; 885 886 line_size = 1 << cci.pcci_line_size; 887 if (line_size > max) 888 max = line_size; 889 } 890 891 if (!cci.pcci_unified) { 892 /* cache_type (instruction)=1*/ 893 status = ia64_pal_cache_config_info(l, 1, &cci); 894 if (status != 0) { 895 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 896 "(l=%lu, 1) failed (status=%ld)\n", 897 __func__, l, status); 898 /* The safest setup for flush_icache_range() */ 899 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 900 } 901 } 902 if (cci.pcci_stride < ia64_i_cache_stride_shift) 903 ia64_i_cache_stride_shift = cci.pcci_stride; 904 } 905 out: 906 if (max > ia64_max_cacheline_size) 907 ia64_max_cacheline_size = max; 908 } 909 910 /* 911 * cpu_init() initializes state that is per-CPU. This function acts 912 * as a 'CPU state barrier', nothing should get across. 913 */ 914 void 915 cpu_init (void) 916 { 917 extern void ia64_mmu_init(void *); 918 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 919 unsigned long num_phys_stacked; 920 pal_vm_info_2_u_t vmi; 921 unsigned int max_ctx; 922 struct cpuinfo_ia64 *cpu_info; 923 void *cpu_data; 924 925 cpu_data = per_cpu_init(); 926 #ifdef CONFIG_SMP 927 /* 928 * insert boot cpu into sibling and core mapes 929 * (must be done after per_cpu area is setup) 930 */ 931 if (smp_processor_id() == 0) { 932 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0)); 933 cpumask_set_cpu(0, &cpu_core_map[0]); 934 } else { 935 /* 936 * Set ar.k3 so that assembly code in MCA handler can compute 937 * physical addresses of per cpu variables with a simple: 938 * phys = ar.k3 + &per_cpu_var 939 * and the alt-dtlb-miss handler can set per-cpu mapping into 940 * the TLB when needed. head.S already did this for cpu0. 941 */ 942 ia64_set_kr(IA64_KR_PER_CPU_DATA, 943 ia64_tpa(cpu_data) - (long) __per_cpu_start); 944 } 945 #endif 946 947 get_cache_info(); 948 949 /* 950 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 951 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 952 * depends on the data returned by identify_cpu(). We break the dependency by 953 * accessing cpu_data() through the canonical per-CPU address. 954 */ 955 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 956 identify_cpu(cpu_info); 957 958 #ifdef CONFIG_MCKINLEY 959 { 960 # define FEATURE_SET 16 961 struct ia64_pal_retval iprv; 962 963 if (cpu_info->family == 0x1f) { 964 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 965 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 966 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 967 (iprv.v1 | 0x80), FEATURE_SET, 0); 968 } 969 } 970 #endif 971 972 /* Clear the stack memory reserved for pt_regs: */ 973 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 974 975 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 976 977 /* 978 * Initialize the page-table base register to a global 979 * directory with all zeroes. This ensure that we can handle 980 * TLB-misses to user address-space even before we created the 981 * first user address-space. This may happen, e.g., due to 982 * aggressive use of lfetch.fault. 983 */ 984 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 985 986 /* 987 * Initialize default control register to defer speculative faults except 988 * for those arising from TLB misses, which are not deferred. The 989 * kernel MUST NOT depend on a particular setting of these bits (in other words, 990 * the kernel must have recovery code for all speculative accesses). Turn on 991 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 992 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 993 * be fine). 994 */ 995 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 996 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 997 mmgrab(&init_mm); 998 current->active_mm = &init_mm; 999 BUG_ON(current->mm); 1000 1001 ia64_mmu_init(ia64_imva(cpu_data)); 1002 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1003 1004 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1005 ia64_set_itc(0); 1006 1007 /* disable all local interrupt sources: */ 1008 ia64_set_itv(1 << 16); 1009 ia64_set_lrr0(1 << 16); 1010 ia64_set_lrr1(1 << 16); 1011 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1012 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1013 1014 /* clear TPR & XTP to enable all interrupt classes: */ 1015 ia64_setreg(_IA64_REG_CR_TPR, 0); 1016 1017 /* Clear any pending interrupts left by SAL/EFI */ 1018 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1019 ia64_eoi(); 1020 1021 #ifdef CONFIG_SMP 1022 normal_xtp(); 1023 #endif 1024 1025 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1026 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1027 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1028 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1029 } else { 1030 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1031 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1032 } 1033 while (max_ctx < ia64_ctx.max_ctx) { 1034 unsigned int old = ia64_ctx.max_ctx; 1035 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1036 break; 1037 } 1038 1039 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1040 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1041 "stacked regs\n"); 1042 num_phys_stacked = 96; 1043 } 1044 /* size of physical stacked register partition plus 8 bytes: */ 1045 if (num_phys_stacked > max_num_phys_stacked) { 1046 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1047 max_num_phys_stacked = num_phys_stacked; 1048 } 1049 platform_cpu_init(); 1050 } 1051 1052 void __init 1053 check_bugs (void) 1054 { 1055 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1056 (unsigned long) __end___mckinley_e9_bundles); 1057 } 1058 1059 static int __init run_dmi_scan(void) 1060 { 1061 dmi_setup(); 1062 return 0; 1063 } 1064 core_initcall(run_dmi_scan); 1065