1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/paravirt.h> 55 #include <asm/patch.h> 56 #include <asm/pgtable.h> 57 #include <asm/processor.h> 58 #include <asm/sal.h> 59 #include <asm/sections.h> 60 #include <asm/setup.h> 61 #include <asm/smp.h> 62 #include <asm/system.h> 63 #include <asm/tlbflush.h> 64 #include <asm/unistd.h> 65 #include <asm/hpsim.h> 66 67 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 68 # error "struct cpuinfo_ia64 too big!" 69 #endif 70 71 #ifdef CONFIG_SMP 72 unsigned long __per_cpu_offset[NR_CPUS]; 73 EXPORT_SYMBOL(__per_cpu_offset); 74 #endif 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 94 static struct resource bss_resource = { 95 .name = "Kernel bss", 96 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 97 }; 98 99 unsigned long ia64_max_cacheline_size; 100 101 int dma_get_cache_alignment(void) 102 { 103 return ia64_max_cacheline_size; 104 } 105 EXPORT_SYMBOL(dma_get_cache_alignment); 106 107 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 108 EXPORT_SYMBOL(ia64_iobase); 109 struct io_space io_space[MAX_IO_SPACES]; 110 EXPORT_SYMBOL(io_space); 111 unsigned int num_io_spaces; 112 113 /* 114 * "flush_icache_range()" needs to know what processor dependent stride size to use 115 * when it makes i-cache(s) coherent with d-caches. 116 */ 117 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 118 unsigned long ia64_i_cache_stride_shift = ~0; 119 120 /* 121 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 122 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 123 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 124 * address of the second buffer must be aligned to (merge_mask+1) in order to be 125 * mergeable). By default, we assume there is no I/O MMU which can merge physically 126 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 127 * page-size of 2^64. 128 */ 129 unsigned long ia64_max_iommu_merge_mask = ~0UL; 130 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 131 132 /* 133 * We use a special marker for the end of memory and it uses the extra (+1) slot 134 */ 135 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 136 int num_rsvd_regions __initdata; 137 138 139 /* 140 * Filter incoming memory segments based on the primitive map created from the boot 141 * parameters. Segments contained in the map are removed from the memory ranges. A 142 * caller-specified function is called with the memory ranges that remain after filtering. 143 * This routine does not assume the incoming segments are sorted. 144 */ 145 int __init 146 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 147 { 148 unsigned long range_start, range_end, prev_start; 149 void (*func)(unsigned long, unsigned long, int); 150 int i; 151 152 #if IGNORE_PFN0 153 if (start == PAGE_OFFSET) { 154 printk(KERN_WARNING "warning: skipping physical page 0\n"); 155 start += PAGE_SIZE; 156 if (start >= end) return 0; 157 } 158 #endif 159 /* 160 * lowest possible address(walker uses virtual) 161 */ 162 prev_start = PAGE_OFFSET; 163 func = arg; 164 165 for (i = 0; i < num_rsvd_regions; ++i) { 166 range_start = max(start, prev_start); 167 range_end = min(end, rsvd_region[i].start); 168 169 if (range_start < range_end) 170 call_pernode_memory(__pa(range_start), range_end - range_start, func); 171 172 /* nothing more available in this segment */ 173 if (range_end == end) return 0; 174 175 prev_start = rsvd_region[i].end; 176 } 177 /* end of memory marker allows full processing inside loop body */ 178 return 0; 179 } 180 181 /* 182 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 183 * are not filtered out. 184 */ 185 int __init 186 filter_memory(unsigned long start, unsigned long end, void *arg) 187 { 188 void (*func)(unsigned long, unsigned long, int); 189 190 #if IGNORE_PFN0 191 if (start == PAGE_OFFSET) { 192 printk(KERN_WARNING "warning: skipping physical page 0\n"); 193 start += PAGE_SIZE; 194 if (start >= end) 195 return 0; 196 } 197 #endif 198 func = arg; 199 if (start < end) 200 call_pernode_memory(__pa(start), end - start, func); 201 return 0; 202 } 203 204 static void __init 205 sort_regions (struct rsvd_region *rsvd_region, int max) 206 { 207 int j; 208 209 /* simple bubble sorting */ 210 while (max--) { 211 for (j = 0; j < max; ++j) { 212 if (rsvd_region[j].start > rsvd_region[j+1].start) { 213 struct rsvd_region tmp; 214 tmp = rsvd_region[j]; 215 rsvd_region[j] = rsvd_region[j + 1]; 216 rsvd_region[j + 1] = tmp; 217 } 218 } 219 } 220 } 221 222 /* 223 * Request address space for all standard resources 224 */ 225 static int __init register_memory(void) 226 { 227 code_resource.start = ia64_tpa(_text); 228 code_resource.end = ia64_tpa(_etext) - 1; 229 data_resource.start = ia64_tpa(_etext); 230 data_resource.end = ia64_tpa(_edata) - 1; 231 bss_resource.start = ia64_tpa(__bss_start); 232 bss_resource.end = ia64_tpa(_end) - 1; 233 efi_initialize_iomem_resources(&code_resource, &data_resource, 234 &bss_resource); 235 236 return 0; 237 } 238 239 __initcall(register_memory); 240 241 242 #ifdef CONFIG_KEXEC 243 244 /* 245 * This function checks if the reserved crashkernel is allowed on the specific 246 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 247 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 248 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 249 * in kdump case. See the comment in sba_init() in sba_iommu.c. 250 * 251 * So, the only machvec that really supports loading the kdump kernel 252 * over 4 GB is "sn2". 253 */ 254 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 255 { 256 if (ia64_platform_is("sn2") || ia64_platform_is("uv")) 257 return 1; 258 else 259 return pbase < (1UL << 32); 260 } 261 262 static void __init setup_crashkernel(unsigned long total, int *n) 263 { 264 unsigned long long base = 0, size = 0; 265 int ret; 266 267 ret = parse_crashkernel(boot_command_line, total, 268 &size, &base); 269 if (ret == 0 && size > 0) { 270 if (!base) { 271 sort_regions(rsvd_region, *n); 272 base = kdump_find_rsvd_region(size, 273 rsvd_region, *n); 274 } 275 276 if (!check_crashkernel_memory(base, size)) { 277 pr_warning("crashkernel: There would be kdump memory " 278 "at %ld GB but this is unusable because it " 279 "must\nbe below 4 GB. Change the memory " 280 "configuration of the machine.\n", 281 (unsigned long)(base >> 30)); 282 return; 283 } 284 285 if (base != ~0UL) { 286 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 287 "for crashkernel (System RAM: %ldMB)\n", 288 (unsigned long)(size >> 20), 289 (unsigned long)(base >> 20), 290 (unsigned long)(total >> 20)); 291 rsvd_region[*n].start = 292 (unsigned long)__va(base); 293 rsvd_region[*n].end = 294 (unsigned long)__va(base + size); 295 (*n)++; 296 crashk_res.start = base; 297 crashk_res.end = base + size - 1; 298 } 299 } 300 efi_memmap_res.start = ia64_boot_param->efi_memmap; 301 efi_memmap_res.end = efi_memmap_res.start + 302 ia64_boot_param->efi_memmap_size; 303 boot_param_res.start = __pa(ia64_boot_param); 304 boot_param_res.end = boot_param_res.start + 305 sizeof(*ia64_boot_param); 306 } 307 #else 308 static inline void __init setup_crashkernel(unsigned long total, int *n) 309 {} 310 #endif 311 312 /** 313 * reserve_memory - setup reserved memory areas 314 * 315 * Setup the reserved memory areas set aside for the boot parameters, 316 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 317 * see arch/ia64/include/asm/meminit.h if you need to define more. 318 */ 319 void __init 320 reserve_memory (void) 321 { 322 int n = 0; 323 unsigned long total_memory; 324 325 /* 326 * none of the entries in this table overlap 327 */ 328 rsvd_region[n].start = (unsigned long) ia64_boot_param; 329 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 330 n++; 331 332 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 333 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 334 n++; 335 336 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 337 rsvd_region[n].end = (rsvd_region[n].start 338 + strlen(__va(ia64_boot_param->command_line)) + 1); 339 n++; 340 341 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 342 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 343 n++; 344 345 n += paravirt_reserve_memory(&rsvd_region[n]); 346 347 #ifdef CONFIG_BLK_DEV_INITRD 348 if (ia64_boot_param->initrd_start) { 349 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 350 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 351 n++; 352 } 353 #endif 354 355 #ifdef CONFIG_PROC_VMCORE 356 if (reserve_elfcorehdr(&rsvd_region[n].start, 357 &rsvd_region[n].end) == 0) 358 n++; 359 #endif 360 361 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 362 n++; 363 364 setup_crashkernel(total_memory, &n); 365 366 /* end of memory marker */ 367 rsvd_region[n].start = ~0UL; 368 rsvd_region[n].end = ~0UL; 369 n++; 370 371 num_rsvd_regions = n; 372 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 373 374 sort_regions(rsvd_region, num_rsvd_regions); 375 } 376 377 378 /** 379 * find_initrd - get initrd parameters from the boot parameter structure 380 * 381 * Grab the initrd start and end from the boot parameter struct given us by 382 * the boot loader. 383 */ 384 void __init 385 find_initrd (void) 386 { 387 #ifdef CONFIG_BLK_DEV_INITRD 388 if (ia64_boot_param->initrd_start) { 389 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 390 initrd_end = initrd_start+ia64_boot_param->initrd_size; 391 392 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 393 initrd_start, ia64_boot_param->initrd_size); 394 } 395 #endif 396 } 397 398 static void __init 399 io_port_init (void) 400 { 401 unsigned long phys_iobase; 402 403 /* 404 * Set `iobase' based on the EFI memory map or, failing that, the 405 * value firmware left in ar.k0. 406 * 407 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 408 * the port's virtual address, so ia32_load_state() loads it with a 409 * user virtual address. But in ia64 mode, glibc uses the 410 * *physical* address in ar.k0 to mmap the appropriate area from 411 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 412 * cases, user-mode can only use the legacy 0-64K I/O port space. 413 * 414 * ar.k0 is not involved in kernel I/O port accesses, which can use 415 * any of the I/O port spaces and are done via MMIO using the 416 * virtual mmio_base from the appropriate io_space[]. 417 */ 418 phys_iobase = efi_get_iobase(); 419 if (!phys_iobase) { 420 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 421 printk(KERN_INFO "No I/O port range found in EFI memory map, " 422 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 423 } 424 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 425 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 426 427 /* setup legacy IO port space */ 428 io_space[0].mmio_base = ia64_iobase; 429 io_space[0].sparse = 1; 430 num_io_spaces = 1; 431 } 432 433 /** 434 * early_console_setup - setup debugging console 435 * 436 * Consoles started here require little enough setup that we can start using 437 * them very early in the boot process, either right after the machine 438 * vector initialization, or even before if the drivers can detect their hw. 439 * 440 * Returns non-zero if a console couldn't be setup. 441 */ 442 static inline int __init 443 early_console_setup (char *cmdline) 444 { 445 int earlycons = 0; 446 447 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 448 { 449 extern int sn_serial_console_early_setup(void); 450 if (!sn_serial_console_early_setup()) 451 earlycons++; 452 } 453 #endif 454 #ifdef CONFIG_EFI_PCDP 455 if (!efi_setup_pcdp_console(cmdline)) 456 earlycons++; 457 #endif 458 if (!simcons_register()) 459 earlycons++; 460 461 return (earlycons) ? 0 : -1; 462 } 463 464 static inline void 465 mark_bsp_online (void) 466 { 467 #ifdef CONFIG_SMP 468 /* If we register an early console, allow CPU 0 to printk */ 469 cpu_set(smp_processor_id(), cpu_online_map); 470 #endif 471 } 472 473 static __initdata int nomca; 474 static __init int setup_nomca(char *s) 475 { 476 nomca = 1; 477 return 0; 478 } 479 early_param("nomca", setup_nomca); 480 481 #ifdef CONFIG_PROC_VMCORE 482 /* elfcorehdr= specifies the location of elf core header 483 * stored by the crashed kernel. 484 */ 485 static int __init parse_elfcorehdr(char *arg) 486 { 487 if (!arg) 488 return -EINVAL; 489 490 elfcorehdr_addr = memparse(arg, &arg); 491 return 0; 492 } 493 early_param("elfcorehdr", parse_elfcorehdr); 494 495 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 496 { 497 unsigned long length; 498 499 /* We get the address using the kernel command line, 500 * but the size is extracted from the EFI tables. 501 * Both address and size are required for reservation 502 * to work properly. 503 */ 504 505 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) 506 return -EINVAL; 507 508 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 509 elfcorehdr_addr = ELFCORE_ADDR_MAX; 510 return -EINVAL; 511 } 512 513 *start = (unsigned long)__va(elfcorehdr_addr); 514 *end = *start + length; 515 return 0; 516 } 517 518 #endif /* CONFIG_PROC_VMCORE */ 519 520 void __init 521 setup_arch (char **cmdline_p) 522 { 523 unw_init(); 524 525 paravirt_arch_setup_early(); 526 527 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 528 529 *cmdline_p = __va(ia64_boot_param->command_line); 530 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 531 532 efi_init(); 533 io_port_init(); 534 535 #ifdef CONFIG_IA64_GENERIC 536 /* machvec needs to be parsed from the command line 537 * before parse_early_param() is called to ensure 538 * that ia64_mv is initialised before any command line 539 * settings may cause console setup to occur 540 */ 541 machvec_init_from_cmdline(*cmdline_p); 542 #endif 543 544 parse_early_param(); 545 546 if (early_console_setup(*cmdline_p) == 0) 547 mark_bsp_online(); 548 549 #ifdef CONFIG_ACPI 550 /* Initialize the ACPI boot-time table parser */ 551 acpi_table_init(); 552 # ifdef CONFIG_ACPI_NUMA 553 acpi_numa_init(); 554 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ? 555 32 : cpus_weight(early_cpu_possible_map)), 556 additional_cpus > 0 ? additional_cpus : 0); 557 # endif 558 #else 559 # ifdef CONFIG_SMP 560 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 561 # endif 562 #endif /* CONFIG_APCI_BOOT */ 563 564 find_memory(); 565 566 /* process SAL system table: */ 567 ia64_sal_init(__va(efi.sal_systab)); 568 569 #ifdef CONFIG_ITANIUM 570 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 571 #else 572 { 573 u64 num_phys_stacked; 574 575 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 576 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 577 } 578 #endif 579 580 #ifdef CONFIG_SMP 581 cpu_physical_id(0) = hard_smp_processor_id(); 582 #endif 583 584 cpu_init(); /* initialize the bootstrap CPU */ 585 mmu_context_init(); /* initialize context_id bitmap */ 586 587 #ifdef CONFIG_ACPI 588 acpi_boot_init(); 589 #endif 590 591 paravirt_banner(); 592 paravirt_arch_setup_console(cmdline_p); 593 594 #ifdef CONFIG_VT 595 if (!conswitchp) { 596 # if defined(CONFIG_DUMMY_CONSOLE) 597 conswitchp = &dummy_con; 598 # endif 599 # if defined(CONFIG_VGA_CONSOLE) 600 /* 601 * Non-legacy systems may route legacy VGA MMIO range to system 602 * memory. vga_con probes the MMIO hole, so memory looks like 603 * a VGA device to it. The EFI memory map can tell us if it's 604 * memory so we can avoid this problem. 605 */ 606 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 607 conswitchp = &vga_con; 608 # endif 609 } 610 #endif 611 612 /* enable IA-64 Machine Check Abort Handling unless disabled */ 613 if (paravirt_arch_setup_nomca()) 614 nomca = 1; 615 if (!nomca) 616 ia64_mca_init(); 617 618 platform_setup(cmdline_p); 619 #ifndef CONFIG_IA64_HP_SIM 620 check_sal_cache_flush(); 621 #endif 622 paging_init(); 623 } 624 625 /* 626 * Display cpu info for all CPUs. 627 */ 628 static int 629 show_cpuinfo (struct seq_file *m, void *v) 630 { 631 #ifdef CONFIG_SMP 632 # define lpj c->loops_per_jiffy 633 # define cpunum c->cpu 634 #else 635 # define lpj loops_per_jiffy 636 # define cpunum 0 637 #endif 638 static struct { 639 unsigned long mask; 640 const char *feature_name; 641 } feature_bits[] = { 642 { 1UL << 0, "branchlong" }, 643 { 1UL << 1, "spontaneous deferral"}, 644 { 1UL << 2, "16-byte atomic ops" } 645 }; 646 char features[128], *cp, *sep; 647 struct cpuinfo_ia64 *c = v; 648 unsigned long mask; 649 unsigned long proc_freq; 650 int i, size; 651 652 mask = c->features; 653 654 /* build the feature string: */ 655 memcpy(features, "standard", 9); 656 cp = features; 657 size = sizeof(features); 658 sep = ""; 659 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 660 if (mask & feature_bits[i].mask) { 661 cp += snprintf(cp, size, "%s%s", sep, 662 feature_bits[i].feature_name), 663 sep = ", "; 664 mask &= ~feature_bits[i].mask; 665 size = sizeof(features) - (cp - features); 666 } 667 } 668 if (mask && size > 1) { 669 /* print unknown features as a hex value */ 670 snprintf(cp, size, "%s0x%lx", sep, mask); 671 } 672 673 proc_freq = cpufreq_quick_get(cpunum); 674 if (!proc_freq) 675 proc_freq = c->proc_freq / 1000; 676 677 seq_printf(m, 678 "processor : %d\n" 679 "vendor : %s\n" 680 "arch : IA-64\n" 681 "family : %u\n" 682 "model : %u\n" 683 "model name : %s\n" 684 "revision : %u\n" 685 "archrev : %u\n" 686 "features : %s\n" 687 "cpu number : %lu\n" 688 "cpu regs : %u\n" 689 "cpu MHz : %lu.%03lu\n" 690 "itc MHz : %lu.%06lu\n" 691 "BogoMIPS : %lu.%02lu\n", 692 cpunum, c->vendor, c->family, c->model, 693 c->model_name, c->revision, c->archrev, 694 features, c->ppn, c->number, 695 proc_freq / 1000, proc_freq % 1000, 696 c->itc_freq / 1000000, c->itc_freq % 1000000, 697 lpj*HZ/500000, (lpj*HZ/5000) % 100); 698 #ifdef CONFIG_SMP 699 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 700 if (c->socket_id != -1) 701 seq_printf(m, "physical id: %u\n", c->socket_id); 702 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 703 seq_printf(m, 704 "core id : %u\n" 705 "thread id : %u\n", 706 c->core_id, c->thread_id); 707 #endif 708 seq_printf(m,"\n"); 709 710 return 0; 711 } 712 713 static void * 714 c_start (struct seq_file *m, loff_t *pos) 715 { 716 #ifdef CONFIG_SMP 717 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 718 ++*pos; 719 #endif 720 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 721 } 722 723 static void * 724 c_next (struct seq_file *m, void *v, loff_t *pos) 725 { 726 ++*pos; 727 return c_start(m, pos); 728 } 729 730 static void 731 c_stop (struct seq_file *m, void *v) 732 { 733 } 734 735 const struct seq_operations cpuinfo_op = { 736 .start = c_start, 737 .next = c_next, 738 .stop = c_stop, 739 .show = show_cpuinfo 740 }; 741 742 #define MAX_BRANDS 8 743 static char brandname[MAX_BRANDS][128]; 744 745 static char * __cpuinit 746 get_model_name(__u8 family, __u8 model) 747 { 748 static int overflow; 749 char brand[128]; 750 int i; 751 752 memcpy(brand, "Unknown", 8); 753 if (ia64_pal_get_brand_info(brand)) { 754 if (family == 0x7) 755 memcpy(brand, "Merced", 7); 756 else if (family == 0x1f) switch (model) { 757 case 0: memcpy(brand, "McKinley", 9); break; 758 case 1: memcpy(brand, "Madison", 8); break; 759 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 760 } 761 } 762 for (i = 0; i < MAX_BRANDS; i++) 763 if (strcmp(brandname[i], brand) == 0) 764 return brandname[i]; 765 for (i = 0; i < MAX_BRANDS; i++) 766 if (brandname[i][0] == '\0') 767 return strcpy(brandname[i], brand); 768 if (overflow++ == 0) 769 printk(KERN_ERR 770 "%s: Table overflow. Some processor model information will be missing\n", 771 __func__); 772 return "Unknown"; 773 } 774 775 static void __cpuinit 776 identify_cpu (struct cpuinfo_ia64 *c) 777 { 778 union { 779 unsigned long bits[5]; 780 struct { 781 /* id 0 & 1: */ 782 char vendor[16]; 783 784 /* id 2 */ 785 u64 ppn; /* processor serial number */ 786 787 /* id 3: */ 788 unsigned number : 8; 789 unsigned revision : 8; 790 unsigned model : 8; 791 unsigned family : 8; 792 unsigned archrev : 8; 793 unsigned reserved : 24; 794 795 /* id 4: */ 796 u64 features; 797 } field; 798 } cpuid; 799 pal_vm_info_1_u_t vm1; 800 pal_vm_info_2_u_t vm2; 801 pal_status_t status; 802 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 803 int i; 804 for (i = 0; i < 5; ++i) 805 cpuid.bits[i] = ia64_get_cpuid(i); 806 807 memcpy(c->vendor, cpuid.field.vendor, 16); 808 #ifdef CONFIG_SMP 809 c->cpu = smp_processor_id(); 810 811 /* below default values will be overwritten by identify_siblings() 812 * for Multi-Threading/Multi-Core capable CPUs 813 */ 814 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 815 c->socket_id = -1; 816 817 identify_siblings(c); 818 819 if (c->threads_per_core > smp_num_siblings) 820 smp_num_siblings = c->threads_per_core; 821 #endif 822 c->ppn = cpuid.field.ppn; 823 c->number = cpuid.field.number; 824 c->revision = cpuid.field.revision; 825 c->model = cpuid.field.model; 826 c->family = cpuid.field.family; 827 c->archrev = cpuid.field.archrev; 828 c->features = cpuid.field.features; 829 c->model_name = get_model_name(c->family, c->model); 830 831 status = ia64_pal_vm_summary(&vm1, &vm2); 832 if (status == PAL_STATUS_SUCCESS) { 833 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 834 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 835 } 836 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 837 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 838 } 839 840 void __init 841 setup_per_cpu_areas (void) 842 { 843 /* start_kernel() requires this... */ 844 #ifdef CONFIG_ACPI_HOTPLUG_CPU 845 prefill_possible_map(); 846 #endif 847 } 848 849 /* 850 * Calculate the max. cache line size. 851 * 852 * In addition, the minimum of the i-cache stride sizes is calculated for 853 * "flush_icache_range()". 854 */ 855 static void __cpuinit 856 get_max_cacheline_size (void) 857 { 858 unsigned long line_size, max = 1; 859 u64 l, levels, unique_caches; 860 pal_cache_config_info_t cci; 861 s64 status; 862 863 status = ia64_pal_cache_summary(&levels, &unique_caches); 864 if (status != 0) { 865 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 866 __func__, status); 867 max = SMP_CACHE_BYTES; 868 /* Safest setup for "flush_icache_range()" */ 869 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 870 goto out; 871 } 872 873 for (l = 0; l < levels; ++l) { 874 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 875 &cci); 876 if (status != 0) { 877 printk(KERN_ERR 878 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 879 __func__, l, status); 880 max = SMP_CACHE_BYTES; 881 /* The safest setup for "flush_icache_range()" */ 882 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 883 cci.pcci_unified = 1; 884 } 885 line_size = 1 << cci.pcci_line_size; 886 if (line_size > max) 887 max = line_size; 888 if (!cci.pcci_unified) { 889 status = ia64_pal_cache_config_info(l, 890 /* cache_type (instruction)= */ 1, 891 &cci); 892 if (status != 0) { 893 printk(KERN_ERR 894 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 895 __func__, l, status); 896 /* The safest setup for "flush_icache_range()" */ 897 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 898 } 899 } 900 if (cci.pcci_stride < ia64_i_cache_stride_shift) 901 ia64_i_cache_stride_shift = cci.pcci_stride; 902 } 903 out: 904 if (max > ia64_max_cacheline_size) 905 ia64_max_cacheline_size = max; 906 } 907 908 /* 909 * cpu_init() initializes state that is per-CPU. This function acts 910 * as a 'CPU state barrier', nothing should get across. 911 */ 912 void __cpuinit 913 cpu_init (void) 914 { 915 extern void __cpuinit ia64_mmu_init (void *); 916 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 917 unsigned long num_phys_stacked; 918 pal_vm_info_2_u_t vmi; 919 unsigned int max_ctx; 920 struct cpuinfo_ia64 *cpu_info; 921 void *cpu_data; 922 923 cpu_data = per_cpu_init(); 924 #ifdef CONFIG_SMP 925 /* 926 * insert boot cpu into sibling and core mapes 927 * (must be done after per_cpu area is setup) 928 */ 929 if (smp_processor_id() == 0) { 930 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 931 cpu_set(0, cpu_core_map[0]); 932 } else { 933 /* 934 * Set ar.k3 so that assembly code in MCA handler can compute 935 * physical addresses of per cpu variables with a simple: 936 * phys = ar.k3 + &per_cpu_var 937 * and the alt-dtlb-miss handler can set per-cpu mapping into 938 * the TLB when needed. head.S already did this for cpu0. 939 */ 940 ia64_set_kr(IA64_KR_PER_CPU_DATA, 941 ia64_tpa(cpu_data) - (long) __per_cpu_start); 942 } 943 #endif 944 945 get_max_cacheline_size(); 946 947 /* 948 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 949 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 950 * depends on the data returned by identify_cpu(). We break the dependency by 951 * accessing cpu_data() through the canonical per-CPU address. 952 */ 953 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 954 identify_cpu(cpu_info); 955 956 #ifdef CONFIG_MCKINLEY 957 { 958 # define FEATURE_SET 16 959 struct ia64_pal_retval iprv; 960 961 if (cpu_info->family == 0x1f) { 962 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 963 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 964 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 965 (iprv.v1 | 0x80), FEATURE_SET, 0); 966 } 967 } 968 #endif 969 970 /* Clear the stack memory reserved for pt_regs: */ 971 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 972 973 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 974 975 /* 976 * Initialize the page-table base register to a global 977 * directory with all zeroes. This ensure that we can handle 978 * TLB-misses to user address-space even before we created the 979 * first user address-space. This may happen, e.g., due to 980 * aggressive use of lfetch.fault. 981 */ 982 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 983 984 /* 985 * Initialize default control register to defer speculative faults except 986 * for those arising from TLB misses, which are not deferred. The 987 * kernel MUST NOT depend on a particular setting of these bits (in other words, 988 * the kernel must have recovery code for all speculative accesses). Turn on 989 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 990 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 991 * be fine). 992 */ 993 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 994 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 995 atomic_inc(&init_mm.mm_count); 996 current->active_mm = &init_mm; 997 if (current->mm) 998 BUG(); 999 1000 ia64_mmu_init(ia64_imva(cpu_data)); 1001 ia64_mca_cpu_init(ia64_imva(cpu_data)); 1002 1003 #ifdef CONFIG_IA32_SUPPORT 1004 ia32_cpu_init(); 1005 #endif 1006 1007 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 1008 ia64_set_itc(0); 1009 1010 /* disable all local interrupt sources: */ 1011 ia64_set_itv(1 << 16); 1012 ia64_set_lrr0(1 << 16); 1013 ia64_set_lrr1(1 << 16); 1014 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 1015 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 1016 1017 /* clear TPR & XTP to enable all interrupt classes: */ 1018 ia64_setreg(_IA64_REG_CR_TPR, 0); 1019 1020 /* Clear any pending interrupts left by SAL/EFI */ 1021 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1022 ia64_eoi(); 1023 1024 #ifdef CONFIG_SMP 1025 normal_xtp(); 1026 #endif 1027 1028 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1029 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1030 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1031 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1032 } else { 1033 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1034 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1035 } 1036 while (max_ctx < ia64_ctx.max_ctx) { 1037 unsigned int old = ia64_ctx.max_ctx; 1038 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1039 break; 1040 } 1041 1042 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1043 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1044 "stacked regs\n"); 1045 num_phys_stacked = 96; 1046 } 1047 /* size of physical stacked register partition plus 8 bytes: */ 1048 if (num_phys_stacked > max_num_phys_stacked) { 1049 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1050 max_num_phys_stacked = num_phys_stacked; 1051 } 1052 platform_cpu_init(); 1053 pm_idle = default_idle; 1054 } 1055 1056 void __init 1057 check_bugs (void) 1058 { 1059 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1060 (unsigned long) __end___mckinley_e9_bundles); 1061 } 1062 1063 static int __init run_dmi_scan(void) 1064 { 1065 dmi_scan_machine(); 1066 return 0; 1067 } 1068 core_initcall(run_dmi_scan); 1069