1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Architecture-specific setup. 4 * 5 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * Stephane Eranian <eranian@hpl.hp.com> 8 * Copyright (C) 2000, 2004 Intel Corp 9 * Rohit Seth <rohit.seth@intel.com> 10 * Suresh Siddha <suresh.b.siddha@intel.com> 11 * Gordon Jin <gordon.jin@intel.com> 12 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * 15 * 12/26/04 S.Siddha, G.Jin, R.Seth 16 * Add multi-threading and multi-core detection 17 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 18 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 19 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 20 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 21 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 22 * 01/07/99 S.Eranian added the support for command line argument 23 * 06/24/99 W.Drummond added boot_cpu_data. 24 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 25 */ 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/cpu.h> 33 #include <linux/kernel.h> 34 #include <linux/memblock.h> 35 #include <linux/reboot.h> 36 #include <linux/sched/mm.h> 37 #include <linux/sched/clock.h> 38 #include <linux/sched/task_stack.h> 39 #include <linux/seq_file.h> 40 #include <linux/string.h> 41 #include <linux/threads.h> 42 #include <linux/screen_info.h> 43 #include <linux/dmi.h> 44 #include <linux/serial.h> 45 #include <linux/serial_core.h> 46 #include <linux/efi.h> 47 #include <linux/initrd.h> 48 #include <linux/pm.h> 49 #include <linux/cpufreq.h> 50 #include <linux/kexec.h> 51 #include <linux/crash_dump.h> 52 53 #include <asm/machvec.h> 54 #include <asm/mca.h> 55 #include <asm/meminit.h> 56 #include <asm/page.h> 57 #include <asm/patch.h> 58 #include <asm/pgtable.h> 59 #include <asm/processor.h> 60 #include <asm/sal.h> 61 #include <asm/sections.h> 62 #include <asm/setup.h> 63 #include <asm/smp.h> 64 #include <asm/tlbflush.h> 65 #include <asm/unistd.h> 66 67 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 68 # error "struct cpuinfo_ia64 too big!" 69 #endif 70 71 #ifdef CONFIG_SMP 72 unsigned long __per_cpu_offset[NR_CPUS]; 73 EXPORT_SYMBOL(__per_cpu_offset); 74 #endif 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); 77 EXPORT_SYMBOL(ia64_cpu_info); 78 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 79 #ifdef CONFIG_SMP 80 EXPORT_SYMBOL(local_per_cpu_offset); 81 #endif 82 unsigned long ia64_cycles_per_usec; 83 struct ia64_boot_param *ia64_boot_param; 84 struct screen_info screen_info; 85 unsigned long vga_console_iobase; 86 unsigned long vga_console_membase; 87 88 static struct resource data_resource = { 89 .name = "Kernel data", 90 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 91 }; 92 93 static struct resource code_resource = { 94 .name = "Kernel code", 95 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 96 }; 97 98 static struct resource bss_resource = { 99 .name = "Kernel bss", 100 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 101 }; 102 103 unsigned long ia64_max_cacheline_size; 104 105 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 106 EXPORT_SYMBOL(ia64_iobase); 107 struct io_space io_space[MAX_IO_SPACES]; 108 EXPORT_SYMBOL(io_space); 109 unsigned int num_io_spaces; 110 111 /* 112 * "flush_icache_range()" needs to know what processor dependent stride size to use 113 * when it makes i-cache(s) coherent with d-caches. 114 */ 115 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 116 unsigned long ia64_i_cache_stride_shift = ~0; 117 /* 118 * "clflush_cache_range()" needs to know what processor dependent stride size to 119 * use when it flushes cache lines including both d-cache and i-cache. 120 */ 121 /* Safest way to go: 32 bytes by 32 bytes */ 122 #define CACHE_STRIDE_SHIFT 5 123 unsigned long ia64_cache_stride_shift = ~0; 124 125 /* 126 * We use a special marker for the end of memory and it uses the extra (+1) slot 127 */ 128 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 129 int num_rsvd_regions __initdata; 130 131 132 /* 133 * Filter incoming memory segments based on the primitive map created from the boot 134 * parameters. Segments contained in the map are removed from the memory ranges. A 135 * caller-specified function is called with the memory ranges that remain after filtering. 136 * This routine does not assume the incoming segments are sorted. 137 */ 138 int __init 139 filter_rsvd_memory (u64 start, u64 end, void *arg) 140 { 141 u64 range_start, range_end, prev_start; 142 void (*func)(unsigned long, unsigned long, int); 143 int i; 144 145 #if IGNORE_PFN0 146 if (start == PAGE_OFFSET) { 147 printk(KERN_WARNING "warning: skipping physical page 0\n"); 148 start += PAGE_SIZE; 149 if (start >= end) return 0; 150 } 151 #endif 152 /* 153 * lowest possible address(walker uses virtual) 154 */ 155 prev_start = PAGE_OFFSET; 156 func = arg; 157 158 for (i = 0; i < num_rsvd_regions; ++i) { 159 range_start = max(start, prev_start); 160 range_end = min(end, rsvd_region[i].start); 161 162 if (range_start < range_end) 163 call_pernode_memory(__pa(range_start), range_end - range_start, func); 164 165 /* nothing more available in this segment */ 166 if (range_end == end) return 0; 167 168 prev_start = rsvd_region[i].end; 169 } 170 /* end of memory marker allows full processing inside loop body */ 171 return 0; 172 } 173 174 /* 175 * Similar to "filter_rsvd_memory()", but the reserved memory ranges 176 * are not filtered out. 177 */ 178 int __init 179 filter_memory(u64 start, u64 end, void *arg) 180 { 181 void (*func)(unsigned long, unsigned long, int); 182 183 #if IGNORE_PFN0 184 if (start == PAGE_OFFSET) { 185 printk(KERN_WARNING "warning: skipping physical page 0\n"); 186 start += PAGE_SIZE; 187 if (start >= end) 188 return 0; 189 } 190 #endif 191 func = arg; 192 if (start < end) 193 call_pernode_memory(__pa(start), end - start, func); 194 return 0; 195 } 196 197 static void __init 198 sort_regions (struct rsvd_region *rsvd_region, int max) 199 { 200 int j; 201 202 /* simple bubble sorting */ 203 while (max--) { 204 for (j = 0; j < max; ++j) { 205 if (rsvd_region[j].start > rsvd_region[j+1].start) { 206 struct rsvd_region tmp; 207 tmp = rsvd_region[j]; 208 rsvd_region[j] = rsvd_region[j + 1]; 209 rsvd_region[j + 1] = tmp; 210 } 211 } 212 } 213 } 214 215 /* merge overlaps */ 216 static int __init 217 merge_regions (struct rsvd_region *rsvd_region, int max) 218 { 219 int i; 220 for (i = 1; i < max; ++i) { 221 if (rsvd_region[i].start >= rsvd_region[i-1].end) 222 continue; 223 if (rsvd_region[i].end > rsvd_region[i-1].end) 224 rsvd_region[i-1].end = rsvd_region[i].end; 225 --max; 226 memmove(&rsvd_region[i], &rsvd_region[i+1], 227 (max - i) * sizeof(struct rsvd_region)); 228 } 229 return max; 230 } 231 232 /* 233 * Request address space for all standard resources 234 */ 235 static int __init register_memory(void) 236 { 237 code_resource.start = ia64_tpa(_text); 238 code_resource.end = ia64_tpa(_etext) - 1; 239 data_resource.start = ia64_tpa(_etext); 240 data_resource.end = ia64_tpa(_edata) - 1; 241 bss_resource.start = ia64_tpa(__bss_start); 242 bss_resource.end = ia64_tpa(_end) - 1; 243 efi_initialize_iomem_resources(&code_resource, &data_resource, 244 &bss_resource); 245 246 return 0; 247 } 248 249 __initcall(register_memory); 250 251 252 #ifdef CONFIG_KEXEC 253 254 /* 255 * This function checks if the reserved crashkernel is allowed on the specific 256 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require 257 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of 258 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that 259 * in kdump case. See the comment in sba_init() in sba_iommu.c. 260 * 261 * So, the only machvec that really supports loading the kdump kernel 262 * over 4 GB is "uv". 263 */ 264 static int __init check_crashkernel_memory(unsigned long pbase, size_t size) 265 { 266 if (ia64_platform_is("uv")) 267 return 1; 268 else 269 return pbase < (1UL << 32); 270 } 271 272 static void __init setup_crashkernel(unsigned long total, int *n) 273 { 274 unsigned long long base = 0, size = 0; 275 int ret; 276 277 ret = parse_crashkernel(boot_command_line, total, 278 &size, &base); 279 if (ret == 0 && size > 0) { 280 if (!base) { 281 sort_regions(rsvd_region, *n); 282 *n = merge_regions(rsvd_region, *n); 283 base = kdump_find_rsvd_region(size, 284 rsvd_region, *n); 285 } 286 287 if (!check_crashkernel_memory(base, size)) { 288 pr_warning("crashkernel: There would be kdump memory " 289 "at %ld GB but this is unusable because it " 290 "must\nbe below 4 GB. Change the memory " 291 "configuration of the machine.\n", 292 (unsigned long)(base >> 30)); 293 return; 294 } 295 296 if (base != ~0UL) { 297 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 298 "for crashkernel (System RAM: %ldMB)\n", 299 (unsigned long)(size >> 20), 300 (unsigned long)(base >> 20), 301 (unsigned long)(total >> 20)); 302 rsvd_region[*n].start = 303 (unsigned long)__va(base); 304 rsvd_region[*n].end = 305 (unsigned long)__va(base + size); 306 (*n)++; 307 crashk_res.start = base; 308 crashk_res.end = base + size - 1; 309 } 310 } 311 efi_memmap_res.start = ia64_boot_param->efi_memmap; 312 efi_memmap_res.end = efi_memmap_res.start + 313 ia64_boot_param->efi_memmap_size; 314 boot_param_res.start = __pa(ia64_boot_param); 315 boot_param_res.end = boot_param_res.start + 316 sizeof(*ia64_boot_param); 317 } 318 #else 319 static inline void __init setup_crashkernel(unsigned long total, int *n) 320 {} 321 #endif 322 323 /** 324 * reserve_memory - setup reserved memory areas 325 * 326 * Setup the reserved memory areas set aside for the boot parameters, 327 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 328 * see arch/ia64/include/asm/meminit.h if you need to define more. 329 */ 330 void __init 331 reserve_memory (void) 332 { 333 int n = 0; 334 unsigned long total_memory; 335 336 /* 337 * none of the entries in this table overlap 338 */ 339 rsvd_region[n].start = (unsigned long) ia64_boot_param; 340 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 341 n++; 342 343 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 344 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 345 n++; 346 347 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 348 rsvd_region[n].end = (rsvd_region[n].start 349 + strlen(__va(ia64_boot_param->command_line)) + 1); 350 n++; 351 352 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 353 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 354 n++; 355 356 #ifdef CONFIG_BLK_DEV_INITRD 357 if (ia64_boot_param->initrd_start) { 358 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 359 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 360 n++; 361 } 362 #endif 363 364 #ifdef CONFIG_CRASH_DUMP 365 if (reserve_elfcorehdr(&rsvd_region[n].start, 366 &rsvd_region[n].end) == 0) 367 n++; 368 #endif 369 370 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 371 n++; 372 373 setup_crashkernel(total_memory, &n); 374 375 /* end of memory marker */ 376 rsvd_region[n].start = ~0UL; 377 rsvd_region[n].end = ~0UL; 378 n++; 379 380 num_rsvd_regions = n; 381 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 382 383 sort_regions(rsvd_region, num_rsvd_regions); 384 num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions); 385 386 /* reserve all regions except the end of memory marker with memblock */ 387 for (n = 0; n < num_rsvd_regions - 1; n++) { 388 struct rsvd_region *region = &rsvd_region[n]; 389 phys_addr_t addr = __pa(region->start); 390 phys_addr_t size = region->end - region->start; 391 392 memblock_reserve(addr, size); 393 } 394 } 395 396 /** 397 * find_initrd - get initrd parameters from the boot parameter structure 398 * 399 * Grab the initrd start and end from the boot parameter struct given us by 400 * the boot loader. 401 */ 402 void __init 403 find_initrd (void) 404 { 405 #ifdef CONFIG_BLK_DEV_INITRD 406 if (ia64_boot_param->initrd_start) { 407 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 408 initrd_end = initrd_start+ia64_boot_param->initrd_size; 409 410 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n", 411 initrd_start, ia64_boot_param->initrd_size); 412 } 413 #endif 414 } 415 416 static void __init 417 io_port_init (void) 418 { 419 unsigned long phys_iobase; 420 421 /* 422 * Set `iobase' based on the EFI memory map or, failing that, the 423 * value firmware left in ar.k0. 424 * 425 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 426 * the port's virtual address, so ia32_load_state() loads it with a 427 * user virtual address. But in ia64 mode, glibc uses the 428 * *physical* address in ar.k0 to mmap the appropriate area from 429 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 430 * cases, user-mode can only use the legacy 0-64K I/O port space. 431 * 432 * ar.k0 is not involved in kernel I/O port accesses, which can use 433 * any of the I/O port spaces and are done via MMIO using the 434 * virtual mmio_base from the appropriate io_space[]. 435 */ 436 phys_iobase = efi_get_iobase(); 437 if (!phys_iobase) { 438 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 439 printk(KERN_INFO "No I/O port range found in EFI memory map, " 440 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 441 } 442 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 443 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 444 445 /* setup legacy IO port space */ 446 io_space[0].mmio_base = ia64_iobase; 447 io_space[0].sparse = 1; 448 num_io_spaces = 1; 449 } 450 451 /** 452 * early_console_setup - setup debugging console 453 * 454 * Consoles started here require little enough setup that we can start using 455 * them very early in the boot process, either right after the machine 456 * vector initialization, or even before if the drivers can detect their hw. 457 * 458 * Returns non-zero if a console couldn't be setup. 459 */ 460 static inline int __init 461 early_console_setup (char *cmdline) 462 { 463 #ifdef CONFIG_EFI_PCDP 464 if (!efi_setup_pcdp_console(cmdline)) 465 return 0; 466 #endif 467 return -1; 468 } 469 470 static inline void 471 mark_bsp_online (void) 472 { 473 #ifdef CONFIG_SMP 474 /* If we register an early console, allow CPU 0 to printk */ 475 set_cpu_online(smp_processor_id(), true); 476 #endif 477 } 478 479 static __initdata int nomca; 480 static __init int setup_nomca(char *s) 481 { 482 nomca = 1; 483 return 0; 484 } 485 early_param("nomca", setup_nomca); 486 487 #ifdef CONFIG_CRASH_DUMP 488 int __init reserve_elfcorehdr(u64 *start, u64 *end) 489 { 490 u64 length; 491 492 /* We get the address using the kernel command line, 493 * but the size is extracted from the EFI tables. 494 * Both address and size are required for reservation 495 * to work properly. 496 */ 497 498 if (!is_vmcore_usable()) 499 return -EINVAL; 500 501 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 502 vmcore_unusable(); 503 return -EINVAL; 504 } 505 506 *start = (unsigned long)__va(elfcorehdr_addr); 507 *end = *start + length; 508 return 0; 509 } 510 511 #endif /* CONFIG_PROC_VMCORE */ 512 513 void __init 514 setup_arch (char **cmdline_p) 515 { 516 unw_init(); 517 518 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 519 520 *cmdline_p = __va(ia64_boot_param->command_line); 521 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 522 523 efi_init(); 524 io_port_init(); 525 526 #ifdef CONFIG_IA64_GENERIC 527 /* machvec needs to be parsed from the command line 528 * before parse_early_param() is called to ensure 529 * that ia64_mv is initialised before any command line 530 * settings may cause console setup to occur 531 */ 532 machvec_init_from_cmdline(*cmdline_p); 533 #endif 534 535 parse_early_param(); 536 537 if (early_console_setup(*cmdline_p) == 0) 538 mark_bsp_online(); 539 540 /* Initialize the ACPI boot-time table parser */ 541 acpi_table_init(); 542 early_acpi_boot_init(); 543 #ifdef CONFIG_ACPI_NUMA 544 acpi_numa_init(); 545 acpi_numa_fixup(); 546 #ifdef CONFIG_ACPI_HOTPLUG_CPU 547 prefill_possible_map(); 548 #endif 549 per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ? 550 32 : cpumask_weight(&early_cpu_possible_map)), 551 additional_cpus > 0 ? additional_cpus : 0); 552 #endif /* CONFIG_ACPI_NUMA */ 553 554 #ifdef CONFIG_SMP 555 smp_build_cpu_map(); 556 #endif 557 find_memory(); 558 559 /* process SAL system table: */ 560 ia64_sal_init(__va(efi.sal_systab)); 561 562 #ifdef CONFIG_ITANIUM 563 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 564 #else 565 { 566 unsigned long num_phys_stacked; 567 568 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96) 569 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist); 570 } 571 #endif 572 573 #ifdef CONFIG_SMP 574 cpu_physical_id(0) = hard_smp_processor_id(); 575 #endif 576 577 cpu_init(); /* initialize the bootstrap CPU */ 578 mmu_context_init(); /* initialize context_id bitmap */ 579 580 #ifdef CONFIG_VT 581 if (!conswitchp) { 582 # if defined(CONFIG_DUMMY_CONSOLE) 583 conswitchp = &dummy_con; 584 # endif 585 # if defined(CONFIG_VGA_CONSOLE) 586 /* 587 * Non-legacy systems may route legacy VGA MMIO range to system 588 * memory. vga_con probes the MMIO hole, so memory looks like 589 * a VGA device to it. The EFI memory map can tell us if it's 590 * memory so we can avoid this problem. 591 */ 592 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 593 conswitchp = &vga_con; 594 # endif 595 } 596 #endif 597 598 /* enable IA-64 Machine Check Abort Handling unless disabled */ 599 if (!nomca) 600 ia64_mca_init(); 601 602 platform_setup(cmdline_p); 603 paging_init(); 604 605 clear_sched_clock_stable(); 606 } 607 608 /* 609 * Display cpu info for all CPUs. 610 */ 611 static int 612 show_cpuinfo (struct seq_file *m, void *v) 613 { 614 #ifdef CONFIG_SMP 615 # define lpj c->loops_per_jiffy 616 # define cpunum c->cpu 617 #else 618 # define lpj loops_per_jiffy 619 # define cpunum 0 620 #endif 621 static struct { 622 unsigned long mask; 623 const char *feature_name; 624 } feature_bits[] = { 625 { 1UL << 0, "branchlong" }, 626 { 1UL << 1, "spontaneous deferral"}, 627 { 1UL << 2, "16-byte atomic ops" } 628 }; 629 char features[128], *cp, *sep; 630 struct cpuinfo_ia64 *c = v; 631 unsigned long mask; 632 unsigned long proc_freq; 633 int i, size; 634 635 mask = c->features; 636 637 /* build the feature string: */ 638 memcpy(features, "standard", 9); 639 cp = features; 640 size = sizeof(features); 641 sep = ""; 642 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 643 if (mask & feature_bits[i].mask) { 644 cp += snprintf(cp, size, "%s%s", sep, 645 feature_bits[i].feature_name), 646 sep = ", "; 647 mask &= ~feature_bits[i].mask; 648 size = sizeof(features) - (cp - features); 649 } 650 } 651 if (mask && size > 1) { 652 /* print unknown features as a hex value */ 653 snprintf(cp, size, "%s0x%lx", sep, mask); 654 } 655 656 proc_freq = cpufreq_quick_get(cpunum); 657 if (!proc_freq) 658 proc_freq = c->proc_freq / 1000; 659 660 seq_printf(m, 661 "processor : %d\n" 662 "vendor : %s\n" 663 "arch : IA-64\n" 664 "family : %u\n" 665 "model : %u\n" 666 "model name : %s\n" 667 "revision : %u\n" 668 "archrev : %u\n" 669 "features : %s\n" 670 "cpu number : %lu\n" 671 "cpu regs : %u\n" 672 "cpu MHz : %lu.%03lu\n" 673 "itc MHz : %lu.%06lu\n" 674 "BogoMIPS : %lu.%02lu\n", 675 cpunum, c->vendor, c->family, c->model, 676 c->model_name, c->revision, c->archrev, 677 features, c->ppn, c->number, 678 proc_freq / 1000, proc_freq % 1000, 679 c->itc_freq / 1000000, c->itc_freq % 1000000, 680 lpj*HZ/500000, (lpj*HZ/5000) % 100); 681 #ifdef CONFIG_SMP 682 seq_printf(m, "siblings : %u\n", 683 cpumask_weight(&cpu_core_map[cpunum])); 684 if (c->socket_id != -1) 685 seq_printf(m, "physical id: %u\n", c->socket_id); 686 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 687 seq_printf(m, 688 "core id : %u\n" 689 "thread id : %u\n", 690 c->core_id, c->thread_id); 691 #endif 692 seq_printf(m,"\n"); 693 694 return 0; 695 } 696 697 static void * 698 c_start (struct seq_file *m, loff_t *pos) 699 { 700 #ifdef CONFIG_SMP 701 while (*pos < nr_cpu_ids && !cpu_online(*pos)) 702 ++*pos; 703 #endif 704 return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL; 705 } 706 707 static void * 708 c_next (struct seq_file *m, void *v, loff_t *pos) 709 { 710 ++*pos; 711 return c_start(m, pos); 712 } 713 714 static void 715 c_stop (struct seq_file *m, void *v) 716 { 717 } 718 719 const struct seq_operations cpuinfo_op = { 720 .start = c_start, 721 .next = c_next, 722 .stop = c_stop, 723 .show = show_cpuinfo 724 }; 725 726 #define MAX_BRANDS 8 727 static char brandname[MAX_BRANDS][128]; 728 729 static char * 730 get_model_name(__u8 family, __u8 model) 731 { 732 static int overflow; 733 char brand[128]; 734 int i; 735 736 memcpy(brand, "Unknown", 8); 737 if (ia64_pal_get_brand_info(brand)) { 738 if (family == 0x7) 739 memcpy(brand, "Merced", 7); 740 else if (family == 0x1f) switch (model) { 741 case 0: memcpy(brand, "McKinley", 9); break; 742 case 1: memcpy(brand, "Madison", 8); break; 743 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 744 } 745 } 746 for (i = 0; i < MAX_BRANDS; i++) 747 if (strcmp(brandname[i], brand) == 0) 748 return brandname[i]; 749 for (i = 0; i < MAX_BRANDS; i++) 750 if (brandname[i][0] == '\0') 751 return strcpy(brandname[i], brand); 752 if (overflow++ == 0) 753 printk(KERN_ERR 754 "%s: Table overflow. Some processor model information will be missing\n", 755 __func__); 756 return "Unknown"; 757 } 758 759 static void 760 identify_cpu (struct cpuinfo_ia64 *c) 761 { 762 union { 763 unsigned long bits[5]; 764 struct { 765 /* id 0 & 1: */ 766 char vendor[16]; 767 768 /* id 2 */ 769 u64 ppn; /* processor serial number */ 770 771 /* id 3: */ 772 unsigned number : 8; 773 unsigned revision : 8; 774 unsigned model : 8; 775 unsigned family : 8; 776 unsigned archrev : 8; 777 unsigned reserved : 24; 778 779 /* id 4: */ 780 u64 features; 781 } field; 782 } cpuid; 783 pal_vm_info_1_u_t vm1; 784 pal_vm_info_2_u_t vm2; 785 pal_status_t status; 786 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 787 int i; 788 for (i = 0; i < 5; ++i) 789 cpuid.bits[i] = ia64_get_cpuid(i); 790 791 memcpy(c->vendor, cpuid.field.vendor, 16); 792 #ifdef CONFIG_SMP 793 c->cpu = smp_processor_id(); 794 795 /* below default values will be overwritten by identify_siblings() 796 * for Multi-Threading/Multi-Core capable CPUs 797 */ 798 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 799 c->socket_id = -1; 800 801 identify_siblings(c); 802 803 if (c->threads_per_core > smp_num_siblings) 804 smp_num_siblings = c->threads_per_core; 805 #endif 806 c->ppn = cpuid.field.ppn; 807 c->number = cpuid.field.number; 808 c->revision = cpuid.field.revision; 809 c->model = cpuid.field.model; 810 c->family = cpuid.field.family; 811 c->archrev = cpuid.field.archrev; 812 c->features = cpuid.field.features; 813 c->model_name = get_model_name(c->family, c->model); 814 815 status = ia64_pal_vm_summary(&vm1, &vm2); 816 if (status == PAL_STATUS_SUCCESS) { 817 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 818 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 819 } 820 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 821 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 822 } 823 824 /* 825 * Do the following calculations: 826 * 827 * 1. the max. cache line size. 828 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()". 829 * 3. the minimum of the cache stride sizes for "clflush_cache_range()". 830 */ 831 static void 832 get_cache_info(void) 833 { 834 unsigned long line_size, max = 1; 835 unsigned long l, levels, unique_caches; 836 pal_cache_config_info_t cci; 837 long status; 838 839 status = ia64_pal_cache_summary(&levels, &unique_caches); 840 if (status != 0) { 841 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 842 __func__, status); 843 max = SMP_CACHE_BYTES; 844 /* Safest setup for "flush_icache_range()" */ 845 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 846 /* Safest setup for "clflush_cache_range()" */ 847 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 848 goto out; 849 } 850 851 for (l = 0; l < levels; ++l) { 852 /* cache_type (data_or_unified)=2 */ 853 status = ia64_pal_cache_config_info(l, 2, &cci); 854 if (status != 0) { 855 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 856 "(l=%lu, 2) failed (status=%ld)\n", 857 __func__, l, status); 858 max = SMP_CACHE_BYTES; 859 /* The safest setup for "flush_icache_range()" */ 860 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 861 /* The safest setup for "clflush_cache_range()" */ 862 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT; 863 cci.pcci_unified = 1; 864 } else { 865 if (cci.pcci_stride < ia64_cache_stride_shift) 866 ia64_cache_stride_shift = cci.pcci_stride; 867 868 line_size = 1 << cci.pcci_line_size; 869 if (line_size > max) 870 max = line_size; 871 } 872 873 if (!cci.pcci_unified) { 874 /* cache_type (instruction)=1*/ 875 status = ia64_pal_cache_config_info(l, 1, &cci); 876 if (status != 0) { 877 printk(KERN_ERR "%s: ia64_pal_cache_config_info" 878 "(l=%lu, 1) failed (status=%ld)\n", 879 __func__, l, status); 880 /* The safest setup for flush_icache_range() */ 881 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 882 } 883 } 884 if (cci.pcci_stride < ia64_i_cache_stride_shift) 885 ia64_i_cache_stride_shift = cci.pcci_stride; 886 } 887 out: 888 if (max > ia64_max_cacheline_size) 889 ia64_max_cacheline_size = max; 890 } 891 892 /* 893 * cpu_init() initializes state that is per-CPU. This function acts 894 * as a 'CPU state barrier', nothing should get across. 895 */ 896 void 897 cpu_init (void) 898 { 899 extern void ia64_mmu_init(void *); 900 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 901 unsigned long num_phys_stacked; 902 pal_vm_info_2_u_t vmi; 903 unsigned int max_ctx; 904 struct cpuinfo_ia64 *cpu_info; 905 void *cpu_data; 906 907 cpu_data = per_cpu_init(); 908 #ifdef CONFIG_SMP 909 /* 910 * insert boot cpu into sibling and core mapes 911 * (must be done after per_cpu area is setup) 912 */ 913 if (smp_processor_id() == 0) { 914 cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0)); 915 cpumask_set_cpu(0, &cpu_core_map[0]); 916 } else { 917 /* 918 * Set ar.k3 so that assembly code in MCA handler can compute 919 * physical addresses of per cpu variables with a simple: 920 * phys = ar.k3 + &per_cpu_var 921 * and the alt-dtlb-miss handler can set per-cpu mapping into 922 * the TLB when needed. head.S already did this for cpu0. 923 */ 924 ia64_set_kr(IA64_KR_PER_CPU_DATA, 925 ia64_tpa(cpu_data) - (long) __per_cpu_start); 926 } 927 #endif 928 929 get_cache_info(); 930 931 /* 932 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 933 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 934 * depends on the data returned by identify_cpu(). We break the dependency by 935 * accessing cpu_data() through the canonical per-CPU address. 936 */ 937 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start); 938 identify_cpu(cpu_info); 939 940 #ifdef CONFIG_MCKINLEY 941 { 942 # define FEATURE_SET 16 943 struct ia64_pal_retval iprv; 944 945 if (cpu_info->family == 0x1f) { 946 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 947 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 948 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 949 (iprv.v1 | 0x80), FEATURE_SET, 0); 950 } 951 } 952 #endif 953 954 /* Clear the stack memory reserved for pt_regs: */ 955 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 956 957 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 958 959 /* 960 * Initialize the page-table base register to a global 961 * directory with all zeroes. This ensure that we can handle 962 * TLB-misses to user address-space even before we created the 963 * first user address-space. This may happen, e.g., due to 964 * aggressive use of lfetch.fault. 965 */ 966 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 967 968 /* 969 * Initialize default control register to defer speculative faults except 970 * for those arising from TLB misses, which are not deferred. The 971 * kernel MUST NOT depend on a particular setting of these bits (in other words, 972 * the kernel must have recovery code for all speculative accesses). Turn on 973 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 974 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 975 * be fine). 976 */ 977 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 978 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 979 mmgrab(&init_mm); 980 current->active_mm = &init_mm; 981 BUG_ON(current->mm); 982 983 ia64_mmu_init(ia64_imva(cpu_data)); 984 ia64_mca_cpu_init(ia64_imva(cpu_data)); 985 986 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 987 ia64_set_itc(0); 988 989 /* disable all local interrupt sources: */ 990 ia64_set_itv(1 << 16); 991 ia64_set_lrr0(1 << 16); 992 ia64_set_lrr1(1 << 16); 993 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 994 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 995 996 /* clear TPR & XTP to enable all interrupt classes: */ 997 ia64_setreg(_IA64_REG_CR_TPR, 0); 998 999 /* Clear any pending interrupts left by SAL/EFI */ 1000 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 1001 ia64_eoi(); 1002 1003 #ifdef CONFIG_SMP 1004 normal_xtp(); 1005 #endif 1006 1007 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 1008 if (ia64_pal_vm_summary(NULL, &vmi) == 0) { 1009 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 1010 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL); 1011 } else { 1012 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 1013 max_ctx = (1U << 15) - 1; /* use architected minimum */ 1014 } 1015 while (max_ctx < ia64_ctx.max_ctx) { 1016 unsigned int old = ia64_ctx.max_ctx; 1017 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 1018 break; 1019 } 1020 1021 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 1022 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 1023 "stacked regs\n"); 1024 num_phys_stacked = 96; 1025 } 1026 /* size of physical stacked register partition plus 8 bytes: */ 1027 if (num_phys_stacked > max_num_phys_stacked) { 1028 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 1029 max_num_phys_stacked = num_phys_stacked; 1030 } 1031 } 1032 1033 void __init 1034 check_bugs (void) 1035 { 1036 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 1037 (unsigned long) __end___mckinley_e9_bundles); 1038 } 1039 1040 static int __init run_dmi_scan(void) 1041 { 1042 dmi_setup(); 1043 return 0; 1044 } 1045 core_initcall(run_dmi_scan); 1046