1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/config.h> 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/bootmem.h> 31 #include <linux/console.h> 32 #include <linux/delay.h> 33 #include <linux/kernel.h> 34 #include <linux/reboot.h> 35 #include <linux/sched.h> 36 #include <linux/seq_file.h> 37 #include <linux/string.h> 38 #include <linux/threads.h> 39 #include <linux/tty.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/platform.h> 45 #include <linux/pm.h> 46 #include <linux/cpufreq.h> 47 48 #include <asm/ia32.h> 49 #include <asm/machvec.h> 50 #include <asm/mca.h> 51 #include <asm/meminit.h> 52 #include <asm/page.h> 53 #include <asm/patch.h> 54 #include <asm/pgtable.h> 55 #include <asm/processor.h> 56 #include <asm/sal.h> 57 #include <asm/sections.h> 58 #include <asm/serial.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/system.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 extern void ia64_setup_printk_clock(void); 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 79 unsigned long ia64_cycles_per_usec; 80 struct ia64_boot_param *ia64_boot_param; 81 struct screen_info screen_info; 82 unsigned long vga_console_iobase; 83 unsigned long vga_console_membase; 84 85 static struct resource data_resource = { 86 .name = "Kernel data", 87 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 88 }; 89 90 static struct resource code_resource = { 91 .name = "Kernel code", 92 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 93 }; 94 extern void efi_initialize_iomem_resources(struct resource *, 95 struct resource *); 96 extern char _text[], _end[], _etext[]; 97 98 unsigned long ia64_max_cacheline_size; 99 100 int dma_get_cache_alignment(void) 101 { 102 return ia64_max_cacheline_size; 103 } 104 EXPORT_SYMBOL(dma_get_cache_alignment); 105 106 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 107 EXPORT_SYMBOL(ia64_iobase); 108 struct io_space io_space[MAX_IO_SPACES]; 109 EXPORT_SYMBOL(io_space); 110 unsigned int num_io_spaces; 111 112 /* 113 * "flush_icache_range()" needs to know what processor dependent stride size to use 114 * when it makes i-cache(s) coherent with d-caches. 115 */ 116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117 unsigned long ia64_i_cache_stride_shift = ~0; 118 119 /* 120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 123 * address of the second buffer must be aligned to (merge_mask+1) in order to be 124 * mergeable). By default, we assume there is no I/O MMU which can merge physically 125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 126 * page-size of 2^64. 127 */ 128 unsigned long ia64_max_iommu_merge_mask = ~0UL; 129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 130 131 /* 132 * We use a special marker for the end of memory and it uses the extra (+1) slot 133 */ 134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1]; 135 int num_rsvd_regions; 136 137 138 /* 139 * Filter incoming memory segments based on the primitive map created from the boot 140 * parameters. Segments contained in the map are removed from the memory ranges. A 141 * caller-specified function is called with the memory ranges that remain after filtering. 142 * This routine does not assume the incoming segments are sorted. 143 */ 144 int 145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 146 { 147 unsigned long range_start, range_end, prev_start; 148 void (*func)(unsigned long, unsigned long, int); 149 int i; 150 151 #if IGNORE_PFN0 152 if (start == PAGE_OFFSET) { 153 printk(KERN_WARNING "warning: skipping physical page 0\n"); 154 start += PAGE_SIZE; 155 if (start >= end) return 0; 156 } 157 #endif 158 /* 159 * lowest possible address(walker uses virtual) 160 */ 161 prev_start = PAGE_OFFSET; 162 func = arg; 163 164 for (i = 0; i < num_rsvd_regions; ++i) { 165 range_start = max(start, prev_start); 166 range_end = min(end, rsvd_region[i].start); 167 168 if (range_start < range_end) 169 call_pernode_memory(__pa(range_start), range_end - range_start, func); 170 171 /* nothing more available in this segment */ 172 if (range_end == end) return 0; 173 174 prev_start = rsvd_region[i].end; 175 } 176 /* end of memory marker allows full processing inside loop body */ 177 return 0; 178 } 179 180 static void 181 sort_regions (struct rsvd_region *rsvd_region, int max) 182 { 183 int j; 184 185 /* simple bubble sorting */ 186 while (max--) { 187 for (j = 0; j < max; ++j) { 188 if (rsvd_region[j].start > rsvd_region[j+1].start) { 189 struct rsvd_region tmp; 190 tmp = rsvd_region[j]; 191 rsvd_region[j] = rsvd_region[j + 1]; 192 rsvd_region[j + 1] = tmp; 193 } 194 } 195 } 196 } 197 198 /* 199 * Request address space for all standard resources 200 */ 201 static int __init register_memory(void) 202 { 203 code_resource.start = ia64_tpa(_text); 204 code_resource.end = ia64_tpa(_etext) - 1; 205 data_resource.start = ia64_tpa(_etext); 206 data_resource.end = ia64_tpa(_end) - 1; 207 efi_initialize_iomem_resources(&code_resource, &data_resource); 208 209 return 0; 210 } 211 212 __initcall(register_memory); 213 214 /** 215 * reserve_memory - setup reserved memory areas 216 * 217 * Setup the reserved memory areas set aside for the boot parameters, 218 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 219 * see include/asm-ia64/meminit.h if you need to define more. 220 */ 221 void 222 reserve_memory (void) 223 { 224 int n = 0; 225 226 /* 227 * none of the entries in this table overlap 228 */ 229 rsvd_region[n].start = (unsigned long) ia64_boot_param; 230 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 231 n++; 232 233 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 234 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 235 n++; 236 237 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 238 rsvd_region[n].end = (rsvd_region[n].start 239 + strlen(__va(ia64_boot_param->command_line)) + 1); 240 n++; 241 242 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 243 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 244 n++; 245 246 #ifdef CONFIG_BLK_DEV_INITRD 247 if (ia64_boot_param->initrd_start) { 248 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 249 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 250 n++; 251 } 252 #endif 253 254 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 255 n++; 256 257 /* end of memory marker */ 258 rsvd_region[n].start = ~0UL; 259 rsvd_region[n].end = ~0UL; 260 n++; 261 262 num_rsvd_regions = n; 263 264 sort_regions(rsvd_region, num_rsvd_regions); 265 } 266 267 /** 268 * find_initrd - get initrd parameters from the boot parameter structure 269 * 270 * Grab the initrd start and end from the boot parameter struct given us by 271 * the boot loader. 272 */ 273 void 274 find_initrd (void) 275 { 276 #ifdef CONFIG_BLK_DEV_INITRD 277 if (ia64_boot_param->initrd_start) { 278 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 279 initrd_end = initrd_start+ia64_boot_param->initrd_size; 280 281 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 282 initrd_start, ia64_boot_param->initrd_size); 283 } 284 #endif 285 } 286 287 static void __init 288 io_port_init (void) 289 { 290 unsigned long phys_iobase; 291 292 /* 293 * Set `iobase' based on the EFI memory map or, failing that, the 294 * value firmware left in ar.k0. 295 * 296 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 297 * the port's virtual address, so ia32_load_state() loads it with a 298 * user virtual address. But in ia64 mode, glibc uses the 299 * *physical* address in ar.k0 to mmap the appropriate area from 300 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 301 * cases, user-mode can only use the legacy 0-64K I/O port space. 302 * 303 * ar.k0 is not involved in kernel I/O port accesses, which can use 304 * any of the I/O port spaces and are done via MMIO using the 305 * virtual mmio_base from the appropriate io_space[]. 306 */ 307 phys_iobase = efi_get_iobase(); 308 if (!phys_iobase) { 309 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 310 printk(KERN_INFO "No I/O port range found in EFI memory map, " 311 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 312 } 313 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 314 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 315 316 /* setup legacy IO port space */ 317 io_space[0].mmio_base = ia64_iobase; 318 io_space[0].sparse = 1; 319 num_io_spaces = 1; 320 } 321 322 /** 323 * early_console_setup - setup debugging console 324 * 325 * Consoles started here require little enough setup that we can start using 326 * them very early in the boot process, either right after the machine 327 * vector initialization, or even before if the drivers can detect their hw. 328 * 329 * Returns non-zero if a console couldn't be setup. 330 */ 331 static inline int __init 332 early_console_setup (char *cmdline) 333 { 334 int earlycons = 0; 335 336 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 337 { 338 extern int sn_serial_console_early_setup(void); 339 if (!sn_serial_console_early_setup()) 340 earlycons++; 341 } 342 #endif 343 #ifdef CONFIG_EFI_PCDP 344 if (!efi_setup_pcdp_console(cmdline)) 345 earlycons++; 346 #endif 347 #ifdef CONFIG_SERIAL_8250_CONSOLE 348 if (!early_serial_console_init(cmdline)) 349 earlycons++; 350 #endif 351 352 return (earlycons) ? 0 : -1; 353 } 354 355 static inline void 356 mark_bsp_online (void) 357 { 358 #ifdef CONFIG_SMP 359 /* If we register an early console, allow CPU 0 to printk */ 360 cpu_set(smp_processor_id(), cpu_online_map); 361 #endif 362 } 363 364 #ifdef CONFIG_SMP 365 static void __init 366 check_for_logical_procs (void) 367 { 368 pal_logical_to_physical_t info; 369 s64 status; 370 371 status = ia64_pal_logical_to_phys(0, &info); 372 if (status == -1) { 373 printk(KERN_INFO "No logical to physical processor mapping " 374 "available\n"); 375 return; 376 } 377 if (status) { 378 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 379 status); 380 return; 381 } 382 /* 383 * Total number of siblings that BSP has. Though not all of them 384 * may have booted successfully. The correct number of siblings 385 * booted is in info.overview_num_log. 386 */ 387 smp_num_siblings = info.overview_tpc; 388 smp_num_cpucores = info.overview_cpp; 389 } 390 #endif 391 392 void __init 393 setup_arch (char **cmdline_p) 394 { 395 unw_init(); 396 397 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 398 399 *cmdline_p = __va(ia64_boot_param->command_line); 400 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 401 402 efi_init(); 403 io_port_init(); 404 405 #ifdef CONFIG_IA64_GENERIC 406 { 407 const char *mvec_name = strstr (*cmdline_p, "machvec="); 408 char str[64]; 409 410 if (mvec_name) { 411 const char *end; 412 size_t len; 413 414 mvec_name += 8; 415 end = strchr (mvec_name, ' '); 416 if (end) 417 len = end - mvec_name; 418 else 419 len = strlen (mvec_name); 420 len = min(len, sizeof (str) - 1); 421 strncpy (str, mvec_name, len); 422 str[len] = '\0'; 423 mvec_name = str; 424 } else 425 mvec_name = acpi_get_sysname(); 426 machvec_init(mvec_name); 427 } 428 #endif 429 430 if (early_console_setup(*cmdline_p) == 0) 431 mark_bsp_online(); 432 433 parse_early_param(); 434 #ifdef CONFIG_ACPI 435 /* Initialize the ACPI boot-time table parser */ 436 acpi_table_init(); 437 # ifdef CONFIG_ACPI_NUMA 438 acpi_numa_init(); 439 # endif 440 #else 441 # ifdef CONFIG_SMP 442 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 443 # endif 444 #endif /* CONFIG_APCI_BOOT */ 445 446 find_memory(); 447 448 /* process SAL system table: */ 449 ia64_sal_init(efi.sal_systab); 450 451 ia64_setup_printk_clock(); 452 453 #ifdef CONFIG_SMP 454 cpu_physical_id(0) = hard_smp_processor_id(); 455 456 cpu_set(0, cpu_sibling_map[0]); 457 cpu_set(0, cpu_core_map[0]); 458 459 check_for_logical_procs(); 460 if (smp_num_cpucores > 1) 461 printk(KERN_INFO 462 "cpu package is Multi-Core capable: number of cores=%d\n", 463 smp_num_cpucores); 464 if (smp_num_siblings > 1) 465 printk(KERN_INFO 466 "cpu package is Multi-Threading capable: number of siblings=%d\n", 467 smp_num_siblings); 468 #endif 469 470 cpu_init(); /* initialize the bootstrap CPU */ 471 mmu_context_init(); /* initialize context_id bitmap */ 472 473 #ifdef CONFIG_ACPI 474 acpi_boot_init(); 475 #endif 476 477 #ifdef CONFIG_VT 478 if (!conswitchp) { 479 # if defined(CONFIG_DUMMY_CONSOLE) 480 conswitchp = &dummy_con; 481 # endif 482 # if defined(CONFIG_VGA_CONSOLE) 483 /* 484 * Non-legacy systems may route legacy VGA MMIO range to system 485 * memory. vga_con probes the MMIO hole, so memory looks like 486 * a VGA device to it. The EFI memory map can tell us if it's 487 * memory so we can avoid this problem. 488 */ 489 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 490 conswitchp = &vga_con; 491 # endif 492 } 493 #endif 494 495 /* enable IA-64 Machine Check Abort Handling unless disabled */ 496 if (!strstr(saved_command_line, "nomca")) 497 ia64_mca_init(); 498 499 platform_setup(cmdline_p); 500 paging_init(); 501 } 502 503 /* 504 * Display cpu info for all cpu's. 505 */ 506 static int 507 show_cpuinfo (struct seq_file *m, void *v) 508 { 509 #ifdef CONFIG_SMP 510 # define lpj c->loops_per_jiffy 511 # define cpunum c->cpu 512 #else 513 # define lpj loops_per_jiffy 514 # define cpunum 0 515 #endif 516 static struct { 517 unsigned long mask; 518 const char *feature_name; 519 } feature_bits[] = { 520 { 1UL << 0, "branchlong" }, 521 { 1UL << 1, "spontaneous deferral"}, 522 { 1UL << 2, "16-byte atomic ops" } 523 }; 524 char family[32], features[128], *cp, sep; 525 struct cpuinfo_ia64 *c = v; 526 unsigned long mask; 527 unsigned long proc_freq; 528 int i; 529 530 mask = c->features; 531 532 switch (c->family) { 533 case 0x07: memcpy(family, "Itanium", 8); break; 534 case 0x1f: memcpy(family, "Itanium 2", 10); break; 535 default: sprintf(family, "%u", c->family); break; 536 } 537 538 /* build the feature string: */ 539 memcpy(features, " standard", 10); 540 cp = features; 541 sep = 0; 542 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 543 if (mask & feature_bits[i].mask) { 544 if (sep) 545 *cp++ = sep; 546 sep = ','; 547 *cp++ = ' '; 548 strcpy(cp, feature_bits[i].feature_name); 549 cp += strlen(feature_bits[i].feature_name); 550 mask &= ~feature_bits[i].mask; 551 } 552 } 553 if (mask) { 554 /* print unknown features as a hex value: */ 555 if (sep) 556 *cp++ = sep; 557 sprintf(cp, " 0x%lx", mask); 558 } 559 560 proc_freq = cpufreq_quick_get(cpunum); 561 if (!proc_freq) 562 proc_freq = c->proc_freq / 1000; 563 564 seq_printf(m, 565 "processor : %d\n" 566 "vendor : %s\n" 567 "arch : IA-64\n" 568 "family : %s\n" 569 "model : %u\n" 570 "revision : %u\n" 571 "archrev : %u\n" 572 "features :%s\n" /* don't change this---it _is_ right! */ 573 "cpu number : %lu\n" 574 "cpu regs : %u\n" 575 "cpu MHz : %lu.%06lu\n" 576 "itc MHz : %lu.%06lu\n" 577 "BogoMIPS : %lu.%02lu\n", 578 cpunum, c->vendor, family, c->model, c->revision, c->archrev, 579 features, c->ppn, c->number, 580 proc_freq / 1000, proc_freq % 1000, 581 c->itc_freq / 1000000, c->itc_freq % 1000000, 582 lpj*HZ/500000, (lpj*HZ/5000) % 100); 583 #ifdef CONFIG_SMP 584 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 585 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 586 seq_printf(m, 587 "physical id: %u\n" 588 "core id : %u\n" 589 "thread id : %u\n", 590 c->socket_id, c->core_id, c->thread_id); 591 #endif 592 seq_printf(m,"\n"); 593 594 return 0; 595 } 596 597 static void * 598 c_start (struct seq_file *m, loff_t *pos) 599 { 600 #ifdef CONFIG_SMP 601 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 602 ++*pos; 603 #endif 604 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 605 } 606 607 static void * 608 c_next (struct seq_file *m, void *v, loff_t *pos) 609 { 610 ++*pos; 611 return c_start(m, pos); 612 } 613 614 static void 615 c_stop (struct seq_file *m, void *v) 616 { 617 } 618 619 struct seq_operations cpuinfo_op = { 620 .start = c_start, 621 .next = c_next, 622 .stop = c_stop, 623 .show = show_cpuinfo 624 }; 625 626 static void __cpuinit 627 identify_cpu (struct cpuinfo_ia64 *c) 628 { 629 union { 630 unsigned long bits[5]; 631 struct { 632 /* id 0 & 1: */ 633 char vendor[16]; 634 635 /* id 2 */ 636 u64 ppn; /* processor serial number */ 637 638 /* id 3: */ 639 unsigned number : 8; 640 unsigned revision : 8; 641 unsigned model : 8; 642 unsigned family : 8; 643 unsigned archrev : 8; 644 unsigned reserved : 24; 645 646 /* id 4: */ 647 u64 features; 648 } field; 649 } cpuid; 650 pal_vm_info_1_u_t vm1; 651 pal_vm_info_2_u_t vm2; 652 pal_status_t status; 653 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 654 int i; 655 656 for (i = 0; i < 5; ++i) 657 cpuid.bits[i] = ia64_get_cpuid(i); 658 659 memcpy(c->vendor, cpuid.field.vendor, 16); 660 #ifdef CONFIG_SMP 661 c->cpu = smp_processor_id(); 662 663 /* below default values will be overwritten by identify_siblings() 664 * for Multi-Threading/Multi-Core capable cpu's 665 */ 666 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 667 c->socket_id = -1; 668 669 identify_siblings(c); 670 #endif 671 c->ppn = cpuid.field.ppn; 672 c->number = cpuid.field.number; 673 c->revision = cpuid.field.revision; 674 c->model = cpuid.field.model; 675 c->family = cpuid.field.family; 676 c->archrev = cpuid.field.archrev; 677 c->features = cpuid.field.features; 678 679 status = ia64_pal_vm_summary(&vm1, &vm2); 680 if (status == PAL_STATUS_SUCCESS) { 681 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 682 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 683 } 684 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 685 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 686 } 687 688 void 689 setup_per_cpu_areas (void) 690 { 691 /* start_kernel() requires this... */ 692 #ifdef CONFIG_ACPI_HOTPLUG_CPU 693 prefill_possible_map(); 694 #endif 695 } 696 697 /* 698 * Calculate the max. cache line size. 699 * 700 * In addition, the minimum of the i-cache stride sizes is calculated for 701 * "flush_icache_range()". 702 */ 703 static void __cpuinit 704 get_max_cacheline_size (void) 705 { 706 unsigned long line_size, max = 1; 707 unsigned int cache_size = 0; 708 u64 l, levels, unique_caches; 709 pal_cache_config_info_t cci; 710 s64 status; 711 712 status = ia64_pal_cache_summary(&levels, &unique_caches); 713 if (status != 0) { 714 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 715 __FUNCTION__, status); 716 max = SMP_CACHE_BYTES; 717 /* Safest setup for "flush_icache_range()" */ 718 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 719 goto out; 720 } 721 722 for (l = 0; l < levels; ++l) { 723 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 724 &cci); 725 if (status != 0) { 726 printk(KERN_ERR 727 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 728 __FUNCTION__, l, status); 729 max = SMP_CACHE_BYTES; 730 /* The safest setup for "flush_icache_range()" */ 731 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 732 cci.pcci_unified = 1; 733 } 734 line_size = 1 << cci.pcci_line_size; 735 if (line_size > max) 736 max = line_size; 737 if (cache_size < cci.pcci_cache_size) 738 cache_size = cci.pcci_cache_size; 739 if (!cci.pcci_unified) { 740 status = ia64_pal_cache_config_info(l, 741 /* cache_type (instruction)= */ 1, 742 &cci); 743 if (status != 0) { 744 printk(KERN_ERR 745 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 746 __FUNCTION__, l, status); 747 /* The safest setup for "flush_icache_range()" */ 748 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 749 } 750 } 751 if (cci.pcci_stride < ia64_i_cache_stride_shift) 752 ia64_i_cache_stride_shift = cci.pcci_stride; 753 } 754 out: 755 #ifdef CONFIG_SMP 756 max_cache_size = max(max_cache_size, cache_size); 757 #endif 758 if (max > ia64_max_cacheline_size) 759 ia64_max_cacheline_size = max; 760 } 761 762 /* 763 * cpu_init() initializes state that is per-CPU. This function acts 764 * as a 'CPU state barrier', nothing should get across. 765 */ 766 void __cpuinit 767 cpu_init (void) 768 { 769 extern void __cpuinit ia64_mmu_init (void *); 770 unsigned long num_phys_stacked; 771 pal_vm_info_2_u_t vmi; 772 unsigned int max_ctx; 773 struct cpuinfo_ia64 *cpu_info; 774 void *cpu_data; 775 776 cpu_data = per_cpu_init(); 777 778 /* 779 * We set ar.k3 so that assembly code in MCA handler can compute 780 * physical addresses of per cpu variables with a simple: 781 * phys = ar.k3 + &per_cpu_var 782 */ 783 ia64_set_kr(IA64_KR_PER_CPU_DATA, 784 ia64_tpa(cpu_data) - (long) __per_cpu_start); 785 786 get_max_cacheline_size(); 787 788 /* 789 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 790 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 791 * depends on the data returned by identify_cpu(). We break the dependency by 792 * accessing cpu_data() through the canonical per-CPU address. 793 */ 794 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 795 identify_cpu(cpu_info); 796 797 #ifdef CONFIG_MCKINLEY 798 { 799 # define FEATURE_SET 16 800 struct ia64_pal_retval iprv; 801 802 if (cpu_info->family == 0x1f) { 803 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 804 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 805 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 806 (iprv.v1 | 0x80), FEATURE_SET, 0); 807 } 808 } 809 #endif 810 811 /* Clear the stack memory reserved for pt_regs: */ 812 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 813 814 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 815 816 /* 817 * Initialize the page-table base register to a global 818 * directory with all zeroes. This ensure that we can handle 819 * TLB-misses to user address-space even before we created the 820 * first user address-space. This may happen, e.g., due to 821 * aggressive use of lfetch.fault. 822 */ 823 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 824 825 /* 826 * Initialize default control register to defer speculative faults except 827 * for those arising from TLB misses, which are not deferred. The 828 * kernel MUST NOT depend on a particular setting of these bits (in other words, 829 * the kernel must have recovery code for all speculative accesses). Turn on 830 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 831 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 832 * be fine). 833 */ 834 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 835 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 836 atomic_inc(&init_mm.mm_count); 837 current->active_mm = &init_mm; 838 if (current->mm) 839 BUG(); 840 841 ia64_mmu_init(ia64_imva(cpu_data)); 842 ia64_mca_cpu_init(ia64_imva(cpu_data)); 843 844 #ifdef CONFIG_IA32_SUPPORT 845 ia32_cpu_init(); 846 #endif 847 848 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 849 ia64_set_itc(0); 850 851 /* disable all local interrupt sources: */ 852 ia64_set_itv(1 << 16); 853 ia64_set_lrr0(1 << 16); 854 ia64_set_lrr1(1 << 16); 855 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 856 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 857 858 /* clear TPR & XTP to enable all interrupt classes: */ 859 ia64_setreg(_IA64_REG_CR_TPR, 0); 860 #ifdef CONFIG_SMP 861 normal_xtp(); 862 #endif 863 864 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 865 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 866 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 867 else { 868 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 869 max_ctx = (1U << 15) - 1; /* use architected minimum */ 870 } 871 while (max_ctx < ia64_ctx.max_ctx) { 872 unsigned int old = ia64_ctx.max_ctx; 873 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 874 break; 875 } 876 877 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 878 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 879 "stacked regs\n"); 880 num_phys_stacked = 96; 881 } 882 /* size of physical stacked register partition plus 8 bytes: */ 883 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 884 platform_cpu_init(); 885 pm_idle = default_idle; 886 } 887 888 /* 889 * On SMP systems, when the scheduler does migration-cost autodetection, 890 * it needs a way to flush as much of the CPU's caches as possible. 891 */ 892 void sched_cacheflush(void) 893 { 894 ia64_sal_cache_flush(3); 895 } 896 897 void __init 898 check_bugs (void) 899 { 900 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 901 (unsigned long) __end___mckinley_e9_bundles); 902 } 903