1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/config.h> 26 #include <linux/module.h> 27 #include <linux/init.h> 28 29 #include <linux/acpi.h> 30 #include <linux/bootmem.h> 31 #include <linux/console.h> 32 #include <linux/delay.h> 33 #include <linux/kernel.h> 34 #include <linux/reboot.h> 35 #include <linux/sched.h> 36 #include <linux/seq_file.h> 37 #include <linux/string.h> 38 #include <linux/threads.h> 39 #include <linux/tty.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/platform.h> 45 #include <linux/pm.h> 46 #include <linux/cpufreq.h> 47 48 #include <asm/ia32.h> 49 #include <asm/machvec.h> 50 #include <asm/mca.h> 51 #include <asm/meminit.h> 52 #include <asm/page.h> 53 #include <asm/patch.h> 54 #include <asm/pgtable.h> 55 #include <asm/processor.h> 56 #include <asm/sal.h> 57 #include <asm/sections.h> 58 #include <asm/serial.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/system.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 75 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 76 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8); 77 unsigned long ia64_cycles_per_usec; 78 struct ia64_boot_param *ia64_boot_param; 79 struct screen_info screen_info; 80 unsigned long vga_console_iobase; 81 unsigned long vga_console_membase; 82 83 static struct resource data_resource = { 84 .name = "Kernel data", 85 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 86 }; 87 88 static struct resource code_resource = { 89 .name = "Kernel code", 90 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 91 }; 92 extern void efi_initialize_iomem_resources(struct resource *, 93 struct resource *); 94 extern char _text[], _end[], _etext[]; 95 96 unsigned long ia64_max_cacheline_size; 97 98 int dma_get_cache_alignment(void) 99 { 100 return ia64_max_cacheline_size; 101 } 102 EXPORT_SYMBOL(dma_get_cache_alignment); 103 104 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 105 EXPORT_SYMBOL(ia64_iobase); 106 struct io_space io_space[MAX_IO_SPACES]; 107 EXPORT_SYMBOL(io_space); 108 unsigned int num_io_spaces; 109 110 /* 111 * "flush_icache_range()" needs to know what processor dependent stride size to use 112 * when it makes i-cache(s) coherent with d-caches. 113 */ 114 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 115 unsigned long ia64_i_cache_stride_shift = ~0; 116 117 /* 118 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 119 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 120 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 121 * address of the second buffer must be aligned to (merge_mask+1) in order to be 122 * mergeable). By default, we assume there is no I/O MMU which can merge physically 123 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 124 * page-size of 2^64. 125 */ 126 unsigned long ia64_max_iommu_merge_mask = ~0UL; 127 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 128 129 /* 130 * We use a special marker for the end of memory and it uses the extra (+1) slot 131 */ 132 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1]; 133 int num_rsvd_regions; 134 135 136 /* 137 * Filter incoming memory segments based on the primitive map created from the boot 138 * parameters. Segments contained in the map are removed from the memory ranges. A 139 * caller-specified function is called with the memory ranges that remain after filtering. 140 * This routine does not assume the incoming segments are sorted. 141 */ 142 int 143 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 144 { 145 unsigned long range_start, range_end, prev_start; 146 void (*func)(unsigned long, unsigned long, int); 147 int i; 148 149 #if IGNORE_PFN0 150 if (start == PAGE_OFFSET) { 151 printk(KERN_WARNING "warning: skipping physical page 0\n"); 152 start += PAGE_SIZE; 153 if (start >= end) return 0; 154 } 155 #endif 156 /* 157 * lowest possible address(walker uses virtual) 158 */ 159 prev_start = PAGE_OFFSET; 160 func = arg; 161 162 for (i = 0; i < num_rsvd_regions; ++i) { 163 range_start = max(start, prev_start); 164 range_end = min(end, rsvd_region[i].start); 165 166 if (range_start < range_end) 167 call_pernode_memory(__pa(range_start), range_end - range_start, func); 168 169 /* nothing more available in this segment */ 170 if (range_end == end) return 0; 171 172 prev_start = rsvd_region[i].end; 173 } 174 /* end of memory marker allows full processing inside loop body */ 175 return 0; 176 } 177 178 static void 179 sort_regions (struct rsvd_region *rsvd_region, int max) 180 { 181 int j; 182 183 /* simple bubble sorting */ 184 while (max--) { 185 for (j = 0; j < max; ++j) { 186 if (rsvd_region[j].start > rsvd_region[j+1].start) { 187 struct rsvd_region tmp; 188 tmp = rsvd_region[j]; 189 rsvd_region[j] = rsvd_region[j + 1]; 190 rsvd_region[j + 1] = tmp; 191 } 192 } 193 } 194 } 195 196 /* 197 * Request address space for all standard resources 198 */ 199 static int __init register_memory(void) 200 { 201 code_resource.start = ia64_tpa(_text); 202 code_resource.end = ia64_tpa(_etext) - 1; 203 data_resource.start = ia64_tpa(_etext); 204 data_resource.end = ia64_tpa(_end) - 1; 205 efi_initialize_iomem_resources(&code_resource, &data_resource); 206 207 return 0; 208 } 209 210 __initcall(register_memory); 211 212 /** 213 * reserve_memory - setup reserved memory areas 214 * 215 * Setup the reserved memory areas set aside for the boot parameters, 216 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 217 * see include/asm-ia64/meminit.h if you need to define more. 218 */ 219 void 220 reserve_memory (void) 221 { 222 int n = 0; 223 224 /* 225 * none of the entries in this table overlap 226 */ 227 rsvd_region[n].start = (unsigned long) ia64_boot_param; 228 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 229 n++; 230 231 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 232 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 233 n++; 234 235 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 236 rsvd_region[n].end = (rsvd_region[n].start 237 + strlen(__va(ia64_boot_param->command_line)) + 1); 238 n++; 239 240 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 241 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 242 n++; 243 244 #ifdef CONFIG_BLK_DEV_INITRD 245 if (ia64_boot_param->initrd_start) { 246 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 247 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 248 n++; 249 } 250 #endif 251 252 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 253 n++; 254 255 /* end of memory marker */ 256 rsvd_region[n].start = ~0UL; 257 rsvd_region[n].end = ~0UL; 258 n++; 259 260 num_rsvd_regions = n; 261 262 sort_regions(rsvd_region, num_rsvd_regions); 263 } 264 265 /** 266 * find_initrd - get initrd parameters from the boot parameter structure 267 * 268 * Grab the initrd start and end from the boot parameter struct given us by 269 * the boot loader. 270 */ 271 void 272 find_initrd (void) 273 { 274 #ifdef CONFIG_BLK_DEV_INITRD 275 if (ia64_boot_param->initrd_start) { 276 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 277 initrd_end = initrd_start+ia64_boot_param->initrd_size; 278 279 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 280 initrd_start, ia64_boot_param->initrd_size); 281 } 282 #endif 283 } 284 285 static void __init 286 io_port_init (void) 287 { 288 unsigned long phys_iobase; 289 290 /* 291 * Set `iobase' based on the EFI memory map or, failing that, the 292 * value firmware left in ar.k0. 293 * 294 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 295 * the port's virtual address, so ia32_load_state() loads it with a 296 * user virtual address. But in ia64 mode, glibc uses the 297 * *physical* address in ar.k0 to mmap the appropriate area from 298 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 299 * cases, user-mode can only use the legacy 0-64K I/O port space. 300 * 301 * ar.k0 is not involved in kernel I/O port accesses, which can use 302 * any of the I/O port spaces and are done via MMIO using the 303 * virtual mmio_base from the appropriate io_space[]. 304 */ 305 phys_iobase = efi_get_iobase(); 306 if (!phys_iobase) { 307 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 308 printk(KERN_INFO "No I/O port range found in EFI memory map, " 309 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 310 } 311 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 312 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 313 314 /* setup legacy IO port space */ 315 io_space[0].mmio_base = ia64_iobase; 316 io_space[0].sparse = 1; 317 num_io_spaces = 1; 318 } 319 320 /** 321 * early_console_setup - setup debugging console 322 * 323 * Consoles started here require little enough setup that we can start using 324 * them very early in the boot process, either right after the machine 325 * vector initialization, or even before if the drivers can detect their hw. 326 * 327 * Returns non-zero if a console couldn't be setup. 328 */ 329 static inline int __init 330 early_console_setup (char *cmdline) 331 { 332 int earlycons = 0; 333 334 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 335 { 336 extern int sn_serial_console_early_setup(void); 337 if (!sn_serial_console_early_setup()) 338 earlycons++; 339 } 340 #endif 341 #ifdef CONFIG_EFI_PCDP 342 if (!efi_setup_pcdp_console(cmdline)) 343 earlycons++; 344 #endif 345 #ifdef CONFIG_SERIAL_8250_CONSOLE 346 if (!early_serial_console_init(cmdline)) 347 earlycons++; 348 #endif 349 350 return (earlycons) ? 0 : -1; 351 } 352 353 static inline void 354 mark_bsp_online (void) 355 { 356 #ifdef CONFIG_SMP 357 /* If we register an early console, allow CPU 0 to printk */ 358 cpu_set(smp_processor_id(), cpu_online_map); 359 #endif 360 } 361 362 #ifdef CONFIG_SMP 363 static void 364 check_for_logical_procs (void) 365 { 366 pal_logical_to_physical_t info; 367 s64 status; 368 369 status = ia64_pal_logical_to_phys(0, &info); 370 if (status == -1) { 371 printk(KERN_INFO "No logical to physical processor mapping " 372 "available\n"); 373 return; 374 } 375 if (status) { 376 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n", 377 status); 378 return; 379 } 380 /* 381 * Total number of siblings that BSP has. Though not all of them 382 * may have booted successfully. The correct number of siblings 383 * booted is in info.overview_num_log. 384 */ 385 smp_num_siblings = info.overview_tpc; 386 smp_num_cpucores = info.overview_cpp; 387 } 388 #endif 389 390 void __init 391 setup_arch (char **cmdline_p) 392 { 393 unw_init(); 394 395 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 396 397 *cmdline_p = __va(ia64_boot_param->command_line); 398 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE); 399 400 efi_init(); 401 io_port_init(); 402 403 #ifdef CONFIG_IA64_GENERIC 404 { 405 const char *mvec_name = strstr (*cmdline_p, "machvec="); 406 char str[64]; 407 408 if (mvec_name) { 409 const char *end; 410 size_t len; 411 412 mvec_name += 8; 413 end = strchr (mvec_name, ' '); 414 if (end) 415 len = end - mvec_name; 416 else 417 len = strlen (mvec_name); 418 len = min(len, sizeof (str) - 1); 419 strncpy (str, mvec_name, len); 420 str[len] = '\0'; 421 mvec_name = str; 422 } else 423 mvec_name = acpi_get_sysname(); 424 machvec_init(mvec_name); 425 } 426 #endif 427 428 if (early_console_setup(*cmdline_p) == 0) 429 mark_bsp_online(); 430 431 #ifdef CONFIG_ACPI 432 /* Initialize the ACPI boot-time table parser */ 433 acpi_table_init(); 434 # ifdef CONFIG_ACPI_NUMA 435 acpi_numa_init(); 436 # endif 437 #else 438 # ifdef CONFIG_SMP 439 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 440 # endif 441 #endif /* CONFIG_APCI_BOOT */ 442 443 find_memory(); 444 445 /* process SAL system table: */ 446 ia64_sal_init(efi.sal_systab); 447 448 #ifdef CONFIG_SMP 449 cpu_physical_id(0) = hard_smp_processor_id(); 450 451 cpu_set(0, cpu_sibling_map[0]); 452 cpu_set(0, cpu_core_map[0]); 453 454 check_for_logical_procs(); 455 if (smp_num_cpucores > 1) 456 printk(KERN_INFO 457 "cpu package is Multi-Core capable: number of cores=%d\n", 458 smp_num_cpucores); 459 if (smp_num_siblings > 1) 460 printk(KERN_INFO 461 "cpu package is Multi-Threading capable: number of siblings=%d\n", 462 smp_num_siblings); 463 #endif 464 465 cpu_init(); /* initialize the bootstrap CPU */ 466 mmu_context_init(); /* initialize context_id bitmap */ 467 468 #ifdef CONFIG_ACPI 469 acpi_boot_init(); 470 #endif 471 472 #ifdef CONFIG_VT 473 if (!conswitchp) { 474 # if defined(CONFIG_DUMMY_CONSOLE) 475 conswitchp = &dummy_con; 476 # endif 477 # if defined(CONFIG_VGA_CONSOLE) 478 /* 479 * Non-legacy systems may route legacy VGA MMIO range to system 480 * memory. vga_con probes the MMIO hole, so memory looks like 481 * a VGA device to it. The EFI memory map can tell us if it's 482 * memory so we can avoid this problem. 483 */ 484 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 485 conswitchp = &vga_con; 486 # endif 487 } 488 #endif 489 490 /* enable IA-64 Machine Check Abort Handling unless disabled */ 491 if (!strstr(saved_command_line, "nomca")) 492 ia64_mca_init(); 493 494 platform_setup(cmdline_p); 495 paging_init(); 496 } 497 498 /* 499 * Display cpu info for all cpu's. 500 */ 501 static int 502 show_cpuinfo (struct seq_file *m, void *v) 503 { 504 #ifdef CONFIG_SMP 505 # define lpj c->loops_per_jiffy 506 # define cpunum c->cpu 507 #else 508 # define lpj loops_per_jiffy 509 # define cpunum 0 510 #endif 511 static struct { 512 unsigned long mask; 513 const char *feature_name; 514 } feature_bits[] = { 515 { 1UL << 0, "branchlong" }, 516 { 1UL << 1, "spontaneous deferral"}, 517 { 1UL << 2, "16-byte atomic ops" } 518 }; 519 char family[32], features[128], *cp, sep; 520 struct cpuinfo_ia64 *c = v; 521 unsigned long mask; 522 unsigned long proc_freq; 523 int i; 524 525 mask = c->features; 526 527 switch (c->family) { 528 case 0x07: memcpy(family, "Itanium", 8); break; 529 case 0x1f: memcpy(family, "Itanium 2", 10); break; 530 default: sprintf(family, "%u", c->family); break; 531 } 532 533 /* build the feature string: */ 534 memcpy(features, " standard", 10); 535 cp = features; 536 sep = 0; 537 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) { 538 if (mask & feature_bits[i].mask) { 539 if (sep) 540 *cp++ = sep; 541 sep = ','; 542 *cp++ = ' '; 543 strcpy(cp, feature_bits[i].feature_name); 544 cp += strlen(feature_bits[i].feature_name); 545 mask &= ~feature_bits[i].mask; 546 } 547 } 548 if (mask) { 549 /* print unknown features as a hex value: */ 550 if (sep) 551 *cp++ = sep; 552 sprintf(cp, " 0x%lx", mask); 553 } 554 555 proc_freq = cpufreq_quick_get(cpunum); 556 if (!proc_freq) 557 proc_freq = c->proc_freq / 1000; 558 559 seq_printf(m, 560 "processor : %d\n" 561 "vendor : %s\n" 562 "arch : IA-64\n" 563 "family : %s\n" 564 "model : %u\n" 565 "revision : %u\n" 566 "archrev : %u\n" 567 "features :%s\n" /* don't change this---it _is_ right! */ 568 "cpu number : %lu\n" 569 "cpu regs : %u\n" 570 "cpu MHz : %lu.%06lu\n" 571 "itc MHz : %lu.%06lu\n" 572 "BogoMIPS : %lu.%02lu\n", 573 cpunum, c->vendor, family, c->model, c->revision, c->archrev, 574 features, c->ppn, c->number, 575 proc_freq / 1000, proc_freq % 1000, 576 c->itc_freq / 1000000, c->itc_freq % 1000000, 577 lpj*HZ/500000, (lpj*HZ/5000) % 100); 578 #ifdef CONFIG_SMP 579 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 580 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 581 seq_printf(m, 582 "physical id: %u\n" 583 "core id : %u\n" 584 "thread id : %u\n", 585 c->socket_id, c->core_id, c->thread_id); 586 #endif 587 seq_printf(m,"\n"); 588 589 return 0; 590 } 591 592 static void * 593 c_start (struct seq_file *m, loff_t *pos) 594 { 595 #ifdef CONFIG_SMP 596 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 597 ++*pos; 598 #endif 599 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 600 } 601 602 static void * 603 c_next (struct seq_file *m, void *v, loff_t *pos) 604 { 605 ++*pos; 606 return c_start(m, pos); 607 } 608 609 static void 610 c_stop (struct seq_file *m, void *v) 611 { 612 } 613 614 struct seq_operations cpuinfo_op = { 615 .start = c_start, 616 .next = c_next, 617 .stop = c_stop, 618 .show = show_cpuinfo 619 }; 620 621 void 622 identify_cpu (struct cpuinfo_ia64 *c) 623 { 624 union { 625 unsigned long bits[5]; 626 struct { 627 /* id 0 & 1: */ 628 char vendor[16]; 629 630 /* id 2 */ 631 u64 ppn; /* processor serial number */ 632 633 /* id 3: */ 634 unsigned number : 8; 635 unsigned revision : 8; 636 unsigned model : 8; 637 unsigned family : 8; 638 unsigned archrev : 8; 639 unsigned reserved : 24; 640 641 /* id 4: */ 642 u64 features; 643 } field; 644 } cpuid; 645 pal_vm_info_1_u_t vm1; 646 pal_vm_info_2_u_t vm2; 647 pal_status_t status; 648 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 649 int i; 650 651 for (i = 0; i < 5; ++i) 652 cpuid.bits[i] = ia64_get_cpuid(i); 653 654 memcpy(c->vendor, cpuid.field.vendor, 16); 655 #ifdef CONFIG_SMP 656 c->cpu = smp_processor_id(); 657 658 /* below default values will be overwritten by identify_siblings() 659 * for Multi-Threading/Multi-Core capable cpu's 660 */ 661 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 662 c->socket_id = -1; 663 664 identify_siblings(c); 665 #endif 666 c->ppn = cpuid.field.ppn; 667 c->number = cpuid.field.number; 668 c->revision = cpuid.field.revision; 669 c->model = cpuid.field.model; 670 c->family = cpuid.field.family; 671 c->archrev = cpuid.field.archrev; 672 c->features = cpuid.field.features; 673 674 status = ia64_pal_vm_summary(&vm1, &vm2); 675 if (status == PAL_STATUS_SUCCESS) { 676 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 677 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 678 } 679 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 680 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 681 } 682 683 void 684 setup_per_cpu_areas (void) 685 { 686 /* start_kernel() requires this... */ 687 } 688 689 /* 690 * Calculate the max. cache line size. 691 * 692 * In addition, the minimum of the i-cache stride sizes is calculated for 693 * "flush_icache_range()". 694 */ 695 static void 696 get_max_cacheline_size (void) 697 { 698 unsigned long line_size, max = 1; 699 unsigned int cache_size = 0; 700 u64 l, levels, unique_caches; 701 pal_cache_config_info_t cci; 702 s64 status; 703 704 status = ia64_pal_cache_summary(&levels, &unique_caches); 705 if (status != 0) { 706 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 707 __FUNCTION__, status); 708 max = SMP_CACHE_BYTES; 709 /* Safest setup for "flush_icache_range()" */ 710 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 711 goto out; 712 } 713 714 for (l = 0; l < levels; ++l) { 715 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 716 &cci); 717 if (status != 0) { 718 printk(KERN_ERR 719 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 720 __FUNCTION__, l, status); 721 max = SMP_CACHE_BYTES; 722 /* The safest setup for "flush_icache_range()" */ 723 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 724 cci.pcci_unified = 1; 725 } 726 line_size = 1 << cci.pcci_line_size; 727 if (line_size > max) 728 max = line_size; 729 if (cache_size < cci.pcci_cache_size) 730 cache_size = cci.pcci_cache_size; 731 if (!cci.pcci_unified) { 732 status = ia64_pal_cache_config_info(l, 733 /* cache_type (instruction)= */ 1, 734 &cci); 735 if (status != 0) { 736 printk(KERN_ERR 737 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 738 __FUNCTION__, l, status); 739 /* The safest setup for "flush_icache_range()" */ 740 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 741 } 742 } 743 if (cci.pcci_stride < ia64_i_cache_stride_shift) 744 ia64_i_cache_stride_shift = cci.pcci_stride; 745 } 746 out: 747 #ifdef CONFIG_SMP 748 max_cache_size = max(max_cache_size, cache_size); 749 #endif 750 if (max > ia64_max_cacheline_size) 751 ia64_max_cacheline_size = max; 752 } 753 754 /* 755 * cpu_init() initializes state that is per-CPU. This function acts 756 * as a 'CPU state barrier', nothing should get across. 757 */ 758 void 759 cpu_init (void) 760 { 761 extern void __devinit ia64_mmu_init (void *); 762 unsigned long num_phys_stacked; 763 pal_vm_info_2_u_t vmi; 764 unsigned int max_ctx; 765 struct cpuinfo_ia64 *cpu_info; 766 void *cpu_data; 767 768 cpu_data = per_cpu_init(); 769 770 /* 771 * We set ar.k3 so that assembly code in MCA handler can compute 772 * physical addresses of per cpu variables with a simple: 773 * phys = ar.k3 + &per_cpu_var 774 */ 775 ia64_set_kr(IA64_KR_PER_CPU_DATA, 776 ia64_tpa(cpu_data) - (long) __per_cpu_start); 777 778 get_max_cacheline_size(); 779 780 /* 781 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 782 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 783 * depends on the data returned by identify_cpu(). We break the dependency by 784 * accessing cpu_data() through the canonical per-CPU address. 785 */ 786 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 787 identify_cpu(cpu_info); 788 789 #ifdef CONFIG_MCKINLEY 790 { 791 # define FEATURE_SET 16 792 struct ia64_pal_retval iprv; 793 794 if (cpu_info->family == 0x1f) { 795 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 796 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 797 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 798 (iprv.v1 | 0x80), FEATURE_SET, 0); 799 } 800 } 801 #endif 802 803 /* Clear the stack memory reserved for pt_regs: */ 804 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs)); 805 806 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 807 808 /* 809 * Initialize the page-table base register to a global 810 * directory with all zeroes. This ensure that we can handle 811 * TLB-misses to user address-space even before we created the 812 * first user address-space. This may happen, e.g., due to 813 * aggressive use of lfetch.fault. 814 */ 815 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 816 817 /* 818 * Initialize default control register to defer speculative faults except 819 * for those arising from TLB misses, which are not deferred. The 820 * kernel MUST NOT depend on a particular setting of these bits (in other words, 821 * the kernel must have recovery code for all speculative accesses). Turn on 822 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 823 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 824 * be fine). 825 */ 826 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 827 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 828 atomic_inc(&init_mm.mm_count); 829 current->active_mm = &init_mm; 830 if (current->mm) 831 BUG(); 832 833 ia64_mmu_init(ia64_imva(cpu_data)); 834 ia64_mca_cpu_init(ia64_imva(cpu_data)); 835 836 #ifdef CONFIG_IA32_SUPPORT 837 ia32_cpu_init(); 838 #endif 839 840 /* Clear ITC to eliminiate sched_clock() overflows in human time. */ 841 ia64_set_itc(0); 842 843 /* disable all local interrupt sources: */ 844 ia64_set_itv(1 << 16); 845 ia64_set_lrr0(1 << 16); 846 ia64_set_lrr1(1 << 16); 847 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 848 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 849 850 /* clear TPR & XTP to enable all interrupt classes: */ 851 ia64_setreg(_IA64_REG_CR_TPR, 0); 852 #ifdef CONFIG_SMP 853 normal_xtp(); 854 #endif 855 856 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 857 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 858 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 859 else { 860 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 861 max_ctx = (1U << 15) - 1; /* use architected minimum */ 862 } 863 while (max_ctx < ia64_ctx.max_ctx) { 864 unsigned int old = ia64_ctx.max_ctx; 865 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 866 break; 867 } 868 869 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 870 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 871 "stacked regs\n"); 872 num_phys_stacked = 96; 873 } 874 /* size of physical stacked register partition plus 8 bytes: */ 875 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8; 876 platform_cpu_init(); 877 pm_idle = default_idle; 878 } 879 880 /* 881 * On SMP systems, when the scheduler does migration-cost autodetection, 882 * it needs a way to flush as much of the CPU's caches as possible. 883 */ 884 void sched_cacheflush(void) 885 { 886 ia64_sal_cache_flush(3); 887 } 888 889 void 890 check_bugs (void) 891 { 892 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 893 (unsigned long) __end___mckinley_e9_bundles); 894 } 895