1 /* 2 * Architecture-specific setup. 3 * 4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co 5 * David Mosberger-Tang <davidm@hpl.hp.com> 6 * Stephane Eranian <eranian@hpl.hp.com> 7 * Copyright (C) 2000, 2004 Intel Corp 8 * Rohit Seth <rohit.seth@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Gordon Jin <gordon.jin@intel.com> 11 * Copyright (C) 1999 VA Linux Systems 12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 13 * 14 * 12/26/04 S.Siddha, G.Jin, R.Seth 15 * Add multi-threading and multi-core detection 16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo(). 17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map 18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes 19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes... 20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP 21 * 01/07/99 S.Eranian added the support for command line argument 22 * 06/24/99 W.Drummond added boot_cpu_data. 23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()" 24 */ 25 #include <linux/module.h> 26 #include <linux/init.h> 27 28 #include <linux/acpi.h> 29 #include <linux/bootmem.h> 30 #include <linux/console.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/reboot.h> 34 #include <linux/sched.h> 35 #include <linux/seq_file.h> 36 #include <linux/string.h> 37 #include <linux/threads.h> 38 #include <linux/screen_info.h> 39 #include <linux/dmi.h> 40 #include <linux/serial.h> 41 #include <linux/serial_core.h> 42 #include <linux/efi.h> 43 #include <linux/initrd.h> 44 #include <linux/pm.h> 45 #include <linux/cpufreq.h> 46 #include <linux/kexec.h> 47 #include <linux/crash_dump.h> 48 49 #include <asm/ia32.h> 50 #include <asm/machvec.h> 51 #include <asm/mca.h> 52 #include <asm/meminit.h> 53 #include <asm/page.h> 54 #include <asm/patch.h> 55 #include <asm/pgtable.h> 56 #include <asm/processor.h> 57 #include <asm/sal.h> 58 #include <asm/sections.h> 59 #include <asm/setup.h> 60 #include <asm/smp.h> 61 #include <asm/system.h> 62 #include <asm/unistd.h> 63 #include <asm/hpsim.h> 64 65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE) 66 # error "struct cpuinfo_ia64 too big!" 67 #endif 68 69 #ifdef CONFIG_SMP 70 unsigned long __per_cpu_offset[NR_CPUS]; 71 EXPORT_SYMBOL(__per_cpu_offset); 72 #endif 73 74 extern void ia64_setup_printk_clock(void); 75 76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info); 77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset); 78 unsigned long ia64_cycles_per_usec; 79 struct ia64_boot_param *ia64_boot_param; 80 struct screen_info screen_info; 81 unsigned long vga_console_iobase; 82 unsigned long vga_console_membase; 83 84 static struct resource data_resource = { 85 .name = "Kernel data", 86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 87 }; 88 89 static struct resource code_resource = { 90 .name = "Kernel code", 91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 92 }; 93 94 static struct resource bss_resource = { 95 .name = "Kernel bss", 96 .flags = IORESOURCE_BUSY | IORESOURCE_MEM 97 }; 98 extern char _text[], _end[], _etext[], _edata[], _bss[]; 99 100 unsigned long ia64_max_cacheline_size; 101 102 int dma_get_cache_alignment(void) 103 { 104 return ia64_max_cacheline_size; 105 } 106 EXPORT_SYMBOL(dma_get_cache_alignment); 107 108 unsigned long ia64_iobase; /* virtual address for I/O accesses */ 109 EXPORT_SYMBOL(ia64_iobase); 110 struct io_space io_space[MAX_IO_SPACES]; 111 EXPORT_SYMBOL(io_space); 112 unsigned int num_io_spaces; 113 114 /* 115 * "flush_icache_range()" needs to know what processor dependent stride size to use 116 * when it makes i-cache(s) coherent with d-caches. 117 */ 118 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 119 unsigned long ia64_i_cache_stride_shift = ~0; 120 121 /* 122 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 123 * mask specifies a mask of address bits that must be 0 in order for two buffers to be 124 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start 125 * address of the second buffer must be aligned to (merge_mask+1) in order to be 126 * mergeable). By default, we assume there is no I/O MMU which can merge physically 127 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu 128 * page-size of 2^64. 129 */ 130 unsigned long ia64_max_iommu_merge_mask = ~0UL; 131 EXPORT_SYMBOL(ia64_max_iommu_merge_mask); 132 133 /* 134 * We use a special marker for the end of memory and it uses the extra (+1) slot 135 */ 136 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata; 137 int num_rsvd_regions __initdata; 138 139 140 /* 141 * Filter incoming memory segments based on the primitive map created from the boot 142 * parameters. Segments contained in the map are removed from the memory ranges. A 143 * caller-specified function is called with the memory ranges that remain after filtering. 144 * This routine does not assume the incoming segments are sorted. 145 */ 146 int __init 147 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg) 148 { 149 unsigned long range_start, range_end, prev_start; 150 void (*func)(unsigned long, unsigned long, int); 151 int i; 152 153 #if IGNORE_PFN0 154 if (start == PAGE_OFFSET) { 155 printk(KERN_WARNING "warning: skipping physical page 0\n"); 156 start += PAGE_SIZE; 157 if (start >= end) return 0; 158 } 159 #endif 160 /* 161 * lowest possible address(walker uses virtual) 162 */ 163 prev_start = PAGE_OFFSET; 164 func = arg; 165 166 for (i = 0; i < num_rsvd_regions; ++i) { 167 range_start = max(start, prev_start); 168 range_end = min(end, rsvd_region[i].start); 169 170 if (range_start < range_end) 171 call_pernode_memory(__pa(range_start), range_end - range_start, func); 172 173 /* nothing more available in this segment */ 174 if (range_end == end) return 0; 175 176 prev_start = rsvd_region[i].end; 177 } 178 /* end of memory marker allows full processing inside loop body */ 179 return 0; 180 } 181 182 static void __init 183 sort_regions (struct rsvd_region *rsvd_region, int max) 184 { 185 int j; 186 187 /* simple bubble sorting */ 188 while (max--) { 189 for (j = 0; j < max; ++j) { 190 if (rsvd_region[j].start > rsvd_region[j+1].start) { 191 struct rsvd_region tmp; 192 tmp = rsvd_region[j]; 193 rsvd_region[j] = rsvd_region[j + 1]; 194 rsvd_region[j + 1] = tmp; 195 } 196 } 197 } 198 } 199 200 /* 201 * Request address space for all standard resources 202 */ 203 static int __init register_memory(void) 204 { 205 code_resource.start = ia64_tpa(_text); 206 code_resource.end = ia64_tpa(_etext) - 1; 207 data_resource.start = ia64_tpa(_etext); 208 data_resource.end = ia64_tpa(_edata) - 1; 209 bss_resource.start = ia64_tpa(_bss); 210 bss_resource.end = ia64_tpa(_end) - 1; 211 efi_initialize_iomem_resources(&code_resource, &data_resource, 212 &bss_resource); 213 214 return 0; 215 } 216 217 __initcall(register_memory); 218 219 220 #ifdef CONFIG_KEXEC 221 static void __init setup_crashkernel(unsigned long total, int *n) 222 { 223 unsigned long long base = 0, size = 0; 224 int ret; 225 226 ret = parse_crashkernel(boot_command_line, total, 227 &size, &base); 228 if (ret == 0 && size > 0) { 229 if (!base) { 230 sort_regions(rsvd_region, *n); 231 base = kdump_find_rsvd_region(size, 232 rsvd_region, *n); 233 } 234 if (base != ~0UL) { 235 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " 236 "for crashkernel (System RAM: %ldMB)\n", 237 (unsigned long)(size >> 20), 238 (unsigned long)(base >> 20), 239 (unsigned long)(total >> 20)); 240 rsvd_region[*n].start = 241 (unsigned long)__va(base); 242 rsvd_region[*n].end = 243 (unsigned long)__va(base + size); 244 (*n)++; 245 crashk_res.start = base; 246 crashk_res.end = base + size - 1; 247 } 248 } 249 efi_memmap_res.start = ia64_boot_param->efi_memmap; 250 efi_memmap_res.end = efi_memmap_res.start + 251 ia64_boot_param->efi_memmap_size; 252 boot_param_res.start = __pa(ia64_boot_param); 253 boot_param_res.end = boot_param_res.start + 254 sizeof(*ia64_boot_param); 255 } 256 #else 257 static inline void __init setup_crashkernel(unsigned long total, int *n) 258 {} 259 #endif 260 261 /** 262 * reserve_memory - setup reserved memory areas 263 * 264 * Setup the reserved memory areas set aside for the boot parameters, 265 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined, 266 * see include/asm-ia64/meminit.h if you need to define more. 267 */ 268 void __init 269 reserve_memory (void) 270 { 271 int n = 0; 272 unsigned long total_memory; 273 274 /* 275 * none of the entries in this table overlap 276 */ 277 rsvd_region[n].start = (unsigned long) ia64_boot_param; 278 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param); 279 n++; 280 281 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap); 282 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size; 283 n++; 284 285 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line); 286 rsvd_region[n].end = (rsvd_region[n].start 287 + strlen(__va(ia64_boot_param->command_line)) + 1); 288 n++; 289 290 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START); 291 rsvd_region[n].end = (unsigned long) ia64_imva(_end); 292 n++; 293 294 #ifdef CONFIG_BLK_DEV_INITRD 295 if (ia64_boot_param->initrd_start) { 296 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start); 297 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size; 298 n++; 299 } 300 #endif 301 302 #ifdef CONFIG_PROC_VMCORE 303 if (reserve_elfcorehdr(&rsvd_region[n].start, 304 &rsvd_region[n].end) == 0) 305 n++; 306 #endif 307 308 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end); 309 n++; 310 311 setup_crashkernel(total_memory, &n); 312 313 /* end of memory marker */ 314 rsvd_region[n].start = ~0UL; 315 rsvd_region[n].end = ~0UL; 316 n++; 317 318 num_rsvd_regions = n; 319 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n); 320 321 sort_regions(rsvd_region, num_rsvd_regions); 322 } 323 324 325 /** 326 * find_initrd - get initrd parameters from the boot parameter structure 327 * 328 * Grab the initrd start and end from the boot parameter struct given us by 329 * the boot loader. 330 */ 331 void __init 332 find_initrd (void) 333 { 334 #ifdef CONFIG_BLK_DEV_INITRD 335 if (ia64_boot_param->initrd_start) { 336 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start); 337 initrd_end = initrd_start+ia64_boot_param->initrd_size; 338 339 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 340 initrd_start, ia64_boot_param->initrd_size); 341 } 342 #endif 343 } 344 345 static void __init 346 io_port_init (void) 347 { 348 unsigned long phys_iobase; 349 350 /* 351 * Set `iobase' based on the EFI memory map or, failing that, the 352 * value firmware left in ar.k0. 353 * 354 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute 355 * the port's virtual address, so ia32_load_state() loads it with a 356 * user virtual address. But in ia64 mode, glibc uses the 357 * *physical* address in ar.k0 to mmap the appropriate area from 358 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both 359 * cases, user-mode can only use the legacy 0-64K I/O port space. 360 * 361 * ar.k0 is not involved in kernel I/O port accesses, which can use 362 * any of the I/O port spaces and are done via MMIO using the 363 * virtual mmio_base from the appropriate io_space[]. 364 */ 365 phys_iobase = efi_get_iobase(); 366 if (!phys_iobase) { 367 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE); 368 printk(KERN_INFO "No I/O port range found in EFI memory map, " 369 "falling back to AR.KR0 (0x%lx)\n", phys_iobase); 370 } 371 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0); 372 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase)); 373 374 /* setup legacy IO port space */ 375 io_space[0].mmio_base = ia64_iobase; 376 io_space[0].sparse = 1; 377 num_io_spaces = 1; 378 } 379 380 /** 381 * early_console_setup - setup debugging console 382 * 383 * Consoles started here require little enough setup that we can start using 384 * them very early in the boot process, either right after the machine 385 * vector initialization, or even before if the drivers can detect their hw. 386 * 387 * Returns non-zero if a console couldn't be setup. 388 */ 389 static inline int __init 390 early_console_setup (char *cmdline) 391 { 392 int earlycons = 0; 393 394 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 395 { 396 extern int sn_serial_console_early_setup(void); 397 if (!sn_serial_console_early_setup()) 398 earlycons++; 399 } 400 #endif 401 #ifdef CONFIG_EFI_PCDP 402 if (!efi_setup_pcdp_console(cmdline)) 403 earlycons++; 404 #endif 405 if (!simcons_register()) 406 earlycons++; 407 408 return (earlycons) ? 0 : -1; 409 } 410 411 static inline void 412 mark_bsp_online (void) 413 { 414 #ifdef CONFIG_SMP 415 /* If we register an early console, allow CPU 0 to printk */ 416 cpu_set(smp_processor_id(), cpu_online_map); 417 #endif 418 } 419 420 static __initdata int nomca; 421 static __init int setup_nomca(char *s) 422 { 423 nomca = 1; 424 return 0; 425 } 426 early_param("nomca", setup_nomca); 427 428 #ifdef CONFIG_PROC_VMCORE 429 /* elfcorehdr= specifies the location of elf core header 430 * stored by the crashed kernel. 431 */ 432 static int __init parse_elfcorehdr(char *arg) 433 { 434 if (!arg) 435 return -EINVAL; 436 437 elfcorehdr_addr = memparse(arg, &arg); 438 return 0; 439 } 440 early_param("elfcorehdr", parse_elfcorehdr); 441 442 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end) 443 { 444 unsigned long length; 445 446 /* We get the address using the kernel command line, 447 * but the size is extracted from the EFI tables. 448 * Both address and size are required for reservation 449 * to work properly. 450 */ 451 452 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX) 453 return -EINVAL; 454 455 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) { 456 elfcorehdr_addr = ELFCORE_ADDR_MAX; 457 return -EINVAL; 458 } 459 460 *start = (unsigned long)__va(elfcorehdr_addr); 461 *end = *start + length; 462 return 0; 463 } 464 465 #endif /* CONFIG_PROC_VMCORE */ 466 467 void __init 468 setup_arch (char **cmdline_p) 469 { 470 unw_init(); 471 472 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist); 473 474 *cmdline_p = __va(ia64_boot_param->command_line); 475 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 476 477 efi_init(); 478 io_port_init(); 479 480 #ifdef CONFIG_IA64_GENERIC 481 /* machvec needs to be parsed from the command line 482 * before parse_early_param() is called to ensure 483 * that ia64_mv is initialised before any command line 484 * settings may cause console setup to occur 485 */ 486 machvec_init_from_cmdline(*cmdline_p); 487 #endif 488 489 parse_early_param(); 490 491 if (early_console_setup(*cmdline_p) == 0) 492 mark_bsp_online(); 493 494 #ifdef CONFIG_ACPI 495 /* Initialize the ACPI boot-time table parser */ 496 acpi_table_init(); 497 # ifdef CONFIG_ACPI_NUMA 498 acpi_numa_init(); 499 # endif 500 #else 501 # ifdef CONFIG_SMP 502 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ 503 # endif 504 #endif /* CONFIG_APCI_BOOT */ 505 506 find_memory(); 507 508 /* process SAL system table: */ 509 ia64_sal_init(__va(efi.sal_systab)); 510 511 ia64_setup_printk_clock(); 512 513 #ifdef CONFIG_SMP 514 cpu_physical_id(0) = hard_smp_processor_id(); 515 #endif 516 517 cpu_init(); /* initialize the bootstrap CPU */ 518 mmu_context_init(); /* initialize context_id bitmap */ 519 520 check_sal_cache_flush(); 521 522 #ifdef CONFIG_ACPI 523 acpi_boot_init(); 524 #endif 525 526 #ifdef CONFIG_VT 527 if (!conswitchp) { 528 # if defined(CONFIG_DUMMY_CONSOLE) 529 conswitchp = &dummy_con; 530 # endif 531 # if defined(CONFIG_VGA_CONSOLE) 532 /* 533 * Non-legacy systems may route legacy VGA MMIO range to system 534 * memory. vga_con probes the MMIO hole, so memory looks like 535 * a VGA device to it. The EFI memory map can tell us if it's 536 * memory so we can avoid this problem. 537 */ 538 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY) 539 conswitchp = &vga_con; 540 # endif 541 } 542 #endif 543 544 /* enable IA-64 Machine Check Abort Handling unless disabled */ 545 if (!nomca) 546 ia64_mca_init(); 547 548 platform_setup(cmdline_p); 549 paging_init(); 550 } 551 552 /* 553 * Display cpu info for all CPUs. 554 */ 555 static int 556 show_cpuinfo (struct seq_file *m, void *v) 557 { 558 #ifdef CONFIG_SMP 559 # define lpj c->loops_per_jiffy 560 # define cpunum c->cpu 561 #else 562 # define lpj loops_per_jiffy 563 # define cpunum 0 564 #endif 565 static struct { 566 unsigned long mask; 567 const char *feature_name; 568 } feature_bits[] = { 569 { 1UL << 0, "branchlong" }, 570 { 1UL << 1, "spontaneous deferral"}, 571 { 1UL << 2, "16-byte atomic ops" } 572 }; 573 char features[128], *cp, *sep; 574 struct cpuinfo_ia64 *c = v; 575 unsigned long mask; 576 unsigned long proc_freq; 577 int i, size; 578 579 mask = c->features; 580 581 /* build the feature string: */ 582 memcpy(features, "standard", 9); 583 cp = features; 584 size = sizeof(features); 585 sep = ""; 586 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) { 587 if (mask & feature_bits[i].mask) { 588 cp += snprintf(cp, size, "%s%s", sep, 589 feature_bits[i].feature_name), 590 sep = ", "; 591 mask &= ~feature_bits[i].mask; 592 size = sizeof(features) - (cp - features); 593 } 594 } 595 if (mask && size > 1) { 596 /* print unknown features as a hex value */ 597 snprintf(cp, size, "%s0x%lx", sep, mask); 598 } 599 600 proc_freq = cpufreq_quick_get(cpunum); 601 if (!proc_freq) 602 proc_freq = c->proc_freq / 1000; 603 604 seq_printf(m, 605 "processor : %d\n" 606 "vendor : %s\n" 607 "arch : IA-64\n" 608 "family : %u\n" 609 "model : %u\n" 610 "model name : %s\n" 611 "revision : %u\n" 612 "archrev : %u\n" 613 "features : %s\n" 614 "cpu number : %lu\n" 615 "cpu regs : %u\n" 616 "cpu MHz : %lu.%03lu\n" 617 "itc MHz : %lu.%06lu\n" 618 "BogoMIPS : %lu.%02lu\n", 619 cpunum, c->vendor, c->family, c->model, 620 c->model_name, c->revision, c->archrev, 621 features, c->ppn, c->number, 622 proc_freq / 1000, proc_freq % 1000, 623 c->itc_freq / 1000000, c->itc_freq % 1000000, 624 lpj*HZ/500000, (lpj*HZ/5000) % 100); 625 #ifdef CONFIG_SMP 626 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum])); 627 if (c->socket_id != -1) 628 seq_printf(m, "physical id: %u\n", c->socket_id); 629 if (c->threads_per_core > 1 || c->cores_per_socket > 1) 630 seq_printf(m, 631 "core id : %u\n" 632 "thread id : %u\n", 633 c->core_id, c->thread_id); 634 #endif 635 seq_printf(m,"\n"); 636 637 return 0; 638 } 639 640 static void * 641 c_start (struct seq_file *m, loff_t *pos) 642 { 643 #ifdef CONFIG_SMP 644 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map)) 645 ++*pos; 646 #endif 647 return *pos < NR_CPUS ? cpu_data(*pos) : NULL; 648 } 649 650 static void * 651 c_next (struct seq_file *m, void *v, loff_t *pos) 652 { 653 ++*pos; 654 return c_start(m, pos); 655 } 656 657 static void 658 c_stop (struct seq_file *m, void *v) 659 { 660 } 661 662 struct seq_operations cpuinfo_op = { 663 .start = c_start, 664 .next = c_next, 665 .stop = c_stop, 666 .show = show_cpuinfo 667 }; 668 669 #define MAX_BRANDS 8 670 static char brandname[MAX_BRANDS][128]; 671 672 static char * __cpuinit 673 get_model_name(__u8 family, __u8 model) 674 { 675 static int overflow; 676 char brand[128]; 677 int i; 678 679 memcpy(brand, "Unknown", 8); 680 if (ia64_pal_get_brand_info(brand)) { 681 if (family == 0x7) 682 memcpy(brand, "Merced", 7); 683 else if (family == 0x1f) switch (model) { 684 case 0: memcpy(brand, "McKinley", 9); break; 685 case 1: memcpy(brand, "Madison", 8); break; 686 case 2: memcpy(brand, "Madison up to 9M cache", 23); break; 687 } 688 } 689 for (i = 0; i < MAX_BRANDS; i++) 690 if (strcmp(brandname[i], brand) == 0) 691 return brandname[i]; 692 for (i = 0; i < MAX_BRANDS; i++) 693 if (brandname[i][0] == '\0') 694 return strcpy(brandname[i], brand); 695 if (overflow++ == 0) 696 printk(KERN_ERR 697 "%s: Table overflow. Some processor model information will be missing\n", 698 __FUNCTION__); 699 return "Unknown"; 700 } 701 702 static void __cpuinit 703 identify_cpu (struct cpuinfo_ia64 *c) 704 { 705 union { 706 unsigned long bits[5]; 707 struct { 708 /* id 0 & 1: */ 709 char vendor[16]; 710 711 /* id 2 */ 712 u64 ppn; /* processor serial number */ 713 714 /* id 3: */ 715 unsigned number : 8; 716 unsigned revision : 8; 717 unsigned model : 8; 718 unsigned family : 8; 719 unsigned archrev : 8; 720 unsigned reserved : 24; 721 722 /* id 4: */ 723 u64 features; 724 } field; 725 } cpuid; 726 pal_vm_info_1_u_t vm1; 727 pal_vm_info_2_u_t vm2; 728 pal_status_t status; 729 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */ 730 int i; 731 for (i = 0; i < 5; ++i) 732 cpuid.bits[i] = ia64_get_cpuid(i); 733 734 memcpy(c->vendor, cpuid.field.vendor, 16); 735 #ifdef CONFIG_SMP 736 c->cpu = smp_processor_id(); 737 738 /* below default values will be overwritten by identify_siblings() 739 * for Multi-Threading/Multi-Core capable CPUs 740 */ 741 c->threads_per_core = c->cores_per_socket = c->num_log = 1; 742 c->socket_id = -1; 743 744 identify_siblings(c); 745 746 if (c->threads_per_core > smp_num_siblings) 747 smp_num_siblings = c->threads_per_core; 748 #endif 749 c->ppn = cpuid.field.ppn; 750 c->number = cpuid.field.number; 751 c->revision = cpuid.field.revision; 752 c->model = cpuid.field.model; 753 c->family = cpuid.field.family; 754 c->archrev = cpuid.field.archrev; 755 c->features = cpuid.field.features; 756 c->model_name = get_model_name(c->family, c->model); 757 758 status = ia64_pal_vm_summary(&vm1, &vm2); 759 if (status == PAL_STATUS_SUCCESS) { 760 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb; 761 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size; 762 } 763 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1)); 764 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1)); 765 } 766 767 void __init 768 setup_per_cpu_areas (void) 769 { 770 /* start_kernel() requires this... */ 771 #ifdef CONFIG_ACPI_HOTPLUG_CPU 772 prefill_possible_map(); 773 #endif 774 } 775 776 /* 777 * Calculate the max. cache line size. 778 * 779 * In addition, the minimum of the i-cache stride sizes is calculated for 780 * "flush_icache_range()". 781 */ 782 static void __cpuinit 783 get_max_cacheline_size (void) 784 { 785 unsigned long line_size, max = 1; 786 u64 l, levels, unique_caches; 787 pal_cache_config_info_t cci; 788 s64 status; 789 790 status = ia64_pal_cache_summary(&levels, &unique_caches); 791 if (status != 0) { 792 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", 793 __FUNCTION__, status); 794 max = SMP_CACHE_BYTES; 795 /* Safest setup for "flush_icache_range()" */ 796 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 797 goto out; 798 } 799 800 for (l = 0; l < levels; ++l) { 801 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 802 &cci); 803 if (status != 0) { 804 printk(KERN_ERR 805 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 806 __FUNCTION__, l, status); 807 max = SMP_CACHE_BYTES; 808 /* The safest setup for "flush_icache_range()" */ 809 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 810 cci.pcci_unified = 1; 811 } 812 line_size = 1 << cci.pcci_line_size; 813 if (line_size > max) 814 max = line_size; 815 if (!cci.pcci_unified) { 816 status = ia64_pal_cache_config_info(l, 817 /* cache_type (instruction)= */ 1, 818 &cci); 819 if (status != 0) { 820 printk(KERN_ERR 821 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 822 __FUNCTION__, l, status); 823 /* The safest setup for "flush_icache_range()" */ 824 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 825 } 826 } 827 if (cci.pcci_stride < ia64_i_cache_stride_shift) 828 ia64_i_cache_stride_shift = cci.pcci_stride; 829 } 830 out: 831 if (max > ia64_max_cacheline_size) 832 ia64_max_cacheline_size = max; 833 } 834 835 /* 836 * cpu_init() initializes state that is per-CPU. This function acts 837 * as a 'CPU state barrier', nothing should get across. 838 */ 839 void __cpuinit 840 cpu_init (void) 841 { 842 extern void __cpuinit ia64_mmu_init (void *); 843 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG; 844 unsigned long num_phys_stacked; 845 pal_vm_info_2_u_t vmi; 846 unsigned int max_ctx; 847 struct cpuinfo_ia64 *cpu_info; 848 void *cpu_data; 849 850 cpu_data = per_cpu_init(); 851 #ifdef CONFIG_SMP 852 /* 853 * insert boot cpu into sibling and core mapes 854 * (must be done after per_cpu area is setup) 855 */ 856 if (smp_processor_id() == 0) { 857 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 858 cpu_set(0, cpu_core_map[0]); 859 } 860 #endif 861 862 /* 863 * We set ar.k3 so that assembly code in MCA handler can compute 864 * physical addresses of per cpu variables with a simple: 865 * phys = ar.k3 + &per_cpu_var 866 */ 867 ia64_set_kr(IA64_KR_PER_CPU_DATA, 868 ia64_tpa(cpu_data) - (long) __per_cpu_start); 869 870 get_max_cacheline_size(); 871 872 /* 873 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 874 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it 875 * depends on the data returned by identify_cpu(). We break the dependency by 876 * accessing cpu_data() through the canonical per-CPU address. 877 */ 878 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start); 879 identify_cpu(cpu_info); 880 881 #ifdef CONFIG_MCKINLEY 882 { 883 # define FEATURE_SET 16 884 struct ia64_pal_retval iprv; 885 886 if (cpu_info->family == 0x1f) { 887 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0); 888 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) 889 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, 890 (iprv.v1 | 0x80), FEATURE_SET, 0); 891 } 892 } 893 #endif 894 895 /* Clear the stack memory reserved for pt_regs: */ 896 memset(task_pt_regs(current), 0, sizeof(struct pt_regs)); 897 898 ia64_set_kr(IA64_KR_FPU_OWNER, 0); 899 900 /* 901 * Initialize the page-table base register to a global 902 * directory with all zeroes. This ensure that we can handle 903 * TLB-misses to user address-space even before we created the 904 * first user address-space. This may happen, e.g., due to 905 * aggressive use of lfetch.fault. 906 */ 907 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page))); 908 909 /* 910 * Initialize default control register to defer speculative faults except 911 * for those arising from TLB misses, which are not deferred. The 912 * kernel MUST NOT depend on a particular setting of these bits (in other words, 913 * the kernel must have recovery code for all speculative accesses). Turn on 914 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps 915 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll 916 * be fine). 917 */ 918 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR 919 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC)); 920 atomic_inc(&init_mm.mm_count); 921 current->active_mm = &init_mm; 922 if (current->mm) 923 BUG(); 924 925 ia64_mmu_init(ia64_imva(cpu_data)); 926 ia64_mca_cpu_init(ia64_imva(cpu_data)); 927 928 #ifdef CONFIG_IA32_SUPPORT 929 ia32_cpu_init(); 930 #endif 931 932 /* Clear ITC to eliminate sched_clock() overflows in human time. */ 933 ia64_set_itc(0); 934 935 /* disable all local interrupt sources: */ 936 ia64_set_itv(1 << 16); 937 ia64_set_lrr0(1 << 16); 938 ia64_set_lrr1(1 << 16); 939 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16); 940 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16); 941 942 /* clear TPR & XTP to enable all interrupt classes: */ 943 ia64_setreg(_IA64_REG_CR_TPR, 0); 944 945 /* Clear any pending interrupts left by SAL/EFI */ 946 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR) 947 ia64_eoi(); 948 949 #ifdef CONFIG_SMP 950 normal_xtp(); 951 #endif 952 953 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */ 954 if (ia64_pal_vm_summary(NULL, &vmi) == 0) 955 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1; 956 else { 957 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n"); 958 max_ctx = (1U << 15) - 1; /* use architected minimum */ 959 } 960 while (max_ctx < ia64_ctx.max_ctx) { 961 unsigned int old = ia64_ctx.max_ctx; 962 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old) 963 break; 964 } 965 966 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) { 967 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical " 968 "stacked regs\n"); 969 num_phys_stacked = 96; 970 } 971 /* size of physical stacked register partition plus 8 bytes: */ 972 if (num_phys_stacked > max_num_phys_stacked) { 973 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8); 974 max_num_phys_stacked = num_phys_stacked; 975 } 976 platform_cpu_init(); 977 pm_idle = default_idle; 978 } 979 980 void __init 981 check_bugs (void) 982 { 983 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, 984 (unsigned long) __end___mckinley_e9_bundles); 985 } 986 987 static int __init run_dmi_scan(void) 988 { 989 dmi_scan_machine(); 990 return 0; 991 } 992 core_initcall(run_dmi_scan); 993