1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * This file contains the Itanium PMU register description tables
4*1f4e74c0SViresh Kumar * and pmc checker.
51da177e4SLinus Torvalds *
61da177e4SLinus Torvalds * Copyright (C) 2002-2003 Hewlett Packard Co
71da177e4SLinus Torvalds * Stephane Eranian <eranian@hpl.hp.com>
81da177e4SLinus Torvalds */
91da177e4SLinus Torvalds static int pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
101da177e4SLinus Torvalds
111da177e4SLinus Torvalds static pfm_reg_desc_t pfm_ita_pmc_desc[PMU_MAX_PMCS]={
121da177e4SLinus Torvalds /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
131da177e4SLinus Torvalds /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
141da177e4SLinus Torvalds /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
151da177e4SLinus Torvalds /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
161da177e4SLinus Torvalds /* pmc4 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
171da177e4SLinus Torvalds /* pmc5 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
181da177e4SLinus Torvalds /* pmc6 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
191da177e4SLinus Torvalds /* pmc7 */ { PFM_REG_COUNTING, 6, 0x0UL, -1UL, NULL, NULL, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
201da177e4SLinus Torvalds /* pmc8 */ { PFM_REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
211da177e4SLinus Torvalds /* pmc9 */ { PFM_REG_CONFIG , 0, 0xf00000003ffffff8UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
221da177e4SLinus Torvalds /* pmc10 */ { PFM_REG_MONITOR , 6, 0x0UL, -1UL, NULL, NULL, {RDEP(0)|RDEP(1),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
231da177e4SLinus Torvalds /* pmc11 */ { PFM_REG_MONITOR , 6, 0x0000000010000000UL, -1UL, NULL, pfm_ita_pmc_check, {RDEP(2)|RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
241da177e4SLinus Torvalds /* pmc12 */ { PFM_REG_MONITOR , 6, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
251da177e4SLinus Torvalds /* pmc13 */ { PFM_REG_CONFIG , 0, 0x0003ffff00000001UL, -1UL, NULL, pfm_ita_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
261da177e4SLinus Torvalds { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
271da177e4SLinus Torvalds };
281da177e4SLinus Torvalds
291da177e4SLinus Torvalds static pfm_reg_desc_t pfm_ita_pmd_desc[PMU_MAX_PMDS]={
301da177e4SLinus Torvalds /* pmd0 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(1),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
311da177e4SLinus Torvalds /* pmd1 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(0),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
321da177e4SLinus Torvalds /* pmd2 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
331da177e4SLinus Torvalds /* pmd3 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
341da177e4SLinus Torvalds /* pmd4 */ { PFM_REG_COUNTING, 0, 0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}},
351da177e4SLinus Torvalds /* pmd5 */ { PFM_REG_COUNTING, 0, 0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}},
361da177e4SLinus Torvalds /* pmd6 */ { PFM_REG_COUNTING, 0, 0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}},
371da177e4SLinus Torvalds /* pmd7 */ { PFM_REG_COUNTING, 0, 0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}},
381da177e4SLinus Torvalds /* pmd8 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
391da177e4SLinus Torvalds /* pmd9 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
401da177e4SLinus Torvalds /* pmd10 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
411da177e4SLinus Torvalds /* pmd11 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
421da177e4SLinus Torvalds /* pmd12 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
431da177e4SLinus Torvalds /* pmd13 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
441da177e4SLinus Torvalds /* pmd14 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
451da177e4SLinus Torvalds /* pmd15 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
461da177e4SLinus Torvalds /* pmd16 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
471da177e4SLinus Torvalds /* pmd17 */ { PFM_REG_BUFFER , 0, 0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(3),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
481da177e4SLinus Torvalds { PFM_REG_END , 0, 0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
491da177e4SLinus Torvalds };
501da177e4SLinus Torvalds
511da177e4SLinus Torvalds static int
pfm_ita_pmc_check(struct task_struct * task,pfm_context_t * ctx,unsigned int cnum,unsigned long * val,struct pt_regs * regs)521da177e4SLinus Torvalds pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
531da177e4SLinus Torvalds {
541da177e4SLinus Torvalds int ret;
551da177e4SLinus Torvalds int is_loaded;
561da177e4SLinus Torvalds
571da177e4SLinus Torvalds /* sanitfy check */
581da177e4SLinus Torvalds if (ctx == NULL) return -EINVAL;
591da177e4SLinus Torvalds
601da177e4SLinus Torvalds is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
611da177e4SLinus Torvalds
621da177e4SLinus Torvalds /*
631da177e4SLinus Torvalds * we must clear the (instruction) debug registers if pmc13.ta bit is cleared
641da177e4SLinus Torvalds * before they are written (fl_using_dbreg==0) to avoid picking up stale information.
651da177e4SLinus Torvalds */
661da177e4SLinus Torvalds if (cnum == 13 && is_loaded && ((*val & 0x1) == 0UL) && ctx->ctx_fl_using_dbreg == 0) {
671da177e4SLinus Torvalds
681da177e4SLinus Torvalds DPRINT(("pmc[%d]=0x%lx has active pmc13.ta cleared, clearing ibr\n", cnum, *val));
691da177e4SLinus Torvalds
701da177e4SLinus Torvalds /* don't mix debug with perfmon */
711da177e4SLinus Torvalds if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
721da177e4SLinus Torvalds
731da177e4SLinus Torvalds /*
741da177e4SLinus Torvalds * a count of 0 will mark the debug registers as in use and also
751da177e4SLinus Torvalds * ensure that they are properly cleared.
761da177e4SLinus Torvalds */
771da177e4SLinus Torvalds ret = pfm_write_ibr_dbr(1, ctx, NULL, 0, regs);
781da177e4SLinus Torvalds if (ret) return ret;
791da177e4SLinus Torvalds }
801da177e4SLinus Torvalds
811da177e4SLinus Torvalds /*
821da177e4SLinus Torvalds * we must clear the (data) debug registers if pmc11.pt bit is cleared
831da177e4SLinus Torvalds * before they are written (fl_using_dbreg==0) to avoid picking up stale information.
841da177e4SLinus Torvalds */
851da177e4SLinus Torvalds if (cnum == 11 && is_loaded && ((*val >> 28)& 0x1) == 0 && ctx->ctx_fl_using_dbreg == 0) {
861da177e4SLinus Torvalds
871da177e4SLinus Torvalds DPRINT(("pmc[%d]=0x%lx has active pmc11.pt cleared, clearing dbr\n", cnum, *val));
881da177e4SLinus Torvalds
891da177e4SLinus Torvalds /* don't mix debug with perfmon */
901da177e4SLinus Torvalds if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
911da177e4SLinus Torvalds
921da177e4SLinus Torvalds /*
931da177e4SLinus Torvalds * a count of 0 will mark the debug registers as in use and also
941da177e4SLinus Torvalds * ensure that they are properly cleared.
951da177e4SLinus Torvalds */
961da177e4SLinus Torvalds ret = pfm_write_ibr_dbr(0, ctx, NULL, 0, regs);
971da177e4SLinus Torvalds if (ret) return ret;
981da177e4SLinus Torvalds }
991da177e4SLinus Torvalds return 0;
1001da177e4SLinus Torvalds }
1011da177e4SLinus Torvalds
1021da177e4SLinus Torvalds /*
1031da177e4SLinus Torvalds * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
1041da177e4SLinus Torvalds */
1051da177e4SLinus Torvalds static pmu_config_t pmu_conf_ita={
1061da177e4SLinus Torvalds .pmu_name = "Itanium",
1071da177e4SLinus Torvalds .pmu_family = 0x7,
1081da177e4SLinus Torvalds .ovfl_val = (1UL << 32) - 1,
1091da177e4SLinus Torvalds .pmd_desc = pfm_ita_pmd_desc,
1101da177e4SLinus Torvalds .pmc_desc = pfm_ita_pmc_desc,
1111da177e4SLinus Torvalds .num_ibrs = 8,
1121da177e4SLinus Torvalds .num_dbrs = 8,
1131da177e4SLinus Torvalds .use_rr_dbregs = 1, /* debug register are use for range retrictions */
1141da177e4SLinus Torvalds };
1151da177e4SLinus Torvalds
1161da177e4SLinus Torvalds
117