1 /* 2 * Dynamic DMA mapping support. 3 */ 4 5 #include <linux/types.h> 6 #include <linux/mm.h> 7 #include <linux/string.h> 8 #include <linux/pci.h> 9 #include <linux/module.h> 10 #include <linux/dmar.h> 11 #include <asm/iommu.h> 12 #include <asm/machvec.h> 13 #include <linux/dma-mapping.h> 14 15 #include <asm/system.h> 16 17 #ifdef CONFIG_DMAR 18 19 #include <linux/kernel.h> 20 21 #include <asm/page.h> 22 23 dma_addr_t bad_dma_address __read_mostly; 24 EXPORT_SYMBOL(bad_dma_address); 25 26 static int iommu_sac_force __read_mostly; 27 28 int no_iommu __read_mostly; 29 #ifdef CONFIG_IOMMU_DEBUG 30 int force_iommu __read_mostly = 1; 31 #else 32 int force_iommu __read_mostly; 33 #endif 34 35 /* Dummy device used for NULL arguments (normally ISA). Better would 36 be probably a smaller DMA mask, but this is bug-to-bug compatible 37 to i386. */ 38 struct device fallback_dev = { 39 .init_name = "fallback device", 40 .coherent_dma_mask = DMA_BIT_MASK(32), 41 .dma_mask = &fallback_dev.coherent_dma_mask, 42 }; 43 44 extern struct dma_map_ops intel_dma_ops; 45 46 static int __init pci_iommu_init(void) 47 { 48 if (iommu_detected) 49 intel_iommu_init(); 50 51 return 0; 52 } 53 54 /* Must execute after PCI subsystem */ 55 fs_initcall(pci_iommu_init); 56 57 void pci_iommu_shutdown(void) 58 { 59 return; 60 } 61 62 void __init 63 iommu_dma_init(void) 64 { 65 return; 66 } 67 68 int iommu_dma_supported(struct device *dev, u64 mask) 69 { 70 struct dma_map_ops *ops = platform_dma_get_ops(dev); 71 72 if (ops->dma_supported) 73 return ops->dma_supported(dev, mask); 74 75 /* Copied from i386. Doesn't make much sense, because it will 76 only work for pci_alloc_coherent. 77 The caller just has to use GFP_DMA in this case. */ 78 if (mask < DMA_BIT_MASK(24)) 79 return 0; 80 81 /* Tell the device to use SAC when IOMMU force is on. This 82 allows the driver to use cheaper accesses in some cases. 83 84 Problem with this is that if we overflow the IOMMU area and 85 return DAC as fallback address the device may not handle it 86 correctly. 87 88 As a special case some controllers have a 39bit address 89 mode that is as efficient as 32bit (aic79xx). Don't force 90 SAC for these. Assume all masks <= 40 bits are of this 91 type. Normally this doesn't make any difference, but gives 92 more gentle handling of IOMMU overflow. */ 93 if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) { 94 dev_info(dev, "Force SAC with mask %lx\n", mask); 95 return 0; 96 } 97 98 return 1; 99 } 100 EXPORT_SYMBOL(iommu_dma_supported); 101 102 void __init pci_iommu_alloc(void) 103 { 104 dma_ops = &intel_dma_ops; 105 106 dma_ops->sync_single_for_cpu = machvec_dma_sync_single; 107 dma_ops->sync_sg_for_cpu = machvec_dma_sync_sg; 108 dma_ops->sync_single_for_device = machvec_dma_sync_single; 109 dma_ops->sync_sg_for_device = machvec_dma_sync_sg; 110 dma_ops->dma_supported = iommu_dma_supported; 111 112 /* 113 * The order of these functions is important for 114 * fall-back/fail-over reasons 115 */ 116 detect_intel_iommu(); 117 118 #ifdef CONFIG_SWIOTLB 119 pci_swiotlb_init(); 120 #endif 121 } 122 123 #endif 124