1 #include <linux/config.h> 2 3 #include <asm/cache.h> 4 5 #include "entry.h" 6 7 /* 8 * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves 9 * the minimum state necessary that allows us to turn psr.ic back 10 * on. 11 * 12 * Assumed state upon entry: 13 * psr.ic: off 14 * r31: contains saved predicates (pr) 15 * 16 * Upon exit, the state is as follows: 17 * psr.ic: off 18 * r2 = points to &pt_regs.r16 19 * r8 = contents of ar.ccv 20 * r9 = contents of ar.csd 21 * r10 = contents of ar.ssd 22 * r11 = FPSR_DEFAULT 23 * r12 = kernel sp (kernel virtual address) 24 * r13 = points to current task_struct (kernel virtual address) 25 * p15 = TRUE if psr.i is set in cr.ipsr 26 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15: 27 * preserved 28 * 29 * Note that psr.ic is NOT turned on by this macro. This is so that 30 * we can pass interruption state as arguments to a handler. 31 */ 32 #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \ 33 mov r16=IA64_KR(CURRENT); /* M */ \ 34 mov r27=ar.rsc; /* M */ \ 35 mov r20=r1; /* A */ \ 36 mov r25=ar.unat; /* M */ \ 37 mov r29=cr.ipsr; /* M */ \ 38 mov r26=ar.pfs; /* I */ \ 39 mov r28=cr.iip; /* M */ \ 40 mov r21=ar.fpsr; /* M */ \ 41 COVER; /* B;; (or nothing) */ \ 42 ;; \ 43 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \ 44 ;; \ 45 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \ 46 st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \ 47 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \ 48 /* switch from user to kernel RBS: */ \ 49 ;; \ 50 invala; /* M */ \ 51 SAVE_IFS; \ 52 cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \ 53 ;; \ 54 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ 55 ;; \ 56 (pUStk) mov.m r24=ar.rnat; \ 57 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \ 58 (pKStk) mov r1=sp; /* get sp */ \ 59 ;; \ 60 (pUStk) lfetch.fault.excl.nt1 [r22]; \ 61 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ 62 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \ 63 ;; \ 64 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \ 65 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ 66 ;; \ 67 (pUStk) mov r18=ar.bsp; \ 68 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ 69 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \ 70 adds r16=PT(CR_IPSR),r1; \ 71 ;; \ 72 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \ 73 st8 [r16]=r29; /* save cr.ipsr */ \ 74 ;; \ 75 lfetch.fault.excl.nt1 [r17]; \ 76 tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \ 77 mov r29=b0 \ 78 ;; \ 79 adds r16=PT(R8),r1; /* initialize first base pointer */ \ 80 adds r17=PT(R9),r1; /* initialize second base pointer */ \ 81 (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \ 82 ;; \ 83 .mem.offset 0,0; st8.spill [r16]=r8,16; \ 84 .mem.offset 8,0; st8.spill [r17]=r9,16; \ 85 ;; \ 86 .mem.offset 0,0; st8.spill [r16]=r10,24; \ 87 .mem.offset 8,0; st8.spill [r17]=r11,24; \ 88 ;; \ 89 st8 [r16]=r28,16; /* save cr.iip */ \ 90 st8 [r17]=r30,16; /* save cr.ifs */ \ 91 (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \ 92 mov r8=ar.ccv; \ 93 mov r9=ar.csd; \ 94 mov r10=ar.ssd; \ 95 movl r11=FPSR_DEFAULT; /* L-unit */ \ 96 ;; \ 97 st8 [r16]=r25,16; /* save ar.unat */ \ 98 st8 [r17]=r26,16; /* save ar.pfs */ \ 99 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \ 100 ;; \ 101 st8 [r16]=r27,16; /* save ar.rsc */ \ 102 (pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \ 103 (pKStk) adds r17=16,r17; /* skip over ar_rnat field */ \ 104 ;; /* avoid RAW on r16 & r17 */ \ 105 (pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \ 106 st8 [r17]=r31,16; /* save predicates */ \ 107 (pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \ 108 ;; \ 109 st8 [r16]=r29,16; /* save b0 */ \ 110 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \ 111 cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \ 112 ;; \ 113 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \ 114 .mem.offset 8,0; st8.spill [r17]=r12,16; \ 115 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \ 116 ;; \ 117 .mem.offset 0,0; st8.spill [r16]=r13,16; \ 118 .mem.offset 8,0; st8.spill [r17]=r21,16; /* save ar.fpsr */ \ 119 mov r13=IA64_KR(CURRENT); /* establish `current' */ \ 120 ;; \ 121 .mem.offset 0,0; st8.spill [r16]=r15,16; \ 122 .mem.offset 8,0; st8.spill [r17]=r14,16; \ 123 ;; \ 124 .mem.offset 0,0; st8.spill [r16]=r2,16; \ 125 .mem.offset 8,0; st8.spill [r17]=r3,16; \ 126 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \ 127 ;; \ 128 EXTRA; \ 129 movl r1=__gp; /* establish kernel global pointer */ \ 130 ;; \ 131 bsw.1; /* switch back to bank 1 (must be last in insn group) */ \ 132 ;; 133 134 /* 135 * SAVE_REST saves the remainder of pt_regs (with psr.ic on). 136 * 137 * Assumed state upon entry: 138 * psr.ic: on 139 * r2: points to &pt_regs.r16 140 * r3: points to &pt_regs.r17 141 * r8: contents of ar.ccv 142 * r9: contents of ar.csd 143 * r10: contents of ar.ssd 144 * r11: FPSR_DEFAULT 145 * 146 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST. 147 */ 148 #define SAVE_REST \ 149 .mem.offset 0,0; st8.spill [r2]=r16,16; \ 150 .mem.offset 8,0; st8.spill [r3]=r17,16; \ 151 ;; \ 152 .mem.offset 0,0; st8.spill [r2]=r18,16; \ 153 .mem.offset 8,0; st8.spill [r3]=r19,16; \ 154 ;; \ 155 .mem.offset 0,0; st8.spill [r2]=r20,16; \ 156 .mem.offset 8,0; st8.spill [r3]=r21,16; \ 157 mov r18=b6; \ 158 ;; \ 159 .mem.offset 0,0; st8.spill [r2]=r22,16; \ 160 .mem.offset 8,0; st8.spill [r3]=r23,16; \ 161 mov r19=b7; \ 162 ;; \ 163 .mem.offset 0,0; st8.spill [r2]=r24,16; \ 164 .mem.offset 8,0; st8.spill [r3]=r25,16; \ 165 ;; \ 166 .mem.offset 0,0; st8.spill [r2]=r26,16; \ 167 .mem.offset 8,0; st8.spill [r3]=r27,16; \ 168 ;; \ 169 .mem.offset 0,0; st8.spill [r2]=r28,16; \ 170 .mem.offset 8,0; st8.spill [r3]=r29,16; \ 171 ;; \ 172 .mem.offset 0,0; st8.spill [r2]=r30,16; \ 173 .mem.offset 8,0; st8.spill [r3]=r31,32; \ 174 ;; \ 175 mov ar.fpsr=r11; /* M-unit */ \ 176 st8 [r2]=r8,8; /* ar.ccv */ \ 177 adds r24=PT(B6)-PT(F7),r3; \ 178 ;; \ 179 stf.spill [r2]=f6,32; \ 180 stf.spill [r3]=f7,32; \ 181 ;; \ 182 stf.spill [r2]=f8,32; \ 183 stf.spill [r3]=f9,32; \ 184 ;; \ 185 stf.spill [r2]=f10; \ 186 stf.spill [r3]=f11; \ 187 adds r25=PT(B7)-PT(F11),r3; \ 188 ;; \ 189 st8 [r24]=r18,16; /* b6 */ \ 190 st8 [r25]=r19,16; /* b7 */ \ 191 ;; \ 192 st8 [r24]=r9; /* ar.csd */ \ 193 st8 [r25]=r10; /* ar.ssd */ \ 194 ;; 195 196 #define SAVE_MIN_WITH_COVER DO_SAVE_MIN(cover, mov r30=cr.ifs,) 197 #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19) 198 #define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, ) 199