1 /* 2 * File: mca.c 3 * Purpose: Generic MCA handling layer 4 * 5 * Updated for latest kernel 6 * Copyright (C) 2003 Hewlett-Packard Co 7 * David Mosberger-Tang <davidm@hpl.hp.com> 8 * 9 * Copyright (C) 2002 Dell Inc. 10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com) 11 * 12 * Copyright (C) 2002 Intel 13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com) 14 * 15 * Copyright (C) 2001 Intel 16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com) 17 * 18 * Copyright (C) 2000 Intel 19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com) 20 * 21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc. 22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com) 23 * 24 * 03/04/15 D. Mosberger Added INIT backtrace support. 25 * 02/03/25 M. Domsch GUID cleanups 26 * 27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU 28 * error flag, set SAL default return values, changed 29 * error record structure to linked list, added init call 30 * to sal_get_state_info_size(). 31 * 32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected 33 * platform errors, completed code for logging of 34 * corrected & uncorrected machine check errors, and 35 * updated for conformance with Nov. 2000 revision of the 36 * SAL 3.0 spec. 37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues, 38 * added min save state dump, added INIT handler. 39 * 40 * 2003-12-08 Keith Owens <kaos@sgi.com> 41 * smp_call_function() must not be called from interrupt context (can 42 * deadlock on tasklist_lock). Use keventd to call smp_call_function(). 43 * 44 * 2004-02-01 Keith Owens <kaos@sgi.com> 45 * Avoid deadlock when using printk() for MCA and INIT records. 46 * Delete all record printing code, moved to salinfo_decode in user space. 47 * Mark variables and functions static where possible. 48 * Delete dead variables and functions. 49 * Reorder to remove the need for forward declarations and to consolidate 50 * related code. 51 * 52 * 2005-08-12 Keith Owens <kaos@sgi.com> 53 * Convert MCA/INIT handlers to use per event stacks and SAL/OS state. 54 * 55 * 2005-10-07 Keith Owens <kaos@sgi.com> 56 * Add notify_die() hooks. 57 * 58 * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> 59 * Add printing support for MCA/INIT. 60 */ 61 #include <linux/types.h> 62 #include <linux/init.h> 63 #include <linux/sched.h> 64 #include <linux/interrupt.h> 65 #include <linux/irq.h> 66 #include <linux/bootmem.h> 67 #include <linux/acpi.h> 68 #include <linux/timer.h> 69 #include <linux/module.h> 70 #include <linux/kernel.h> 71 #include <linux/smp.h> 72 #include <linux/workqueue.h> 73 #include <linux/cpumask.h> 74 #include <linux/kdebug.h> 75 76 #include <asm/delay.h> 77 #include <asm/machvec.h> 78 #include <asm/meminit.h> 79 #include <asm/page.h> 80 #include <asm/ptrace.h> 81 #include <asm/system.h> 82 #include <asm/sal.h> 83 #include <asm/mca.h> 84 #include <asm/kexec.h> 85 86 #include <asm/irq.h> 87 #include <asm/hw_irq.h> 88 89 #include "mca_drv.h" 90 #include "entry.h" 91 92 #if defined(IA64_MCA_DEBUG_INFO) 93 # define IA64_MCA_DEBUG(fmt...) printk(fmt) 94 #else 95 # define IA64_MCA_DEBUG(fmt...) 96 #endif 97 98 /* Used by mca_asm.S */ 99 u32 ia64_mca_serialize; 100 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */ 101 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */ 102 DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */ 103 DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */ 104 105 unsigned long __per_cpu_mca[NR_CPUS]; 106 107 /* In mca_asm.S */ 108 extern void ia64_os_init_dispatch_monarch (void); 109 extern void ia64_os_init_dispatch_slave (void); 110 111 static int monarch_cpu = -1; 112 113 static ia64_mc_info_t ia64_mc_info; 114 115 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */ 116 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */ 117 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */ 118 #define CPE_HISTORY_LENGTH 5 119 #define CMC_HISTORY_LENGTH 5 120 121 #ifdef CONFIG_ACPI 122 static struct timer_list cpe_poll_timer; 123 #endif 124 static struct timer_list cmc_poll_timer; 125 /* 126 * This variable tells whether we are currently in polling mode. 127 * Start with this in the wrong state so we won't play w/ timers 128 * before the system is ready. 129 */ 130 static int cmc_polling_enabled = 1; 131 132 /* 133 * Clearing this variable prevents CPE polling from getting activated 134 * in mca_late_init. Use it if your system doesn't provide a CPEI, 135 * but encounters problems retrieving CPE logs. This should only be 136 * necessary for debugging. 137 */ 138 static int cpe_poll_enabled = 1; 139 140 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe); 141 142 static int mca_init __initdata; 143 144 /* 145 * limited & delayed printing support for MCA/INIT handler 146 */ 147 148 #define mprintk(fmt...) ia64_mca_printk(fmt) 149 150 #define MLOGBUF_SIZE (512+256*NR_CPUS) 151 #define MLOGBUF_MSGMAX 256 152 static char mlogbuf[MLOGBUF_SIZE]; 153 static DEFINE_SPINLOCK(mlogbuf_wlock); /* mca context only */ 154 static DEFINE_SPINLOCK(mlogbuf_rlock); /* normal context only */ 155 static unsigned long mlogbuf_start; 156 static unsigned long mlogbuf_end; 157 static unsigned int mlogbuf_finished = 0; 158 static unsigned long mlogbuf_timestamp = 0; 159 160 static int loglevel_save = -1; 161 #define BREAK_LOGLEVEL(__console_loglevel) \ 162 oops_in_progress = 1; \ 163 if (loglevel_save < 0) \ 164 loglevel_save = __console_loglevel; \ 165 __console_loglevel = 15; 166 167 #define RESTORE_LOGLEVEL(__console_loglevel) \ 168 if (loglevel_save >= 0) { \ 169 __console_loglevel = loglevel_save; \ 170 loglevel_save = -1; \ 171 } \ 172 mlogbuf_finished = 0; \ 173 oops_in_progress = 0; 174 175 /* 176 * Push messages into buffer, print them later if not urgent. 177 */ 178 void ia64_mca_printk(const char *fmt, ...) 179 { 180 va_list args; 181 int printed_len; 182 char temp_buf[MLOGBUF_MSGMAX]; 183 char *p; 184 185 va_start(args, fmt); 186 printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args); 187 va_end(args); 188 189 /* Copy the output into mlogbuf */ 190 if (oops_in_progress) { 191 /* mlogbuf was abandoned, use printk directly instead. */ 192 printk(temp_buf); 193 } else { 194 spin_lock(&mlogbuf_wlock); 195 for (p = temp_buf; *p; p++) { 196 unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE; 197 if (next != mlogbuf_start) { 198 mlogbuf[mlogbuf_end] = *p; 199 mlogbuf_end = next; 200 } else { 201 /* buffer full */ 202 break; 203 } 204 } 205 mlogbuf[mlogbuf_end] = '\0'; 206 spin_unlock(&mlogbuf_wlock); 207 } 208 } 209 EXPORT_SYMBOL(ia64_mca_printk); 210 211 /* 212 * Print buffered messages. 213 * NOTE: call this after returning normal context. (ex. from salinfod) 214 */ 215 void ia64_mlogbuf_dump(void) 216 { 217 char temp_buf[MLOGBUF_MSGMAX]; 218 char *p; 219 unsigned long index; 220 unsigned long flags; 221 unsigned int printed_len; 222 223 /* Get output from mlogbuf */ 224 while (mlogbuf_start != mlogbuf_end) { 225 temp_buf[0] = '\0'; 226 p = temp_buf; 227 printed_len = 0; 228 229 spin_lock_irqsave(&mlogbuf_rlock, flags); 230 231 index = mlogbuf_start; 232 while (index != mlogbuf_end) { 233 *p = mlogbuf[index]; 234 index = (index + 1) % MLOGBUF_SIZE; 235 if (!*p) 236 break; 237 p++; 238 if (++printed_len >= MLOGBUF_MSGMAX - 1) 239 break; 240 } 241 *p = '\0'; 242 if (temp_buf[0]) 243 printk(temp_buf); 244 mlogbuf_start = index; 245 246 mlogbuf_timestamp = 0; 247 spin_unlock_irqrestore(&mlogbuf_rlock, flags); 248 } 249 } 250 EXPORT_SYMBOL(ia64_mlogbuf_dump); 251 252 /* 253 * Call this if system is going to down or if immediate flushing messages to 254 * console is required. (ex. recovery was failed, crash dump is going to be 255 * invoked, long-wait rendezvous etc.) 256 * NOTE: this should be called from monarch. 257 */ 258 static void ia64_mlogbuf_finish(int wait) 259 { 260 BREAK_LOGLEVEL(console_loglevel); 261 262 spin_lock_init(&mlogbuf_rlock); 263 ia64_mlogbuf_dump(); 264 printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, " 265 "MCA/INIT might be dodgy or fail.\n"); 266 267 if (!wait) 268 return; 269 270 /* wait for console */ 271 printk("Delaying for 5 seconds...\n"); 272 udelay(5*1000000); 273 274 mlogbuf_finished = 1; 275 } 276 277 /* 278 * Print buffered messages from INIT context. 279 */ 280 static void ia64_mlogbuf_dump_from_init(void) 281 { 282 if (mlogbuf_finished) 283 return; 284 285 if (mlogbuf_timestamp && (mlogbuf_timestamp + 30*HZ > jiffies)) { 286 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT " 287 " and the system seems to be messed up.\n"); 288 ia64_mlogbuf_finish(0); 289 return; 290 } 291 292 if (!spin_trylock(&mlogbuf_rlock)) { 293 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. " 294 "Generated messages other than stack dump will be " 295 "buffered to mlogbuf and will be printed later.\n"); 296 printk(KERN_ERR "INIT: If messages would not printed after " 297 "this INIT, wait 30sec and assert INIT again.\n"); 298 if (!mlogbuf_timestamp) 299 mlogbuf_timestamp = jiffies; 300 return; 301 } 302 spin_unlock(&mlogbuf_rlock); 303 ia64_mlogbuf_dump(); 304 } 305 306 static void inline 307 ia64_mca_spin(const char *func) 308 { 309 if (monarch_cpu == smp_processor_id()) 310 ia64_mlogbuf_finish(0); 311 mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func); 312 while (1) 313 cpu_relax(); 314 } 315 /* 316 * IA64_MCA log support 317 */ 318 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */ 319 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */ 320 321 typedef struct ia64_state_log_s 322 { 323 spinlock_t isl_lock; 324 int isl_index; 325 unsigned long isl_count; 326 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */ 327 } ia64_state_log_t; 328 329 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES]; 330 331 #define IA64_LOG_ALLOCATE(it, size) \ 332 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \ 333 (ia64_err_rec_t *)alloc_bootmem(size); \ 334 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \ 335 (ia64_err_rec_t *)alloc_bootmem(size);} 336 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock) 337 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s) 338 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s) 339 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index 340 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index 341 #define IA64_LOG_INDEX_INC(it) \ 342 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \ 343 ia64_state_log[it].isl_count++;} 344 #define IA64_LOG_INDEX_DEC(it) \ 345 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index 346 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)])) 347 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)])) 348 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count 349 350 /* 351 * ia64_log_init 352 * Reset the OS ia64 log buffer 353 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) 354 * Outputs : None 355 */ 356 static void __init 357 ia64_log_init(int sal_info_type) 358 { 359 u64 max_size = 0; 360 361 IA64_LOG_NEXT_INDEX(sal_info_type) = 0; 362 IA64_LOG_LOCK_INIT(sal_info_type); 363 364 // SAL will tell us the maximum size of any error record of this type 365 max_size = ia64_sal_get_state_info_size(sal_info_type); 366 if (!max_size) 367 /* alloc_bootmem() doesn't like zero-sized allocations! */ 368 return; 369 370 // set up OS data structures to hold error info 371 IA64_LOG_ALLOCATE(sal_info_type, max_size); 372 memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size); 373 memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size); 374 } 375 376 /* 377 * ia64_log_get 378 * 379 * Get the current MCA log from SAL and copy it into the OS log buffer. 380 * 381 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) 382 * irq_safe whether you can use printk at this point 383 * Outputs : size (total record length) 384 * *buffer (ptr to error record) 385 * 386 */ 387 static u64 388 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe) 389 { 390 sal_log_record_header_t *log_buffer; 391 u64 total_len = 0; 392 unsigned long s; 393 394 IA64_LOG_LOCK(sal_info_type); 395 396 /* Get the process state information */ 397 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type); 398 399 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer); 400 401 if (total_len) { 402 IA64_LOG_INDEX_INC(sal_info_type); 403 IA64_LOG_UNLOCK(sal_info_type); 404 if (irq_safe) { 405 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. " 406 "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len); 407 } 408 *buffer = (u8 *) log_buffer; 409 return total_len; 410 } else { 411 IA64_LOG_UNLOCK(sal_info_type); 412 return 0; 413 } 414 } 415 416 /* 417 * ia64_mca_log_sal_error_record 418 * 419 * This function retrieves a specified error record type from SAL 420 * and wakes up any processes waiting for error records. 421 * 422 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE) 423 * FIXME: remove MCA and irq_safe. 424 */ 425 static void 426 ia64_mca_log_sal_error_record(int sal_info_type) 427 { 428 u8 *buffer; 429 sal_log_record_header_t *rh; 430 u64 size; 431 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA; 432 #ifdef IA64_MCA_DEBUG_INFO 433 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" }; 434 #endif 435 436 size = ia64_log_get(sal_info_type, &buffer, irq_safe); 437 if (!size) 438 return; 439 440 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe); 441 442 if (irq_safe) 443 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n", 444 smp_processor_id(), 445 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN"); 446 447 /* Clear logs from corrected errors in case there's no user-level logger */ 448 rh = (sal_log_record_header_t *)buffer; 449 if (rh->severity == sal_log_severity_corrected) 450 ia64_sal_clear_state_info(sal_info_type); 451 } 452 453 /* 454 * search_mca_table 455 * See if the MCA surfaced in an instruction range 456 * that has been tagged as recoverable. 457 * 458 * Inputs 459 * first First address range to check 460 * last Last address range to check 461 * ip Instruction pointer, address we are looking for 462 * 463 * Return value: 464 * 1 on Success (in the table)/ 0 on Failure (not in the table) 465 */ 466 int 467 search_mca_table (const struct mca_table_entry *first, 468 const struct mca_table_entry *last, 469 unsigned long ip) 470 { 471 const struct mca_table_entry *curr; 472 u64 curr_start, curr_end; 473 474 curr = first; 475 while (curr <= last) { 476 curr_start = (u64) &curr->start_addr + curr->start_addr; 477 curr_end = (u64) &curr->end_addr + curr->end_addr; 478 479 if ((ip >= curr_start) && (ip <= curr_end)) { 480 return 1; 481 } 482 curr++; 483 } 484 return 0; 485 } 486 487 /* Given an address, look for it in the mca tables. */ 488 int mca_recover_range(unsigned long addr) 489 { 490 extern struct mca_table_entry __start___mca_table[]; 491 extern struct mca_table_entry __stop___mca_table[]; 492 493 return search_mca_table(__start___mca_table, __stop___mca_table-1, addr); 494 } 495 EXPORT_SYMBOL_GPL(mca_recover_range); 496 497 #ifdef CONFIG_ACPI 498 499 int cpe_vector = -1; 500 int ia64_cpe_irq = -1; 501 502 static irqreturn_t 503 ia64_mca_cpe_int_handler (int cpe_irq, void *arg) 504 { 505 static unsigned long cpe_history[CPE_HISTORY_LENGTH]; 506 static int index; 507 static DEFINE_SPINLOCK(cpe_history_lock); 508 509 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n", 510 __FUNCTION__, cpe_irq, smp_processor_id()); 511 512 /* SAL spec states this should run w/ interrupts enabled */ 513 local_irq_enable(); 514 515 spin_lock(&cpe_history_lock); 516 if (!cpe_poll_enabled && cpe_vector >= 0) { 517 518 int i, count = 1; /* we know 1 happened now */ 519 unsigned long now = jiffies; 520 521 for (i = 0; i < CPE_HISTORY_LENGTH; i++) { 522 if (now - cpe_history[i] <= HZ) 523 count++; 524 } 525 526 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH); 527 if (count >= CPE_HISTORY_LENGTH) { 528 529 cpe_poll_enabled = 1; 530 spin_unlock(&cpe_history_lock); 531 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR)); 532 533 /* 534 * Corrected errors will still be corrected, but 535 * make sure there's a log somewhere that indicates 536 * something is generating more than we can handle. 537 */ 538 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n"); 539 540 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL); 541 542 /* lock already released, get out now */ 543 goto out; 544 } else { 545 cpe_history[index++] = now; 546 if (index == CPE_HISTORY_LENGTH) 547 index = 0; 548 } 549 } 550 spin_unlock(&cpe_history_lock); 551 out: 552 /* Get the CPE error record and log it */ 553 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE); 554 555 return IRQ_HANDLED; 556 } 557 558 #endif /* CONFIG_ACPI */ 559 560 #ifdef CONFIG_ACPI 561 /* 562 * ia64_mca_register_cpev 563 * 564 * Register the corrected platform error vector with SAL. 565 * 566 * Inputs 567 * cpev Corrected Platform Error Vector number 568 * 569 * Outputs 570 * None 571 */ 572 static void __init 573 ia64_mca_register_cpev (int cpev) 574 { 575 /* Register the CPE interrupt vector with SAL */ 576 struct ia64_sal_retval isrv; 577 578 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0); 579 if (isrv.status) { 580 printk(KERN_ERR "Failed to register Corrected Platform " 581 "Error interrupt vector with SAL (status %ld)\n", isrv.status); 582 return; 583 } 584 585 IA64_MCA_DEBUG("%s: corrected platform error " 586 "vector %#x registered\n", __FUNCTION__, cpev); 587 } 588 #endif /* CONFIG_ACPI */ 589 590 /* 591 * ia64_mca_cmc_vector_setup 592 * 593 * Setup the corrected machine check vector register in the processor. 594 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.) 595 * This function is invoked on a per-processor basis. 596 * 597 * Inputs 598 * None 599 * 600 * Outputs 601 * None 602 */ 603 void __cpuinit 604 ia64_mca_cmc_vector_setup (void) 605 { 606 cmcv_reg_t cmcv; 607 608 cmcv.cmcv_regval = 0; 609 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */ 610 cmcv.cmcv_vector = IA64_CMC_VECTOR; 611 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); 612 613 IA64_MCA_DEBUG("%s: CPU %d corrected " 614 "machine check vector %#x registered.\n", 615 __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR); 616 617 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n", 618 __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV)); 619 } 620 621 /* 622 * ia64_mca_cmc_vector_disable 623 * 624 * Mask the corrected machine check vector register in the processor. 625 * This function is invoked on a per-processor basis. 626 * 627 * Inputs 628 * dummy(unused) 629 * 630 * Outputs 631 * None 632 */ 633 static void 634 ia64_mca_cmc_vector_disable (void *dummy) 635 { 636 cmcv_reg_t cmcv; 637 638 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); 639 640 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ 641 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); 642 643 IA64_MCA_DEBUG("%s: CPU %d corrected " 644 "machine check vector %#x disabled.\n", 645 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector); 646 } 647 648 /* 649 * ia64_mca_cmc_vector_enable 650 * 651 * Unmask the corrected machine check vector register in the processor. 652 * This function is invoked on a per-processor basis. 653 * 654 * Inputs 655 * dummy(unused) 656 * 657 * Outputs 658 * None 659 */ 660 static void 661 ia64_mca_cmc_vector_enable (void *dummy) 662 { 663 cmcv_reg_t cmcv; 664 665 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); 666 667 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ 668 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); 669 670 IA64_MCA_DEBUG("%s: CPU %d corrected " 671 "machine check vector %#x enabled.\n", 672 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector); 673 } 674 675 /* 676 * ia64_mca_cmc_vector_disable_keventd 677 * 678 * Called via keventd (smp_call_function() is not safe in interrupt context) to 679 * disable the cmc interrupt vector. 680 */ 681 static void 682 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused) 683 { 684 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0); 685 } 686 687 /* 688 * ia64_mca_cmc_vector_enable_keventd 689 * 690 * Called via keventd (smp_call_function() is not safe in interrupt context) to 691 * enable the cmc interrupt vector. 692 */ 693 static void 694 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused) 695 { 696 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0); 697 } 698 699 /* 700 * ia64_mca_wakeup 701 * 702 * Send an inter-cpu interrupt to wake-up a particular cpu 703 * and mark that cpu to be out of rendez. 704 * 705 * Inputs : cpuid 706 * Outputs : None 707 */ 708 static void 709 ia64_mca_wakeup(int cpu) 710 { 711 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0); 712 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 713 714 } 715 716 /* 717 * ia64_mca_wakeup_all 718 * 719 * Wakeup all the cpus which have rendez'ed previously. 720 * 721 * Inputs : None 722 * Outputs : None 723 */ 724 static void 725 ia64_mca_wakeup_all(void) 726 { 727 int cpu; 728 729 /* Clear the Rendez checkin flag for all cpus */ 730 for_each_online_cpu(cpu) { 731 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE) 732 ia64_mca_wakeup(cpu); 733 } 734 735 } 736 737 /* 738 * ia64_mca_rendez_interrupt_handler 739 * 740 * This is handler used to put slave processors into spinloop 741 * while the monarch processor does the mca handling and later 742 * wake each slave up once the monarch is done. 743 * 744 * Inputs : None 745 * Outputs : None 746 */ 747 static irqreturn_t 748 ia64_mca_rendez_int_handler(int rendez_irq, void *arg) 749 { 750 unsigned long flags; 751 int cpu = smp_processor_id(); 752 struct ia64_mca_notify_die nd = 753 { .sos = NULL, .monarch_cpu = &monarch_cpu }; 754 755 /* Mask all interrupts */ 756 local_irq_save(flags); 757 if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", get_irq_regs(), 758 (long)&nd, 0, 0) == NOTIFY_STOP) 759 ia64_mca_spin(__FUNCTION__); 760 761 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE; 762 /* Register with the SAL monarch that the slave has 763 * reached SAL 764 */ 765 ia64_sal_mc_rendez(); 766 767 if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", get_irq_regs(), 768 (long)&nd, 0, 0) == NOTIFY_STOP) 769 ia64_mca_spin(__FUNCTION__); 770 771 /* Wait for the monarch cpu to exit. */ 772 while (monarch_cpu != -1) 773 cpu_relax(); /* spin until monarch leaves */ 774 775 if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", get_irq_regs(), 776 (long)&nd, 0, 0) == NOTIFY_STOP) 777 ia64_mca_spin(__FUNCTION__); 778 779 /* Enable all interrupts */ 780 local_irq_restore(flags); 781 return IRQ_HANDLED; 782 } 783 784 /* 785 * ia64_mca_wakeup_int_handler 786 * 787 * The interrupt handler for processing the inter-cpu interrupt to the 788 * slave cpu which was spinning in the rendez loop. 789 * Since this spinning is done by turning off the interrupts and 790 * polling on the wakeup-interrupt bit in the IRR, there is 791 * nothing useful to be done in the handler. 792 * 793 * Inputs : wakeup_irq (Wakeup-interrupt bit) 794 * arg (Interrupt handler specific argument) 795 * Outputs : None 796 * 797 */ 798 static irqreturn_t 799 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg) 800 { 801 return IRQ_HANDLED; 802 } 803 804 /* Function pointer for extra MCA recovery */ 805 int (*ia64_mca_ucmc_extension) 806 (void*,struct ia64_sal_os_state*) 807 = NULL; 808 809 int 810 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)) 811 { 812 if (ia64_mca_ucmc_extension) 813 return 1; 814 815 ia64_mca_ucmc_extension = fn; 816 return 0; 817 } 818 819 void 820 ia64_unreg_MCA_extension(void) 821 { 822 if (ia64_mca_ucmc_extension) 823 ia64_mca_ucmc_extension = NULL; 824 } 825 826 EXPORT_SYMBOL(ia64_reg_MCA_extension); 827 EXPORT_SYMBOL(ia64_unreg_MCA_extension); 828 829 830 static inline void 831 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat) 832 { 833 u64 fslot, tslot, nat; 834 *tr = *fr; 835 fslot = ((unsigned long)fr >> 3) & 63; 836 tslot = ((unsigned long)tr >> 3) & 63; 837 *tnat &= ~(1UL << tslot); 838 nat = (fnat >> fslot) & 1; 839 *tnat |= (nat << tslot); 840 } 841 842 /* Change the comm field on the MCA/INT task to include the pid that 843 * was interrupted, it makes for easier debugging. If that pid was 0 844 * (swapper or nested MCA/INIT) then use the start of the previous comm 845 * field suffixed with its cpu. 846 */ 847 848 static void 849 ia64_mca_modify_comm(const struct task_struct *previous_current) 850 { 851 char *p, comm[sizeof(current->comm)]; 852 if (previous_current->pid) 853 snprintf(comm, sizeof(comm), "%s %d", 854 current->comm, previous_current->pid); 855 else { 856 int l; 857 if ((p = strchr(previous_current->comm, ' '))) 858 l = p - previous_current->comm; 859 else 860 l = strlen(previous_current->comm); 861 snprintf(comm, sizeof(comm), "%s %*s %d", 862 current->comm, l, previous_current->comm, 863 task_thread_info(previous_current)->cpu); 864 } 865 memcpy(current->comm, comm, sizeof(current->comm)); 866 } 867 868 /* On entry to this routine, we are running on the per cpu stack, see 869 * mca_asm.h. The original stack has not been touched by this event. Some of 870 * the original stack's registers will be in the RBS on this stack. This stack 871 * also contains a partial pt_regs and switch_stack, the rest of the data is in 872 * PAL minstate. 873 * 874 * The first thing to do is modify the original stack to look like a blocked 875 * task so we can run backtrace on the original task. Also mark the per cpu 876 * stack as current to ensure that we use the correct task state, it also means 877 * that we can do backtrace on the MCA/INIT handler code itself. 878 */ 879 880 static struct task_struct * 881 ia64_mca_modify_original_stack(struct pt_regs *regs, 882 const struct switch_stack *sw, 883 struct ia64_sal_os_state *sos, 884 const char *type) 885 { 886 char *p; 887 ia64_va va; 888 extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */ 889 const pal_min_state_area_t *ms = sos->pal_min_state; 890 struct task_struct *previous_current; 891 struct pt_regs *old_regs; 892 struct switch_stack *old_sw; 893 unsigned size = sizeof(struct pt_regs) + 894 sizeof(struct switch_stack) + 16; 895 u64 *old_bspstore, *old_bsp; 896 u64 *new_bspstore, *new_bsp; 897 u64 old_unat, old_rnat, new_rnat, nat; 898 u64 slots, loadrs = regs->loadrs; 899 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1]; 900 u64 ar_bspstore = regs->ar_bspstore; 901 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16); 902 const u64 *bank; 903 const char *msg; 904 int cpu = smp_processor_id(); 905 906 previous_current = curr_task(cpu); 907 set_curr_task(cpu, current); 908 if ((p = strchr(current->comm, ' '))) 909 *p = '\0'; 910 911 /* Best effort attempt to cope with MCA/INIT delivered while in 912 * physical mode. 913 */ 914 regs->cr_ipsr = ms->pmsa_ipsr; 915 if (ia64_psr(regs)->dt == 0) { 916 va.l = r12; 917 if (va.f.reg == 0) { 918 va.f.reg = 7; 919 r12 = va.l; 920 } 921 va.l = r13; 922 if (va.f.reg == 0) { 923 va.f.reg = 7; 924 r13 = va.l; 925 } 926 } 927 if (ia64_psr(regs)->rt == 0) { 928 va.l = ar_bspstore; 929 if (va.f.reg == 0) { 930 va.f.reg = 7; 931 ar_bspstore = va.l; 932 } 933 va.l = ar_bsp; 934 if (va.f.reg == 0) { 935 va.f.reg = 7; 936 ar_bsp = va.l; 937 } 938 } 939 940 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers 941 * have been copied to the old stack, the old stack may fail the 942 * validation tests below. So ia64_old_stack() must restore the dirty 943 * registers from the new stack. The old and new bspstore probably 944 * have different alignments, so loadrs calculated on the old bsp 945 * cannot be used to restore from the new bsp. Calculate a suitable 946 * loadrs for the new stack and save it in the new pt_regs, where 947 * ia64_old_stack() can get it. 948 */ 949 old_bspstore = (u64 *)ar_bspstore; 950 old_bsp = (u64 *)ar_bsp; 951 slots = ia64_rse_num_regs(old_bspstore, old_bsp); 952 new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET); 953 new_bsp = ia64_rse_skip_regs(new_bspstore, slots); 954 regs->loadrs = (new_bsp - new_bspstore) * 8 << 16; 955 956 /* Verify the previous stack state before we change it */ 957 if (user_mode(regs)) { 958 msg = "occurred in user space"; 959 /* previous_current is guaranteed to be valid when the task was 960 * in user space, so ... 961 */ 962 ia64_mca_modify_comm(previous_current); 963 goto no_mod; 964 } 965 966 if (!mca_recover_range(ms->pmsa_iip)) { 967 if (r13 != sos->prev_IA64_KR_CURRENT) { 968 msg = "inconsistent previous current and r13"; 969 goto no_mod; 970 } 971 if ((r12 - r13) >= KERNEL_STACK_SIZE) { 972 msg = "inconsistent r12 and r13"; 973 goto no_mod; 974 } 975 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) { 976 msg = "inconsistent ar.bspstore and r13"; 977 goto no_mod; 978 } 979 va.p = old_bspstore; 980 if (va.f.reg < 5) { 981 msg = "old_bspstore is in the wrong region"; 982 goto no_mod; 983 } 984 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) { 985 msg = "inconsistent ar.bsp and r13"; 986 goto no_mod; 987 } 988 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8; 989 if (ar_bspstore + size > r12) { 990 msg = "no room for blocked state"; 991 goto no_mod; 992 } 993 } 994 995 ia64_mca_modify_comm(previous_current); 996 997 /* Make the original task look blocked. First stack a struct pt_regs, 998 * describing the state at the time of interrupt. mca_asm.S built a 999 * partial pt_regs, copy it and fill in the blanks using minstate. 1000 */ 1001 p = (char *)r12 - sizeof(*regs); 1002 old_regs = (struct pt_regs *)p; 1003 memcpy(old_regs, regs, sizeof(*regs)); 1004 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use 1005 * pmsa_{xip,xpsr,xfs} 1006 */ 1007 if (ia64_psr(regs)->ic) { 1008 old_regs->cr_iip = ms->pmsa_iip; 1009 old_regs->cr_ipsr = ms->pmsa_ipsr; 1010 old_regs->cr_ifs = ms->pmsa_ifs; 1011 } else { 1012 old_regs->cr_iip = ms->pmsa_xip; 1013 old_regs->cr_ipsr = ms->pmsa_xpsr; 1014 old_regs->cr_ifs = ms->pmsa_xfs; 1015 } 1016 old_regs->pr = ms->pmsa_pr; 1017 old_regs->b0 = ms->pmsa_br0; 1018 old_regs->loadrs = loadrs; 1019 old_regs->ar_rsc = ms->pmsa_rsc; 1020 old_unat = old_regs->ar_unat; 1021 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat); 1022 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat); 1023 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat); 1024 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat); 1025 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat); 1026 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat); 1027 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat); 1028 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat); 1029 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat); 1030 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat); 1031 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat); 1032 if (ia64_psr(old_regs)->bn) 1033 bank = ms->pmsa_bank1_gr; 1034 else 1035 bank = ms->pmsa_bank0_gr; 1036 copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat); 1037 copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat); 1038 copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat); 1039 copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat); 1040 copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat); 1041 copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat); 1042 copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat); 1043 copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat); 1044 copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat); 1045 copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat); 1046 copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat); 1047 copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat); 1048 copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat); 1049 copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat); 1050 copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat); 1051 copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat); 1052 1053 /* Next stack a struct switch_stack. mca_asm.S built a partial 1054 * switch_stack, copy it and fill in the blanks using pt_regs and 1055 * minstate. 1056 * 1057 * In the synthesized switch_stack, b0 points to ia64_leave_kernel, 1058 * ar.pfs is set to 0. 1059 * 1060 * unwind.c::unw_unwind() does special processing for interrupt frames. 1061 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate 1062 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not 1063 * that this is documented, of course. Set PRED_NON_SYSCALL in the 1064 * switch_stack on the original stack so it will unwind correctly when 1065 * unwind.c reads pt_regs. 1066 * 1067 * thread.ksp is updated to point to the synthesized switch_stack. 1068 */ 1069 p -= sizeof(struct switch_stack); 1070 old_sw = (struct switch_stack *)p; 1071 memcpy(old_sw, sw, sizeof(*sw)); 1072 old_sw->caller_unat = old_unat; 1073 old_sw->ar_fpsr = old_regs->ar_fpsr; 1074 copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat); 1075 copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat); 1076 copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat); 1077 copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat); 1078 old_sw->b0 = (u64)ia64_leave_kernel; 1079 old_sw->b1 = ms->pmsa_br1; 1080 old_sw->ar_pfs = 0; 1081 old_sw->ar_unat = old_unat; 1082 old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL); 1083 previous_current->thread.ksp = (u64)p - 16; 1084 1085 /* Finally copy the original stack's registers back to its RBS. 1086 * Registers from ar.bspstore through ar.bsp at the time of the event 1087 * are in the current RBS, copy them back to the original stack. The 1088 * copy must be done register by register because the original bspstore 1089 * and the current one have different alignments, so the saved RNAT 1090 * data occurs at different places. 1091 * 1092 * mca_asm does cover, so the old_bsp already includes all registers at 1093 * the time of MCA/INIT. It also does flushrs, so all registers before 1094 * this function have been written to backing store on the MCA/INIT 1095 * stack. 1096 */ 1097 new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore)); 1098 old_rnat = regs->ar_rnat; 1099 while (slots--) { 1100 if (ia64_rse_is_rnat_slot(new_bspstore)) { 1101 new_rnat = ia64_get_rnat(new_bspstore++); 1102 } 1103 if (ia64_rse_is_rnat_slot(old_bspstore)) { 1104 *old_bspstore++ = old_rnat; 1105 old_rnat = 0; 1106 } 1107 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL; 1108 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore)); 1109 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore)); 1110 *old_bspstore++ = *new_bspstore++; 1111 } 1112 old_sw->ar_bspstore = (unsigned long)old_bspstore; 1113 old_sw->ar_rnat = old_rnat; 1114 1115 sos->prev_task = previous_current; 1116 return previous_current; 1117 1118 no_mod: 1119 printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n", 1120 smp_processor_id(), type, msg); 1121 return previous_current; 1122 } 1123 1124 /* The monarch/slave interaction is based on monarch_cpu and requires that all 1125 * slaves have entered rendezvous before the monarch leaves. If any cpu has 1126 * not entered rendezvous yet then wait a bit. The assumption is that any 1127 * slave that has not rendezvoused after a reasonable time is never going to do 1128 * so. In this context, slave includes cpus that respond to the MCA rendezvous 1129 * interrupt, as well as cpus that receive the INIT slave event. 1130 */ 1131 1132 static void 1133 ia64_wait_for_slaves(int monarch, const char *type) 1134 { 1135 int c, wait = 0, missing = 0; 1136 for_each_online_cpu(c) { 1137 if (c == monarch) 1138 continue; 1139 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) { 1140 udelay(1000); /* short wait first */ 1141 wait = 1; 1142 break; 1143 } 1144 } 1145 if (!wait) 1146 goto all_in; 1147 for_each_online_cpu(c) { 1148 if (c == monarch) 1149 continue; 1150 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) { 1151 udelay(5*1000000); /* wait 5 seconds for slaves (arbitrary) */ 1152 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) 1153 missing = 1; 1154 break; 1155 } 1156 } 1157 if (!missing) 1158 goto all_in; 1159 /* 1160 * Maybe slave(s) dead. Print buffered messages immediately. 1161 */ 1162 ia64_mlogbuf_finish(0); 1163 mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type); 1164 for_each_online_cpu(c) { 1165 if (c == monarch) 1166 continue; 1167 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) 1168 mprintk(" %d", c); 1169 } 1170 mprintk("\n"); 1171 return; 1172 1173 all_in: 1174 mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type); 1175 return; 1176 } 1177 1178 /* 1179 * ia64_mca_handler 1180 * 1181 * This is uncorrectable machine check handler called from OS_MCA 1182 * dispatch code which is in turn called from SAL_CHECK(). 1183 * This is the place where the core of OS MCA handling is done. 1184 * Right now the logs are extracted and displayed in a well-defined 1185 * format. This handler code is supposed to be run only on the 1186 * monarch processor. Once the monarch is done with MCA handling 1187 * further MCA logging is enabled by clearing logs. 1188 * Monarch also has the duty of sending wakeup-IPIs to pull the 1189 * slave processors out of rendezvous spinloop. 1190 */ 1191 void 1192 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw, 1193 struct ia64_sal_os_state *sos) 1194 { 1195 int recover, cpu = smp_processor_id(); 1196 struct task_struct *previous_current; 1197 struct ia64_mca_notify_die nd = 1198 { .sos = sos, .monarch_cpu = &monarch_cpu }; 1199 1200 mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d " 1201 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch); 1202 1203 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA"); 1204 monarch_cpu = cpu; 1205 if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0) 1206 == NOTIFY_STOP) 1207 ia64_mca_spin(__FUNCTION__); 1208 ia64_wait_for_slaves(cpu, "MCA"); 1209 1210 /* Wakeup all the processors which are spinning in the rendezvous loop. 1211 * They will leave SAL, then spin in the OS with interrupts disabled 1212 * until this monarch cpu leaves the MCA handler. That gets control 1213 * back to the OS so we can backtrace the other cpus, backtrace when 1214 * spinning in SAL does not work. 1215 */ 1216 ia64_mca_wakeup_all(); 1217 if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0) 1218 == NOTIFY_STOP) 1219 ia64_mca_spin(__FUNCTION__); 1220 1221 /* Get the MCA error record and log it */ 1222 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA); 1223 1224 /* MCA error recovery */ 1225 recover = (ia64_mca_ucmc_extension 1226 && ia64_mca_ucmc_extension( 1227 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA), 1228 sos)); 1229 1230 if (recover) { 1231 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA); 1232 rh->severity = sal_log_severity_corrected; 1233 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA); 1234 sos->os_status = IA64_MCA_CORRECTED; 1235 } else { 1236 /* Dump buffered message to console */ 1237 ia64_mlogbuf_finish(1); 1238 #ifdef CONFIG_KEXEC 1239 atomic_set(&kdump_in_progress, 1); 1240 monarch_cpu = -1; 1241 #endif 1242 } 1243 if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover) 1244 == NOTIFY_STOP) 1245 ia64_mca_spin(__FUNCTION__); 1246 1247 set_curr_task(cpu, previous_current); 1248 monarch_cpu = -1; 1249 } 1250 1251 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd); 1252 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd); 1253 1254 /* 1255 * ia64_mca_cmc_int_handler 1256 * 1257 * This is corrected machine check interrupt handler. 1258 * Right now the logs are extracted and displayed in a well-defined 1259 * format. 1260 * 1261 * Inputs 1262 * interrupt number 1263 * client data arg ptr 1264 * 1265 * Outputs 1266 * None 1267 */ 1268 static irqreturn_t 1269 ia64_mca_cmc_int_handler(int cmc_irq, void *arg) 1270 { 1271 static unsigned long cmc_history[CMC_HISTORY_LENGTH]; 1272 static int index; 1273 static DEFINE_SPINLOCK(cmc_history_lock); 1274 1275 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n", 1276 __FUNCTION__, cmc_irq, smp_processor_id()); 1277 1278 /* SAL spec states this should run w/ interrupts enabled */ 1279 local_irq_enable(); 1280 1281 spin_lock(&cmc_history_lock); 1282 if (!cmc_polling_enabled) { 1283 int i, count = 1; /* we know 1 happened now */ 1284 unsigned long now = jiffies; 1285 1286 for (i = 0; i < CMC_HISTORY_LENGTH; i++) { 1287 if (now - cmc_history[i] <= HZ) 1288 count++; 1289 } 1290 1291 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH); 1292 if (count >= CMC_HISTORY_LENGTH) { 1293 1294 cmc_polling_enabled = 1; 1295 spin_unlock(&cmc_history_lock); 1296 /* If we're being hit with CMC interrupts, we won't 1297 * ever execute the schedule_work() below. Need to 1298 * disable CMC interrupts on this processor now. 1299 */ 1300 ia64_mca_cmc_vector_disable(NULL); 1301 schedule_work(&cmc_disable_work); 1302 1303 /* 1304 * Corrected errors will still be corrected, but 1305 * make sure there's a log somewhere that indicates 1306 * something is generating more than we can handle. 1307 */ 1308 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n"); 1309 1310 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL); 1311 1312 /* lock already released, get out now */ 1313 goto out; 1314 } else { 1315 cmc_history[index++] = now; 1316 if (index == CMC_HISTORY_LENGTH) 1317 index = 0; 1318 } 1319 } 1320 spin_unlock(&cmc_history_lock); 1321 out: 1322 /* Get the CMC error record and log it */ 1323 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC); 1324 1325 return IRQ_HANDLED; 1326 } 1327 1328 /* 1329 * ia64_mca_cmc_int_caller 1330 * 1331 * Triggered by sw interrupt from CMC polling routine. Calls 1332 * real interrupt handler and either triggers a sw interrupt 1333 * on the next cpu or does cleanup at the end. 1334 * 1335 * Inputs 1336 * interrupt number 1337 * client data arg ptr 1338 * Outputs 1339 * handled 1340 */ 1341 static irqreturn_t 1342 ia64_mca_cmc_int_caller(int cmc_irq, void *arg) 1343 { 1344 static int start_count = -1; 1345 unsigned int cpuid; 1346 1347 cpuid = smp_processor_id(); 1348 1349 /* If first cpu, update count */ 1350 if (start_count == -1) 1351 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC); 1352 1353 ia64_mca_cmc_int_handler(cmc_irq, arg); 1354 1355 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++); 1356 1357 if (cpuid < NR_CPUS) { 1358 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); 1359 } else { 1360 /* If no log record, switch out of polling mode */ 1361 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) { 1362 1363 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n"); 1364 schedule_work(&cmc_enable_work); 1365 cmc_polling_enabled = 0; 1366 1367 } else { 1368 1369 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL); 1370 } 1371 1372 start_count = -1; 1373 } 1374 1375 return IRQ_HANDLED; 1376 } 1377 1378 /* 1379 * ia64_mca_cmc_poll 1380 * 1381 * Poll for Corrected Machine Checks (CMCs) 1382 * 1383 * Inputs : dummy(unused) 1384 * Outputs : None 1385 * 1386 */ 1387 static void 1388 ia64_mca_cmc_poll (unsigned long dummy) 1389 { 1390 /* Trigger a CMC interrupt cascade */ 1391 platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); 1392 } 1393 1394 /* 1395 * ia64_mca_cpe_int_caller 1396 * 1397 * Triggered by sw interrupt from CPE polling routine. Calls 1398 * real interrupt handler and either triggers a sw interrupt 1399 * on the next cpu or does cleanup at the end. 1400 * 1401 * Inputs 1402 * interrupt number 1403 * client data arg ptr 1404 * Outputs 1405 * handled 1406 */ 1407 #ifdef CONFIG_ACPI 1408 1409 static irqreturn_t 1410 ia64_mca_cpe_int_caller(int cpe_irq, void *arg) 1411 { 1412 static int start_count = -1; 1413 static int poll_time = MIN_CPE_POLL_INTERVAL; 1414 unsigned int cpuid; 1415 1416 cpuid = smp_processor_id(); 1417 1418 /* If first cpu, update count */ 1419 if (start_count == -1) 1420 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE); 1421 1422 ia64_mca_cpe_int_handler(cpe_irq, arg); 1423 1424 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++); 1425 1426 if (cpuid < NR_CPUS) { 1427 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); 1428 } else { 1429 /* 1430 * If a log was recorded, increase our polling frequency, 1431 * otherwise, backoff or return to interrupt mode. 1432 */ 1433 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) { 1434 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2); 1435 } else if (cpe_vector < 0) { 1436 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2); 1437 } else { 1438 poll_time = MIN_CPE_POLL_INTERVAL; 1439 1440 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n"); 1441 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR)); 1442 cpe_poll_enabled = 0; 1443 } 1444 1445 if (cpe_poll_enabled) 1446 mod_timer(&cpe_poll_timer, jiffies + poll_time); 1447 start_count = -1; 1448 } 1449 1450 return IRQ_HANDLED; 1451 } 1452 1453 /* 1454 * ia64_mca_cpe_poll 1455 * 1456 * Poll for Corrected Platform Errors (CPEs), trigger interrupt 1457 * on first cpu, from there it will trickle through all the cpus. 1458 * 1459 * Inputs : dummy(unused) 1460 * Outputs : None 1461 * 1462 */ 1463 static void 1464 ia64_mca_cpe_poll (unsigned long dummy) 1465 { 1466 /* Trigger a CPE interrupt cascade */ 1467 platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); 1468 } 1469 1470 #endif /* CONFIG_ACPI */ 1471 1472 static int 1473 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data) 1474 { 1475 int c; 1476 struct task_struct *g, *t; 1477 if (val != DIE_INIT_MONARCH_PROCESS) 1478 return NOTIFY_DONE; 1479 #ifdef CONFIG_KEXEC 1480 if (atomic_read(&kdump_in_progress)) 1481 return NOTIFY_DONE; 1482 #endif 1483 1484 /* 1485 * FIXME: mlogbuf will brim over with INIT stack dumps. 1486 * To enable show_stack from INIT, we use oops_in_progress which should 1487 * be used in real oops. This would cause something wrong after INIT. 1488 */ 1489 BREAK_LOGLEVEL(console_loglevel); 1490 ia64_mlogbuf_dump_from_init(); 1491 1492 printk(KERN_ERR "Processes interrupted by INIT -"); 1493 for_each_online_cpu(c) { 1494 struct ia64_sal_os_state *s; 1495 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET); 1496 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET); 1497 g = s->prev_task; 1498 if (g) { 1499 if (g->pid) 1500 printk(" %d", g->pid); 1501 else 1502 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g); 1503 } 1504 } 1505 printk("\n\n"); 1506 if (read_trylock(&tasklist_lock)) { 1507 do_each_thread (g, t) { 1508 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm); 1509 show_stack(t, NULL); 1510 } while_each_thread (g, t); 1511 read_unlock(&tasklist_lock); 1512 } 1513 /* FIXME: This will not restore zapped printk locks. */ 1514 RESTORE_LOGLEVEL(console_loglevel); 1515 return NOTIFY_DONE; 1516 } 1517 1518 /* 1519 * C portion of the OS INIT handler 1520 * 1521 * Called from ia64_os_init_dispatch 1522 * 1523 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for 1524 * this event. This code is used for both monarch and slave INIT events, see 1525 * sos->monarch. 1526 * 1527 * All INIT events switch to the INIT stack and change the previous process to 1528 * blocked status. If one of the INIT events is the monarch then we are 1529 * probably processing the nmi button/command. Use the monarch cpu to dump all 1530 * the processes. The slave INIT events all spin until the monarch cpu 1531 * returns. We can also get INIT slave events for MCA, in which case the MCA 1532 * process is the monarch. 1533 */ 1534 1535 void 1536 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw, 1537 struct ia64_sal_os_state *sos) 1538 { 1539 static atomic_t slaves; 1540 static atomic_t monarchs; 1541 struct task_struct *previous_current; 1542 int cpu = smp_processor_id(); 1543 struct ia64_mca_notify_die nd = 1544 { .sos = sos, .monarch_cpu = &monarch_cpu }; 1545 1546 (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0); 1547 1548 mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n", 1549 sos->proc_state_param, cpu, sos->monarch); 1550 salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0); 1551 1552 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT"); 1553 sos->os_status = IA64_INIT_RESUME; 1554 1555 /* FIXME: Workaround for broken proms that drive all INIT events as 1556 * slaves. The last slave that enters is promoted to be a monarch. 1557 * Remove this code in September 2006, that gives platforms a year to 1558 * fix their proms and get their customers updated. 1559 */ 1560 if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) { 1561 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n", 1562 __FUNCTION__, cpu); 1563 atomic_dec(&slaves); 1564 sos->monarch = 1; 1565 } 1566 1567 /* FIXME: Workaround for broken proms that drive all INIT events as 1568 * monarchs. Second and subsequent monarchs are demoted to slaves. 1569 * Remove this code in September 2006, that gives platforms a year to 1570 * fix their proms and get their customers updated. 1571 */ 1572 if (sos->monarch && atomic_add_return(1, &monarchs) > 1) { 1573 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n", 1574 __FUNCTION__, cpu); 1575 atomic_dec(&monarchs); 1576 sos->monarch = 0; 1577 } 1578 1579 if (!sos->monarch) { 1580 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT; 1581 while (monarch_cpu == -1) 1582 cpu_relax(); /* spin until monarch enters */ 1583 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0) 1584 == NOTIFY_STOP) 1585 ia64_mca_spin(__FUNCTION__); 1586 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0) 1587 == NOTIFY_STOP) 1588 ia64_mca_spin(__FUNCTION__); 1589 while (monarch_cpu != -1) 1590 cpu_relax(); /* spin until monarch leaves */ 1591 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0) 1592 == NOTIFY_STOP) 1593 ia64_mca_spin(__FUNCTION__); 1594 mprintk("Slave on cpu %d returning to normal service.\n", cpu); 1595 set_curr_task(cpu, previous_current); 1596 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 1597 atomic_dec(&slaves); 1598 return; 1599 } 1600 1601 monarch_cpu = cpu; 1602 if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0) 1603 == NOTIFY_STOP) 1604 ia64_mca_spin(__FUNCTION__); 1605 1606 /* 1607 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be 1608 * generated via the BMC's command-line interface, but since the console is on the 1609 * same serial line, the user will need some time to switch out of the BMC before 1610 * the dump begins. 1611 */ 1612 mprintk("Delaying for 5 seconds...\n"); 1613 udelay(5*1000000); 1614 ia64_wait_for_slaves(cpu, "INIT"); 1615 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through 1616 * to default_monarch_init_process() above and just print all the 1617 * tasks. 1618 */ 1619 if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0) 1620 == NOTIFY_STOP) 1621 ia64_mca_spin(__FUNCTION__); 1622 if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0) 1623 == NOTIFY_STOP) 1624 ia64_mca_spin(__FUNCTION__); 1625 mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu); 1626 atomic_dec(&monarchs); 1627 set_curr_task(cpu, previous_current); 1628 monarch_cpu = -1; 1629 return; 1630 } 1631 1632 static int __init 1633 ia64_mca_disable_cpe_polling(char *str) 1634 { 1635 cpe_poll_enabled = 0; 1636 return 1; 1637 } 1638 1639 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling); 1640 1641 static struct irqaction cmci_irqaction = { 1642 .handler = ia64_mca_cmc_int_handler, 1643 .flags = IRQF_DISABLED, 1644 .name = "cmc_hndlr" 1645 }; 1646 1647 static struct irqaction cmcp_irqaction = { 1648 .handler = ia64_mca_cmc_int_caller, 1649 .flags = IRQF_DISABLED, 1650 .name = "cmc_poll" 1651 }; 1652 1653 static struct irqaction mca_rdzv_irqaction = { 1654 .handler = ia64_mca_rendez_int_handler, 1655 .flags = IRQF_DISABLED, 1656 .name = "mca_rdzv" 1657 }; 1658 1659 static struct irqaction mca_wkup_irqaction = { 1660 .handler = ia64_mca_wakeup_int_handler, 1661 .flags = IRQF_DISABLED, 1662 .name = "mca_wkup" 1663 }; 1664 1665 #ifdef CONFIG_ACPI 1666 static struct irqaction mca_cpe_irqaction = { 1667 .handler = ia64_mca_cpe_int_handler, 1668 .flags = IRQF_DISABLED, 1669 .name = "cpe_hndlr" 1670 }; 1671 1672 static struct irqaction mca_cpep_irqaction = { 1673 .handler = ia64_mca_cpe_int_caller, 1674 .flags = IRQF_DISABLED, 1675 .name = "cpe_poll" 1676 }; 1677 #endif /* CONFIG_ACPI */ 1678 1679 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on 1680 * these stacks can never sleep, they cannot return from the kernel to user 1681 * space, they do not appear in a normal ps listing. So there is no need to 1682 * format most of the fields. 1683 */ 1684 1685 static void __cpuinit 1686 format_mca_init_stack(void *mca_data, unsigned long offset, 1687 const char *type, int cpu) 1688 { 1689 struct task_struct *p = (struct task_struct *)((char *)mca_data + offset); 1690 struct thread_info *ti; 1691 memset(p, 0, KERNEL_STACK_SIZE); 1692 ti = task_thread_info(p); 1693 ti->flags = _TIF_MCA_INIT; 1694 ti->preempt_count = 1; 1695 ti->task = p; 1696 ti->cpu = cpu; 1697 p->stack = ti; 1698 p->state = TASK_UNINTERRUPTIBLE; 1699 cpu_set(cpu, p->cpus_allowed); 1700 INIT_LIST_HEAD(&p->tasks); 1701 p->parent = p->real_parent = p->group_leader = p; 1702 INIT_LIST_HEAD(&p->children); 1703 INIT_LIST_HEAD(&p->sibling); 1704 strncpy(p->comm, type, sizeof(p->comm)-1); 1705 } 1706 1707 /* Do per-CPU MCA-related initialization. */ 1708 1709 void __cpuinit 1710 ia64_mca_cpu_init(void *cpu_data) 1711 { 1712 void *pal_vaddr; 1713 static int first_time = 1; 1714 1715 if (first_time) { 1716 void *mca_data; 1717 int cpu; 1718 1719 first_time = 0; 1720 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu) 1721 * NR_CPUS + KERNEL_STACK_SIZE); 1722 mca_data = (void *)(((unsigned long)mca_data + 1723 KERNEL_STACK_SIZE - 1) & 1724 (-KERNEL_STACK_SIZE)); 1725 for (cpu = 0; cpu < NR_CPUS; cpu++) { 1726 format_mca_init_stack(mca_data, 1727 offsetof(struct ia64_mca_cpu, mca_stack), 1728 "MCA", cpu); 1729 format_mca_init_stack(mca_data, 1730 offsetof(struct ia64_mca_cpu, init_stack), 1731 "INIT", cpu); 1732 __per_cpu_mca[cpu] = __pa(mca_data); 1733 mca_data += sizeof(struct ia64_mca_cpu); 1734 } 1735 } 1736 1737 /* 1738 * The MCA info structure was allocated earlier and its 1739 * physical address saved in __per_cpu_mca[cpu]. Copy that 1740 * address * to ia64_mca_data so we can access it as a per-CPU 1741 * variable. 1742 */ 1743 __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()]; 1744 1745 /* 1746 * Stash away a copy of the PTE needed to map the per-CPU page. 1747 * We may need it during MCA recovery. 1748 */ 1749 __get_cpu_var(ia64_mca_per_cpu_pte) = 1750 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL)); 1751 1752 /* 1753 * Also, stash away a copy of the PAL address and the PTE 1754 * needed to map it. 1755 */ 1756 pal_vaddr = efi_get_pal_addr(); 1757 if (!pal_vaddr) 1758 return; 1759 __get_cpu_var(ia64_mca_pal_base) = 1760 GRANULEROUNDDOWN((unsigned long) pal_vaddr); 1761 __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr), 1762 PAGE_KERNEL)); 1763 } 1764 1765 /* 1766 * ia64_mca_init 1767 * 1768 * Do all the system level mca specific initialization. 1769 * 1770 * 1. Register spinloop and wakeup request interrupt vectors 1771 * 1772 * 2. Register OS_MCA handler entry point 1773 * 1774 * 3. Register OS_INIT handler entry point 1775 * 1776 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS. 1777 * 1778 * Note that this initialization is done very early before some kernel 1779 * services are available. 1780 * 1781 * Inputs : None 1782 * 1783 * Outputs : None 1784 */ 1785 void __init 1786 ia64_mca_init(void) 1787 { 1788 ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch; 1789 ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave; 1790 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch; 1791 int i; 1792 s64 rc; 1793 struct ia64_sal_retval isrv; 1794 u64 timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */ 1795 static struct notifier_block default_init_monarch_nb = { 1796 .notifier_call = default_monarch_init_process, 1797 .priority = 0/* we need to notified last */ 1798 }; 1799 1800 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__); 1801 1802 /* Clear the Rendez checkin flag for all cpus */ 1803 for(i = 0 ; i < NR_CPUS; i++) 1804 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 1805 1806 /* 1807 * Register the rendezvous spinloop and wakeup mechanism with SAL 1808 */ 1809 1810 /* Register the rendezvous interrupt vector with SAL */ 1811 while (1) { 1812 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT, 1813 SAL_MC_PARAM_MECHANISM_INT, 1814 IA64_MCA_RENDEZ_VECTOR, 1815 timeout, 1816 SAL_MC_PARAM_RZ_ALWAYS); 1817 rc = isrv.status; 1818 if (rc == 0) 1819 break; 1820 if (rc == -2) { 1821 printk(KERN_INFO "Increasing MCA rendezvous timeout from " 1822 "%ld to %ld milliseconds\n", timeout, isrv.v0); 1823 timeout = isrv.v0; 1824 (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0); 1825 continue; 1826 } 1827 printk(KERN_ERR "Failed to register rendezvous interrupt " 1828 "with SAL (status %ld)\n", rc); 1829 return; 1830 } 1831 1832 /* Register the wakeup interrupt vector with SAL */ 1833 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP, 1834 SAL_MC_PARAM_MECHANISM_INT, 1835 IA64_MCA_WAKEUP_VECTOR, 1836 0, 0); 1837 rc = isrv.status; 1838 if (rc) { 1839 printk(KERN_ERR "Failed to register wakeup interrupt with SAL " 1840 "(status %ld)\n", rc); 1841 return; 1842 } 1843 1844 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__); 1845 1846 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp); 1847 /* 1848 * XXX - disable SAL checksum by setting size to 0; should be 1849 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch); 1850 */ 1851 ia64_mc_info.imi_mca_handler_size = 0; 1852 1853 /* Register the os mca handler with SAL */ 1854 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA, 1855 ia64_mc_info.imi_mca_handler, 1856 ia64_tpa(mca_hldlr_ptr->gp), 1857 ia64_mc_info.imi_mca_handler_size, 1858 0, 0, 0))) 1859 { 1860 printk(KERN_ERR "Failed to register OS MCA handler with SAL " 1861 "(status %ld)\n", rc); 1862 return; 1863 } 1864 1865 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__, 1866 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp)); 1867 1868 /* 1869 * XXX - disable SAL checksum by setting size to 0, should be 1870 * size of the actual init handler in mca_asm.S. 1871 */ 1872 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp); 1873 ia64_mc_info.imi_monarch_init_handler_size = 0; 1874 ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp); 1875 ia64_mc_info.imi_slave_init_handler_size = 0; 1876 1877 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__, 1878 ia64_mc_info.imi_monarch_init_handler); 1879 1880 /* Register the os init handler with SAL */ 1881 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, 1882 ia64_mc_info.imi_monarch_init_handler, 1883 ia64_tpa(ia64_getreg(_IA64_REG_GP)), 1884 ia64_mc_info.imi_monarch_init_handler_size, 1885 ia64_mc_info.imi_slave_init_handler, 1886 ia64_tpa(ia64_getreg(_IA64_REG_GP)), 1887 ia64_mc_info.imi_slave_init_handler_size))) 1888 { 1889 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL " 1890 "(status %ld)\n", rc); 1891 return; 1892 } 1893 if (register_die_notifier(&default_init_monarch_nb)) { 1894 printk(KERN_ERR "Failed to register default monarch INIT process\n"); 1895 return; 1896 } 1897 1898 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__); 1899 1900 /* 1901 * Configure the CMCI/P vector and handler. Interrupts for CMC are 1902 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c). 1903 */ 1904 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction); 1905 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction); 1906 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */ 1907 1908 /* Setup the MCA rendezvous interrupt vector */ 1909 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction); 1910 1911 /* Setup the MCA wakeup interrupt vector */ 1912 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction); 1913 1914 #ifdef CONFIG_ACPI 1915 /* Setup the CPEI/P handler */ 1916 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction); 1917 #endif 1918 1919 /* Initialize the areas set aside by the OS to buffer the 1920 * platform/processor error states for MCA/INIT/CMC 1921 * handling. 1922 */ 1923 ia64_log_init(SAL_INFO_TYPE_MCA); 1924 ia64_log_init(SAL_INFO_TYPE_INIT); 1925 ia64_log_init(SAL_INFO_TYPE_CMC); 1926 ia64_log_init(SAL_INFO_TYPE_CPE); 1927 1928 mca_init = 1; 1929 printk(KERN_INFO "MCA related initialization done\n"); 1930 } 1931 1932 /* 1933 * ia64_mca_late_init 1934 * 1935 * Opportunity to setup things that require initialization later 1936 * than ia64_mca_init. Setup a timer to poll for CPEs if the 1937 * platform doesn't support an interrupt driven mechanism. 1938 * 1939 * Inputs : None 1940 * Outputs : Status 1941 */ 1942 static int __init 1943 ia64_mca_late_init(void) 1944 { 1945 if (!mca_init) 1946 return 0; 1947 1948 /* Setup the CMCI/P vector and handler */ 1949 init_timer(&cmc_poll_timer); 1950 cmc_poll_timer.function = ia64_mca_cmc_poll; 1951 1952 /* Unmask/enable the vector */ 1953 cmc_polling_enabled = 0; 1954 schedule_work(&cmc_enable_work); 1955 1956 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__); 1957 1958 #ifdef CONFIG_ACPI 1959 /* Setup the CPEI/P vector and handler */ 1960 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI); 1961 init_timer(&cpe_poll_timer); 1962 cpe_poll_timer.function = ia64_mca_cpe_poll; 1963 1964 { 1965 irq_desc_t *desc; 1966 unsigned int irq; 1967 1968 if (cpe_vector >= 0) { 1969 /* If platform supports CPEI, enable the irq. */ 1970 cpe_poll_enabled = 0; 1971 for (irq = 0; irq < NR_IRQS; ++irq) 1972 if (irq_to_vector(irq) == cpe_vector) { 1973 desc = irq_desc + irq; 1974 desc->status |= IRQ_PER_CPU; 1975 setup_irq(irq, &mca_cpe_irqaction); 1976 ia64_cpe_irq = irq; 1977 } 1978 ia64_mca_register_cpev(cpe_vector); 1979 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__); 1980 } else { 1981 /* If platform doesn't support CPEI, get the timer going. */ 1982 if (cpe_poll_enabled) { 1983 ia64_mca_cpe_poll(0UL); 1984 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__); 1985 } 1986 } 1987 } 1988 #endif 1989 1990 return 0; 1991 } 1992 1993 device_initcall(ia64_mca_late_init); 1994