1 /* 2 * File: mca.c 3 * Purpose: Generic MCA handling layer 4 * 5 * Copyright (C) 2003 Hewlett-Packard Co 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * 8 * Copyright (C) 2002 Dell Inc. 9 * Copyright (C) Matt Domsch <Matt_Domsch@dell.com> 10 * 11 * Copyright (C) 2002 Intel 12 * Copyright (C) Jenna Hall <jenna.s.hall@intel.com> 13 * 14 * Copyright (C) 2001 Intel 15 * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com> 16 * 17 * Copyright (C) 2000 Intel 18 * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com> 19 * 20 * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc. 21 * Copyright (C) Vijay Chander <vijay@engr.sgi.com> 22 * 23 * Copyright (C) 2006 FUJITSU LIMITED 24 * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> 25 * 26 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com> 27 * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues, 28 * added min save state dump, added INIT handler. 29 * 30 * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com> 31 * Added setup of CMCI and CPEI IRQs, logging of corrected platform 32 * errors, completed code for logging of corrected & uncorrected 33 * machine check errors, and updated for conformance with Nov. 2000 34 * revision of the SAL 3.0 spec. 35 * 36 * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com> 37 * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag, 38 * set SAL default return values, changed error record structure to 39 * linked list, added init call to sal_get_state_info_size(). 40 * 41 * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com> 42 * GUID cleanups. 43 * 44 * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com> 45 * Added INIT backtrace support. 46 * 47 * 2003-12-08 Keith Owens <kaos@sgi.com> 48 * smp_call_function() must not be called from interrupt context 49 * (can deadlock on tasklist_lock). 50 * Use keventd to call smp_call_function(). 51 * 52 * 2004-02-01 Keith Owens <kaos@sgi.com> 53 * Avoid deadlock when using printk() for MCA and INIT records. 54 * Delete all record printing code, moved to salinfo_decode in user 55 * space. Mark variables and functions static where possible. 56 * Delete dead variables and functions. Reorder to remove the need 57 * for forward declarations and to consolidate related code. 58 * 59 * 2005-08-12 Keith Owens <kaos@sgi.com> 60 * Convert MCA/INIT handlers to use per event stacks and SAL/OS 61 * state. 62 * 63 * 2005-10-07 Keith Owens <kaos@sgi.com> 64 * Add notify_die() hooks. 65 * 66 * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> 67 * Add printing support for MCA/INIT. 68 * 69 * 2007-04-27 Russ Anderson <rja@sgi.com> 70 * Support multiple cpus going through OS_MCA in the same event. 71 */ 72 #include <linux/jiffies.h> 73 #include <linux/types.h> 74 #include <linux/init.h> 75 #include <linux/sched/signal.h> 76 #include <linux/sched/debug.h> 77 #include <linux/sched/task.h> 78 #include <linux/interrupt.h> 79 #include <linux/irq.h> 80 #include <linux/memblock.h> 81 #include <linux/acpi.h> 82 #include <linux/timer.h> 83 #include <linux/module.h> 84 #include <linux/kernel.h> 85 #include <linux/smp.h> 86 #include <linux/workqueue.h> 87 #include <linux/cpumask.h> 88 #include <linux/kdebug.h> 89 #include <linux/cpu.h> 90 #include <linux/gfp.h> 91 92 #include <asm/delay.h> 93 #include <asm/machvec.h> 94 #include <asm/meminit.h> 95 #include <asm/page.h> 96 #include <asm/ptrace.h> 97 #include <asm/sal.h> 98 #include <asm/mca.h> 99 #include <asm/kexec.h> 100 101 #include <asm/irq.h> 102 #include <asm/hw_irq.h> 103 #include <asm/tlb.h> 104 105 #include "mca_drv.h" 106 #include "entry.h" 107 108 #if defined(IA64_MCA_DEBUG_INFO) 109 # define IA64_MCA_DEBUG(fmt...) printk(fmt) 110 #else 111 # define IA64_MCA_DEBUG(fmt...) 112 #endif 113 114 #define NOTIFY_INIT(event, regs, arg, spin) \ 115 do { \ 116 if ((notify_die((event), "INIT", (regs), (arg), 0, 0) \ 117 == NOTIFY_STOP) && ((spin) == 1)) \ 118 ia64_mca_spin(__func__); \ 119 } while (0) 120 121 #define NOTIFY_MCA(event, regs, arg, spin) \ 122 do { \ 123 if ((notify_die((event), "MCA", (regs), (arg), 0, 0) \ 124 == NOTIFY_STOP) && ((spin) == 1)) \ 125 ia64_mca_spin(__func__); \ 126 } while (0) 127 128 /* Used by mca_asm.S */ 129 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */ 130 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */ 131 DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */ 132 DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */ 133 DEFINE_PER_CPU(u64, ia64_mca_tr_reload); /* Flag for TR reload */ 134 135 unsigned long __per_cpu_mca[NR_CPUS]; 136 137 /* In mca_asm.S */ 138 extern void ia64_os_init_dispatch_monarch (void); 139 extern void ia64_os_init_dispatch_slave (void); 140 141 static int monarch_cpu = -1; 142 143 static ia64_mc_info_t ia64_mc_info; 144 145 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */ 146 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */ 147 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */ 148 #define CPE_HISTORY_LENGTH 5 149 #define CMC_HISTORY_LENGTH 5 150 151 #ifdef CONFIG_ACPI 152 static struct timer_list cpe_poll_timer; 153 #endif 154 static struct timer_list cmc_poll_timer; 155 /* 156 * This variable tells whether we are currently in polling mode. 157 * Start with this in the wrong state so we won't play w/ timers 158 * before the system is ready. 159 */ 160 static int cmc_polling_enabled = 1; 161 162 /* 163 * Clearing this variable prevents CPE polling from getting activated 164 * in mca_late_init. Use it if your system doesn't provide a CPEI, 165 * but encounters problems retrieving CPE logs. This should only be 166 * necessary for debugging. 167 */ 168 static int cpe_poll_enabled = 1; 169 170 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe); 171 172 static int mca_init __initdata; 173 174 /* 175 * limited & delayed printing support for MCA/INIT handler 176 */ 177 178 #define mprintk(fmt...) ia64_mca_printk(fmt) 179 180 #define MLOGBUF_SIZE (512+256*NR_CPUS) 181 #define MLOGBUF_MSGMAX 256 182 static char mlogbuf[MLOGBUF_SIZE]; 183 static DEFINE_SPINLOCK(mlogbuf_wlock); /* mca context only */ 184 static DEFINE_SPINLOCK(mlogbuf_rlock); /* normal context only */ 185 static unsigned long mlogbuf_start; 186 static unsigned long mlogbuf_end; 187 static unsigned int mlogbuf_finished = 0; 188 static unsigned long mlogbuf_timestamp = 0; 189 190 static int loglevel_save = -1; 191 #define BREAK_LOGLEVEL(__console_loglevel) \ 192 oops_in_progress = 1; \ 193 if (loglevel_save < 0) \ 194 loglevel_save = __console_loglevel; \ 195 __console_loglevel = 15; 196 197 #define RESTORE_LOGLEVEL(__console_loglevel) \ 198 if (loglevel_save >= 0) { \ 199 __console_loglevel = loglevel_save; \ 200 loglevel_save = -1; \ 201 } \ 202 mlogbuf_finished = 0; \ 203 oops_in_progress = 0; 204 205 /* 206 * Push messages into buffer, print them later if not urgent. 207 */ 208 void ia64_mca_printk(const char *fmt, ...) 209 { 210 va_list args; 211 int printed_len; 212 char temp_buf[MLOGBUF_MSGMAX]; 213 char *p; 214 215 va_start(args, fmt); 216 printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args); 217 va_end(args); 218 219 /* Copy the output into mlogbuf */ 220 if (oops_in_progress) { 221 /* mlogbuf was abandoned, use printk directly instead. */ 222 printk("%s", temp_buf); 223 } else { 224 spin_lock(&mlogbuf_wlock); 225 for (p = temp_buf; *p; p++) { 226 unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE; 227 if (next != mlogbuf_start) { 228 mlogbuf[mlogbuf_end] = *p; 229 mlogbuf_end = next; 230 } else { 231 /* buffer full */ 232 break; 233 } 234 } 235 mlogbuf[mlogbuf_end] = '\0'; 236 spin_unlock(&mlogbuf_wlock); 237 } 238 } 239 EXPORT_SYMBOL(ia64_mca_printk); 240 241 /* 242 * Print buffered messages. 243 * NOTE: call this after returning normal context. (ex. from salinfod) 244 */ 245 void ia64_mlogbuf_dump(void) 246 { 247 char temp_buf[MLOGBUF_MSGMAX]; 248 char *p; 249 unsigned long index; 250 unsigned long flags; 251 unsigned int printed_len; 252 253 /* Get output from mlogbuf */ 254 while (mlogbuf_start != mlogbuf_end) { 255 temp_buf[0] = '\0'; 256 p = temp_buf; 257 printed_len = 0; 258 259 spin_lock_irqsave(&mlogbuf_rlock, flags); 260 261 index = mlogbuf_start; 262 while (index != mlogbuf_end) { 263 *p = mlogbuf[index]; 264 index = (index + 1) % MLOGBUF_SIZE; 265 if (!*p) 266 break; 267 p++; 268 if (++printed_len >= MLOGBUF_MSGMAX - 1) 269 break; 270 } 271 *p = '\0'; 272 if (temp_buf[0]) 273 printk("%s", temp_buf); 274 mlogbuf_start = index; 275 276 mlogbuf_timestamp = 0; 277 spin_unlock_irqrestore(&mlogbuf_rlock, flags); 278 } 279 } 280 EXPORT_SYMBOL(ia64_mlogbuf_dump); 281 282 /* 283 * Call this if system is going to down or if immediate flushing messages to 284 * console is required. (ex. recovery was failed, crash dump is going to be 285 * invoked, long-wait rendezvous etc.) 286 * NOTE: this should be called from monarch. 287 */ 288 static void ia64_mlogbuf_finish(int wait) 289 { 290 BREAK_LOGLEVEL(console_loglevel); 291 292 spin_lock_init(&mlogbuf_rlock); 293 ia64_mlogbuf_dump(); 294 printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, " 295 "MCA/INIT might be dodgy or fail.\n"); 296 297 if (!wait) 298 return; 299 300 /* wait for console */ 301 printk("Delaying for 5 seconds...\n"); 302 udelay(5*1000000); 303 304 mlogbuf_finished = 1; 305 } 306 307 /* 308 * Print buffered messages from INIT context. 309 */ 310 static void ia64_mlogbuf_dump_from_init(void) 311 { 312 if (mlogbuf_finished) 313 return; 314 315 if (mlogbuf_timestamp && 316 time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) { 317 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT " 318 " and the system seems to be messed up.\n"); 319 ia64_mlogbuf_finish(0); 320 return; 321 } 322 323 if (!spin_trylock(&mlogbuf_rlock)) { 324 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. " 325 "Generated messages other than stack dump will be " 326 "buffered to mlogbuf and will be printed later.\n"); 327 printk(KERN_ERR "INIT: If messages would not printed after " 328 "this INIT, wait 30sec and assert INIT again.\n"); 329 if (!mlogbuf_timestamp) 330 mlogbuf_timestamp = jiffies; 331 return; 332 } 333 spin_unlock(&mlogbuf_rlock); 334 ia64_mlogbuf_dump(); 335 } 336 337 static inline void 338 ia64_mca_spin(const char *func) 339 { 340 if (monarch_cpu == smp_processor_id()) 341 ia64_mlogbuf_finish(0); 342 mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func); 343 while (1) 344 cpu_relax(); 345 } 346 /* 347 * IA64_MCA log support 348 */ 349 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */ 350 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */ 351 352 typedef struct ia64_state_log_s 353 { 354 spinlock_t isl_lock; 355 int isl_index; 356 unsigned long isl_count; 357 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */ 358 } ia64_state_log_t; 359 360 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES]; 361 362 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock) 363 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s) 364 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s) 365 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index 366 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index 367 #define IA64_LOG_INDEX_INC(it) \ 368 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \ 369 ia64_state_log[it].isl_count++;} 370 #define IA64_LOG_INDEX_DEC(it) \ 371 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index 372 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)])) 373 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)])) 374 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count 375 376 static inline void ia64_log_allocate(int it, u64 size) 377 { 378 ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = 379 (ia64_err_rec_t *)memblock_alloc(size, SMP_CACHE_BYTES); 380 if (!ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]) 381 panic("%s: Failed to allocate %llu bytes\n", __func__, size); 382 383 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = 384 (ia64_err_rec_t *)memblock_alloc(size, SMP_CACHE_BYTES); 385 if (!ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]) 386 panic("%s: Failed to allocate %llu bytes\n", __func__, size); 387 } 388 389 /* 390 * ia64_log_init 391 * Reset the OS ia64 log buffer 392 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) 393 * Outputs : None 394 */ 395 static void __init 396 ia64_log_init(int sal_info_type) 397 { 398 u64 max_size = 0; 399 400 IA64_LOG_NEXT_INDEX(sal_info_type) = 0; 401 IA64_LOG_LOCK_INIT(sal_info_type); 402 403 // SAL will tell us the maximum size of any error record of this type 404 max_size = ia64_sal_get_state_info_size(sal_info_type); 405 if (!max_size) 406 /* alloc_bootmem() doesn't like zero-sized allocations! */ 407 return; 408 409 // set up OS data structures to hold error info 410 ia64_log_allocate(sal_info_type, max_size); 411 } 412 413 /* 414 * ia64_log_get 415 * 416 * Get the current MCA log from SAL and copy it into the OS log buffer. 417 * 418 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE}) 419 * irq_safe whether you can use printk at this point 420 * Outputs : size (total record length) 421 * *buffer (ptr to error record) 422 * 423 */ 424 static u64 425 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe) 426 { 427 sal_log_record_header_t *log_buffer; 428 u64 total_len = 0; 429 unsigned long s; 430 431 IA64_LOG_LOCK(sal_info_type); 432 433 /* Get the process state information */ 434 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type); 435 436 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer); 437 438 if (total_len) { 439 IA64_LOG_INDEX_INC(sal_info_type); 440 IA64_LOG_UNLOCK(sal_info_type); 441 if (irq_safe) { 442 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n", 443 __func__, sal_info_type, total_len); 444 } 445 *buffer = (u8 *) log_buffer; 446 return total_len; 447 } else { 448 IA64_LOG_UNLOCK(sal_info_type); 449 return 0; 450 } 451 } 452 453 /* 454 * ia64_mca_log_sal_error_record 455 * 456 * This function retrieves a specified error record type from SAL 457 * and wakes up any processes waiting for error records. 458 * 459 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE) 460 * FIXME: remove MCA and irq_safe. 461 */ 462 static void 463 ia64_mca_log_sal_error_record(int sal_info_type) 464 { 465 u8 *buffer; 466 sal_log_record_header_t *rh; 467 u64 size; 468 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA; 469 #ifdef IA64_MCA_DEBUG_INFO 470 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" }; 471 #endif 472 473 size = ia64_log_get(sal_info_type, &buffer, irq_safe); 474 if (!size) 475 return; 476 477 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe); 478 479 if (irq_safe) 480 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n", 481 smp_processor_id(), 482 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN"); 483 484 /* Clear logs from corrected errors in case there's no user-level logger */ 485 rh = (sal_log_record_header_t *)buffer; 486 if (rh->severity == sal_log_severity_corrected) 487 ia64_sal_clear_state_info(sal_info_type); 488 } 489 490 /* 491 * search_mca_table 492 * See if the MCA surfaced in an instruction range 493 * that has been tagged as recoverable. 494 * 495 * Inputs 496 * first First address range to check 497 * last Last address range to check 498 * ip Instruction pointer, address we are looking for 499 * 500 * Return value: 501 * 1 on Success (in the table)/ 0 on Failure (not in the table) 502 */ 503 int 504 search_mca_table (const struct mca_table_entry *first, 505 const struct mca_table_entry *last, 506 unsigned long ip) 507 { 508 const struct mca_table_entry *curr; 509 u64 curr_start, curr_end; 510 511 curr = first; 512 while (curr <= last) { 513 curr_start = (u64) &curr->start_addr + curr->start_addr; 514 curr_end = (u64) &curr->end_addr + curr->end_addr; 515 516 if ((ip >= curr_start) && (ip <= curr_end)) { 517 return 1; 518 } 519 curr++; 520 } 521 return 0; 522 } 523 524 /* Given an address, look for it in the mca tables. */ 525 int mca_recover_range(unsigned long addr) 526 { 527 extern struct mca_table_entry __start___mca_table[]; 528 extern struct mca_table_entry __stop___mca_table[]; 529 530 return search_mca_table(__start___mca_table, __stop___mca_table-1, addr); 531 } 532 EXPORT_SYMBOL_GPL(mca_recover_range); 533 534 #ifdef CONFIG_ACPI 535 536 int cpe_vector = -1; 537 int ia64_cpe_irq = -1; 538 539 static irqreturn_t 540 ia64_mca_cpe_int_handler (int cpe_irq, void *arg) 541 { 542 static unsigned long cpe_history[CPE_HISTORY_LENGTH]; 543 static int index; 544 static DEFINE_SPINLOCK(cpe_history_lock); 545 546 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n", 547 __func__, cpe_irq, smp_processor_id()); 548 549 /* SAL spec states this should run w/ interrupts enabled */ 550 local_irq_enable(); 551 552 spin_lock(&cpe_history_lock); 553 if (!cpe_poll_enabled && cpe_vector >= 0) { 554 555 int i, count = 1; /* we know 1 happened now */ 556 unsigned long now = jiffies; 557 558 for (i = 0; i < CPE_HISTORY_LENGTH; i++) { 559 if (now - cpe_history[i] <= HZ) 560 count++; 561 } 562 563 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH); 564 if (count >= CPE_HISTORY_LENGTH) { 565 566 cpe_poll_enabled = 1; 567 spin_unlock(&cpe_history_lock); 568 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR)); 569 570 /* 571 * Corrected errors will still be corrected, but 572 * make sure there's a log somewhere that indicates 573 * something is generating more than we can handle. 574 */ 575 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n"); 576 577 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL); 578 579 /* lock already released, get out now */ 580 goto out; 581 } else { 582 cpe_history[index++] = now; 583 if (index == CPE_HISTORY_LENGTH) 584 index = 0; 585 } 586 } 587 spin_unlock(&cpe_history_lock); 588 out: 589 /* Get the CPE error record and log it */ 590 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE); 591 592 local_irq_disable(); 593 594 return IRQ_HANDLED; 595 } 596 597 #endif /* CONFIG_ACPI */ 598 599 #ifdef CONFIG_ACPI 600 /* 601 * ia64_mca_register_cpev 602 * 603 * Register the corrected platform error vector with SAL. 604 * 605 * Inputs 606 * cpev Corrected Platform Error Vector number 607 * 608 * Outputs 609 * None 610 */ 611 void 612 ia64_mca_register_cpev (int cpev) 613 { 614 /* Register the CPE interrupt vector with SAL */ 615 struct ia64_sal_retval isrv; 616 617 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0); 618 if (isrv.status) { 619 printk(KERN_ERR "Failed to register Corrected Platform " 620 "Error interrupt vector with SAL (status %ld)\n", isrv.status); 621 return; 622 } 623 624 IA64_MCA_DEBUG("%s: corrected platform error " 625 "vector %#x registered\n", __func__, cpev); 626 } 627 #endif /* CONFIG_ACPI */ 628 629 /* 630 * ia64_mca_cmc_vector_setup 631 * 632 * Setup the corrected machine check vector register in the processor. 633 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.) 634 * This function is invoked on a per-processor basis. 635 * 636 * Inputs 637 * None 638 * 639 * Outputs 640 * None 641 */ 642 void 643 ia64_mca_cmc_vector_setup (void) 644 { 645 cmcv_reg_t cmcv; 646 647 cmcv.cmcv_regval = 0; 648 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */ 649 cmcv.cmcv_vector = IA64_CMC_VECTOR; 650 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); 651 652 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n", 653 __func__, smp_processor_id(), IA64_CMC_VECTOR); 654 655 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n", 656 __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV)); 657 } 658 659 /* 660 * ia64_mca_cmc_vector_disable 661 * 662 * Mask the corrected machine check vector register in the processor. 663 * This function is invoked on a per-processor basis. 664 * 665 * Inputs 666 * dummy(unused) 667 * 668 * Outputs 669 * None 670 */ 671 static void 672 ia64_mca_cmc_vector_disable (void *dummy) 673 { 674 cmcv_reg_t cmcv; 675 676 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); 677 678 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ 679 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); 680 681 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n", 682 __func__, smp_processor_id(), cmcv.cmcv_vector); 683 } 684 685 /* 686 * ia64_mca_cmc_vector_enable 687 * 688 * Unmask the corrected machine check vector register in the processor. 689 * This function is invoked on a per-processor basis. 690 * 691 * Inputs 692 * dummy(unused) 693 * 694 * Outputs 695 * None 696 */ 697 static void 698 ia64_mca_cmc_vector_enable (void *dummy) 699 { 700 cmcv_reg_t cmcv; 701 702 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); 703 704 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ 705 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); 706 707 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n", 708 __func__, smp_processor_id(), cmcv.cmcv_vector); 709 } 710 711 /* 712 * ia64_mca_cmc_vector_disable_keventd 713 * 714 * Called via keventd (smp_call_function() is not safe in interrupt context) to 715 * disable the cmc interrupt vector. 716 */ 717 static void 718 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused) 719 { 720 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0); 721 } 722 723 /* 724 * ia64_mca_cmc_vector_enable_keventd 725 * 726 * Called via keventd (smp_call_function() is not safe in interrupt context) to 727 * enable the cmc interrupt vector. 728 */ 729 static void 730 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused) 731 { 732 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0); 733 } 734 735 /* 736 * ia64_mca_wakeup 737 * 738 * Send an inter-cpu interrupt to wake-up a particular cpu. 739 * 740 * Inputs : cpuid 741 * Outputs : None 742 */ 743 static void 744 ia64_mca_wakeup(int cpu) 745 { 746 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0); 747 } 748 749 /* 750 * ia64_mca_wakeup_all 751 * 752 * Wakeup all the slave cpus which have rendez'ed previously. 753 * 754 * Inputs : None 755 * Outputs : None 756 */ 757 static void 758 ia64_mca_wakeup_all(void) 759 { 760 int cpu; 761 762 /* Clear the Rendez checkin flag for all cpus */ 763 for_each_online_cpu(cpu) { 764 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE) 765 ia64_mca_wakeup(cpu); 766 } 767 768 } 769 770 /* 771 * ia64_mca_rendez_interrupt_handler 772 * 773 * This is handler used to put slave processors into spinloop 774 * while the monarch processor does the mca handling and later 775 * wake each slave up once the monarch is done. The state 776 * IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed 777 * in SAL. The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates 778 * the cpu has come out of OS rendezvous. 779 * 780 * Inputs : None 781 * Outputs : None 782 */ 783 static irqreturn_t 784 ia64_mca_rendez_int_handler(int rendez_irq, void *arg) 785 { 786 unsigned long flags; 787 int cpu = smp_processor_id(); 788 struct ia64_mca_notify_die nd = 789 { .sos = NULL, .monarch_cpu = &monarch_cpu }; 790 791 /* Mask all interrupts */ 792 local_irq_save(flags); 793 794 NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1); 795 796 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE; 797 /* Register with the SAL monarch that the slave has 798 * reached SAL 799 */ 800 ia64_sal_mc_rendez(); 801 802 NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1); 803 804 /* Wait for the monarch cpu to exit. */ 805 while (monarch_cpu != -1) 806 cpu_relax(); /* spin until monarch leaves */ 807 808 NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1); 809 810 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 811 /* Enable all interrupts */ 812 local_irq_restore(flags); 813 return IRQ_HANDLED; 814 } 815 816 /* 817 * ia64_mca_wakeup_int_handler 818 * 819 * The interrupt handler for processing the inter-cpu interrupt to the 820 * slave cpu which was spinning in the rendez loop. 821 * Since this spinning is done by turning off the interrupts and 822 * polling on the wakeup-interrupt bit in the IRR, there is 823 * nothing useful to be done in the handler. 824 * 825 * Inputs : wakeup_irq (Wakeup-interrupt bit) 826 * arg (Interrupt handler specific argument) 827 * Outputs : None 828 * 829 */ 830 static irqreturn_t 831 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg) 832 { 833 return IRQ_HANDLED; 834 } 835 836 /* Function pointer for extra MCA recovery */ 837 int (*ia64_mca_ucmc_extension) 838 (void*,struct ia64_sal_os_state*) 839 = NULL; 840 841 int 842 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)) 843 { 844 if (ia64_mca_ucmc_extension) 845 return 1; 846 847 ia64_mca_ucmc_extension = fn; 848 return 0; 849 } 850 851 void 852 ia64_unreg_MCA_extension(void) 853 { 854 if (ia64_mca_ucmc_extension) 855 ia64_mca_ucmc_extension = NULL; 856 } 857 858 EXPORT_SYMBOL(ia64_reg_MCA_extension); 859 EXPORT_SYMBOL(ia64_unreg_MCA_extension); 860 861 862 static inline void 863 copy_reg(const u64 *fr, u64 fnat, unsigned long *tr, unsigned long *tnat) 864 { 865 u64 fslot, tslot, nat; 866 *tr = *fr; 867 fslot = ((unsigned long)fr >> 3) & 63; 868 tslot = ((unsigned long)tr >> 3) & 63; 869 *tnat &= ~(1UL << tslot); 870 nat = (fnat >> fslot) & 1; 871 *tnat |= (nat << tslot); 872 } 873 874 /* Change the comm field on the MCA/INT task to include the pid that 875 * was interrupted, it makes for easier debugging. If that pid was 0 876 * (swapper or nested MCA/INIT) then use the start of the previous comm 877 * field suffixed with its cpu. 878 */ 879 880 static void 881 ia64_mca_modify_comm(const struct task_struct *previous_current) 882 { 883 char *p, comm[sizeof(current->comm)]; 884 if (previous_current->pid) 885 snprintf(comm, sizeof(comm), "%s %d", 886 current->comm, previous_current->pid); 887 else { 888 int l; 889 if ((p = strchr(previous_current->comm, ' '))) 890 l = p - previous_current->comm; 891 else 892 l = strlen(previous_current->comm); 893 snprintf(comm, sizeof(comm), "%s %*s %d", 894 current->comm, l, previous_current->comm, 895 task_thread_info(previous_current)->cpu); 896 } 897 memcpy(current->comm, comm, sizeof(current->comm)); 898 } 899 900 static void 901 finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos, 902 unsigned long *nat) 903 { 904 const pal_min_state_area_t *ms = sos->pal_min_state; 905 const u64 *bank; 906 907 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use 908 * pmsa_{xip,xpsr,xfs} 909 */ 910 if (ia64_psr(regs)->ic) { 911 regs->cr_iip = ms->pmsa_iip; 912 regs->cr_ipsr = ms->pmsa_ipsr; 913 regs->cr_ifs = ms->pmsa_ifs; 914 } else { 915 regs->cr_iip = ms->pmsa_xip; 916 regs->cr_ipsr = ms->pmsa_xpsr; 917 regs->cr_ifs = ms->pmsa_xfs; 918 919 sos->iip = ms->pmsa_iip; 920 sos->ipsr = ms->pmsa_ipsr; 921 sos->ifs = ms->pmsa_ifs; 922 } 923 regs->pr = ms->pmsa_pr; 924 regs->b0 = ms->pmsa_br0; 925 regs->ar_rsc = ms->pmsa_rsc; 926 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, ®s->r1, nat); 927 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, ®s->r2, nat); 928 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, ®s->r3, nat); 929 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, ®s->r8, nat); 930 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, ®s->r9, nat); 931 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, ®s->r10, nat); 932 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, ®s->r11, nat); 933 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, ®s->r12, nat); 934 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, ®s->r13, nat); 935 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, ®s->r14, nat); 936 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, ®s->r15, nat); 937 if (ia64_psr(regs)->bn) 938 bank = ms->pmsa_bank1_gr; 939 else 940 bank = ms->pmsa_bank0_gr; 941 copy_reg(&bank[16-16], ms->pmsa_nat_bits, ®s->r16, nat); 942 copy_reg(&bank[17-16], ms->pmsa_nat_bits, ®s->r17, nat); 943 copy_reg(&bank[18-16], ms->pmsa_nat_bits, ®s->r18, nat); 944 copy_reg(&bank[19-16], ms->pmsa_nat_bits, ®s->r19, nat); 945 copy_reg(&bank[20-16], ms->pmsa_nat_bits, ®s->r20, nat); 946 copy_reg(&bank[21-16], ms->pmsa_nat_bits, ®s->r21, nat); 947 copy_reg(&bank[22-16], ms->pmsa_nat_bits, ®s->r22, nat); 948 copy_reg(&bank[23-16], ms->pmsa_nat_bits, ®s->r23, nat); 949 copy_reg(&bank[24-16], ms->pmsa_nat_bits, ®s->r24, nat); 950 copy_reg(&bank[25-16], ms->pmsa_nat_bits, ®s->r25, nat); 951 copy_reg(&bank[26-16], ms->pmsa_nat_bits, ®s->r26, nat); 952 copy_reg(&bank[27-16], ms->pmsa_nat_bits, ®s->r27, nat); 953 copy_reg(&bank[28-16], ms->pmsa_nat_bits, ®s->r28, nat); 954 copy_reg(&bank[29-16], ms->pmsa_nat_bits, ®s->r29, nat); 955 copy_reg(&bank[30-16], ms->pmsa_nat_bits, ®s->r30, nat); 956 copy_reg(&bank[31-16], ms->pmsa_nat_bits, ®s->r31, nat); 957 } 958 959 /* On entry to this routine, we are running on the per cpu stack, see 960 * mca_asm.h. The original stack has not been touched by this event. Some of 961 * the original stack's registers will be in the RBS on this stack. This stack 962 * also contains a partial pt_regs and switch_stack, the rest of the data is in 963 * PAL minstate. 964 * 965 * The first thing to do is modify the original stack to look like a blocked 966 * task so we can run backtrace on the original task. Also mark the per cpu 967 * stack as current to ensure that we use the correct task state, it also means 968 * that we can do backtrace on the MCA/INIT handler code itself. 969 */ 970 971 static struct task_struct * 972 ia64_mca_modify_original_stack(struct pt_regs *regs, 973 const struct switch_stack *sw, 974 struct ia64_sal_os_state *sos, 975 const char *type) 976 { 977 char *p; 978 ia64_va va; 979 extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */ 980 const pal_min_state_area_t *ms = sos->pal_min_state; 981 struct task_struct *previous_current; 982 struct pt_regs *old_regs; 983 struct switch_stack *old_sw; 984 unsigned size = sizeof(struct pt_regs) + 985 sizeof(struct switch_stack) + 16; 986 unsigned long *old_bspstore, *old_bsp; 987 unsigned long *new_bspstore, *new_bsp; 988 unsigned long old_unat, old_rnat, new_rnat, nat; 989 u64 slots, loadrs = regs->loadrs; 990 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1]; 991 u64 ar_bspstore = regs->ar_bspstore; 992 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16); 993 const char *msg; 994 int cpu = smp_processor_id(); 995 996 previous_current = curr_task(cpu); 997 ia64_set_curr_task(cpu, current); 998 if ((p = strchr(current->comm, ' '))) 999 *p = '\0'; 1000 1001 /* Best effort attempt to cope with MCA/INIT delivered while in 1002 * physical mode. 1003 */ 1004 regs->cr_ipsr = ms->pmsa_ipsr; 1005 if (ia64_psr(regs)->dt == 0) { 1006 va.l = r12; 1007 if (va.f.reg == 0) { 1008 va.f.reg = 7; 1009 r12 = va.l; 1010 } 1011 va.l = r13; 1012 if (va.f.reg == 0) { 1013 va.f.reg = 7; 1014 r13 = va.l; 1015 } 1016 } 1017 if (ia64_psr(regs)->rt == 0) { 1018 va.l = ar_bspstore; 1019 if (va.f.reg == 0) { 1020 va.f.reg = 7; 1021 ar_bspstore = va.l; 1022 } 1023 va.l = ar_bsp; 1024 if (va.f.reg == 0) { 1025 va.f.reg = 7; 1026 ar_bsp = va.l; 1027 } 1028 } 1029 1030 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers 1031 * have been copied to the old stack, the old stack may fail the 1032 * validation tests below. So ia64_old_stack() must restore the dirty 1033 * registers from the new stack. The old and new bspstore probably 1034 * have different alignments, so loadrs calculated on the old bsp 1035 * cannot be used to restore from the new bsp. Calculate a suitable 1036 * loadrs for the new stack and save it in the new pt_regs, where 1037 * ia64_old_stack() can get it. 1038 */ 1039 old_bspstore = (unsigned long *)ar_bspstore; 1040 old_bsp = (unsigned long *)ar_bsp; 1041 slots = ia64_rse_num_regs(old_bspstore, old_bsp); 1042 new_bspstore = (unsigned long *)((u64)current + IA64_RBS_OFFSET); 1043 new_bsp = ia64_rse_skip_regs(new_bspstore, slots); 1044 regs->loadrs = (new_bsp - new_bspstore) * 8 << 16; 1045 1046 /* Verify the previous stack state before we change it */ 1047 if (user_mode(regs)) { 1048 msg = "occurred in user space"; 1049 /* previous_current is guaranteed to be valid when the task was 1050 * in user space, so ... 1051 */ 1052 ia64_mca_modify_comm(previous_current); 1053 goto no_mod; 1054 } 1055 1056 if (r13 != sos->prev_IA64_KR_CURRENT) { 1057 msg = "inconsistent previous current and r13"; 1058 goto no_mod; 1059 } 1060 1061 if (!mca_recover_range(ms->pmsa_iip)) { 1062 if ((r12 - r13) >= KERNEL_STACK_SIZE) { 1063 msg = "inconsistent r12 and r13"; 1064 goto no_mod; 1065 } 1066 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) { 1067 msg = "inconsistent ar.bspstore and r13"; 1068 goto no_mod; 1069 } 1070 va.p = old_bspstore; 1071 if (va.f.reg < 5) { 1072 msg = "old_bspstore is in the wrong region"; 1073 goto no_mod; 1074 } 1075 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) { 1076 msg = "inconsistent ar.bsp and r13"; 1077 goto no_mod; 1078 } 1079 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8; 1080 if (ar_bspstore + size > r12) { 1081 msg = "no room for blocked state"; 1082 goto no_mod; 1083 } 1084 } 1085 1086 ia64_mca_modify_comm(previous_current); 1087 1088 /* Make the original task look blocked. First stack a struct pt_regs, 1089 * describing the state at the time of interrupt. mca_asm.S built a 1090 * partial pt_regs, copy it and fill in the blanks using minstate. 1091 */ 1092 p = (char *)r12 - sizeof(*regs); 1093 old_regs = (struct pt_regs *)p; 1094 memcpy(old_regs, regs, sizeof(*regs)); 1095 old_regs->loadrs = loadrs; 1096 old_unat = old_regs->ar_unat; 1097 finish_pt_regs(old_regs, sos, &old_unat); 1098 1099 /* Next stack a struct switch_stack. mca_asm.S built a partial 1100 * switch_stack, copy it and fill in the blanks using pt_regs and 1101 * minstate. 1102 * 1103 * In the synthesized switch_stack, b0 points to ia64_leave_kernel, 1104 * ar.pfs is set to 0. 1105 * 1106 * unwind.c::unw_unwind() does special processing for interrupt frames. 1107 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate 1108 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not 1109 * that this is documented, of course. Set PRED_NON_SYSCALL in the 1110 * switch_stack on the original stack so it will unwind correctly when 1111 * unwind.c reads pt_regs. 1112 * 1113 * thread.ksp is updated to point to the synthesized switch_stack. 1114 */ 1115 p -= sizeof(struct switch_stack); 1116 old_sw = (struct switch_stack *)p; 1117 memcpy(old_sw, sw, sizeof(*sw)); 1118 old_sw->caller_unat = old_unat; 1119 old_sw->ar_fpsr = old_regs->ar_fpsr; 1120 copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat); 1121 copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat); 1122 copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat); 1123 copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat); 1124 old_sw->b0 = (u64)ia64_leave_kernel; 1125 old_sw->b1 = ms->pmsa_br1; 1126 old_sw->ar_pfs = 0; 1127 old_sw->ar_unat = old_unat; 1128 old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL); 1129 previous_current->thread.ksp = (u64)p - 16; 1130 1131 /* Finally copy the original stack's registers back to its RBS. 1132 * Registers from ar.bspstore through ar.bsp at the time of the event 1133 * are in the current RBS, copy them back to the original stack. The 1134 * copy must be done register by register because the original bspstore 1135 * and the current one have different alignments, so the saved RNAT 1136 * data occurs at different places. 1137 * 1138 * mca_asm does cover, so the old_bsp already includes all registers at 1139 * the time of MCA/INIT. It also does flushrs, so all registers before 1140 * this function have been written to backing store on the MCA/INIT 1141 * stack. 1142 */ 1143 new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore)); 1144 old_rnat = regs->ar_rnat; 1145 while (slots--) { 1146 if (ia64_rse_is_rnat_slot(new_bspstore)) { 1147 new_rnat = ia64_get_rnat(new_bspstore++); 1148 } 1149 if (ia64_rse_is_rnat_slot(old_bspstore)) { 1150 *old_bspstore++ = old_rnat; 1151 old_rnat = 0; 1152 } 1153 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL; 1154 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore)); 1155 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore)); 1156 *old_bspstore++ = *new_bspstore++; 1157 } 1158 old_sw->ar_bspstore = (unsigned long)old_bspstore; 1159 old_sw->ar_rnat = old_rnat; 1160 1161 sos->prev_task = previous_current; 1162 return previous_current; 1163 1164 no_mod: 1165 mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n", 1166 smp_processor_id(), type, msg); 1167 old_unat = regs->ar_unat; 1168 finish_pt_regs(regs, sos, &old_unat); 1169 return previous_current; 1170 } 1171 1172 /* The monarch/slave interaction is based on monarch_cpu and requires that all 1173 * slaves have entered rendezvous before the monarch leaves. If any cpu has 1174 * not entered rendezvous yet then wait a bit. The assumption is that any 1175 * slave that has not rendezvoused after a reasonable time is never going to do 1176 * so. In this context, slave includes cpus that respond to the MCA rendezvous 1177 * interrupt, as well as cpus that receive the INIT slave event. 1178 */ 1179 1180 static void 1181 ia64_wait_for_slaves(int monarch, const char *type) 1182 { 1183 int c, i , wait; 1184 1185 /* 1186 * wait 5 seconds total for slaves (arbitrary) 1187 */ 1188 for (i = 0; i < 5000; i++) { 1189 wait = 0; 1190 for_each_online_cpu(c) { 1191 if (c == monarch) 1192 continue; 1193 if (ia64_mc_info.imi_rendez_checkin[c] 1194 == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) { 1195 udelay(1000); /* short wait */ 1196 wait = 1; 1197 break; 1198 } 1199 } 1200 if (!wait) 1201 goto all_in; 1202 } 1203 1204 /* 1205 * Maybe slave(s) dead. Print buffered messages immediately. 1206 */ 1207 ia64_mlogbuf_finish(0); 1208 mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type); 1209 for_each_online_cpu(c) { 1210 if (c == monarch) 1211 continue; 1212 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) 1213 mprintk(" %d", c); 1214 } 1215 mprintk("\n"); 1216 return; 1217 1218 all_in: 1219 mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type); 1220 return; 1221 } 1222 1223 /* mca_insert_tr 1224 * 1225 * Switch rid when TR reload and needed! 1226 * iord: 1: itr, 2: itr; 1227 * 1228 */ 1229 static void mca_insert_tr(u64 iord) 1230 { 1231 1232 int i; 1233 u64 old_rr; 1234 struct ia64_tr_entry *p; 1235 unsigned long psr; 1236 int cpu = smp_processor_id(); 1237 1238 if (!ia64_idtrs[cpu]) 1239 return; 1240 1241 psr = ia64_clear_ic(); 1242 for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) { 1243 p = ia64_idtrs[cpu] + (iord - 1) * IA64_TR_ALLOC_MAX; 1244 if (p->pte & 0x1) { 1245 old_rr = ia64_get_rr(p->ifa); 1246 if (old_rr != p->rr) { 1247 ia64_set_rr(p->ifa, p->rr); 1248 ia64_srlz_d(); 1249 } 1250 ia64_ptr(iord, p->ifa, p->itir >> 2); 1251 ia64_srlz_i(); 1252 if (iord & 0x1) { 1253 ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2); 1254 ia64_srlz_i(); 1255 } 1256 if (iord & 0x2) { 1257 ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2); 1258 ia64_srlz_i(); 1259 } 1260 if (old_rr != p->rr) { 1261 ia64_set_rr(p->ifa, old_rr); 1262 ia64_srlz_d(); 1263 } 1264 } 1265 } 1266 ia64_set_psr(psr); 1267 } 1268 1269 /* 1270 * ia64_mca_handler 1271 * 1272 * This is uncorrectable machine check handler called from OS_MCA 1273 * dispatch code which is in turn called from SAL_CHECK(). 1274 * This is the place where the core of OS MCA handling is done. 1275 * Right now the logs are extracted and displayed in a well-defined 1276 * format. This handler code is supposed to be run only on the 1277 * monarch processor. Once the monarch is done with MCA handling 1278 * further MCA logging is enabled by clearing logs. 1279 * Monarch also has the duty of sending wakeup-IPIs to pull the 1280 * slave processors out of rendezvous spinloop. 1281 * 1282 * If multiple processors call into OS_MCA, the first will become 1283 * the monarch. Subsequent cpus will be recorded in the mca_cpu 1284 * bitmask. After the first monarch has processed its MCA, it 1285 * will wake up the next cpu in the mca_cpu bitmask and then go 1286 * into the rendezvous loop. When all processors have serviced 1287 * their MCA, the last monarch frees up the rest of the processors. 1288 */ 1289 void 1290 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw, 1291 struct ia64_sal_os_state *sos) 1292 { 1293 int recover, cpu = smp_processor_id(); 1294 struct task_struct *previous_current; 1295 struct ia64_mca_notify_die nd = 1296 { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover }; 1297 static atomic_t mca_count; 1298 static cpumask_t mca_cpu; 1299 1300 if (atomic_add_return(1, &mca_count) == 1) { 1301 monarch_cpu = cpu; 1302 sos->monarch = 1; 1303 } else { 1304 cpumask_set_cpu(cpu, &mca_cpu); 1305 sos->monarch = 0; 1306 } 1307 mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d " 1308 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch); 1309 1310 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA"); 1311 1312 NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1); 1313 1314 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA; 1315 if (sos->monarch) { 1316 ia64_wait_for_slaves(cpu, "MCA"); 1317 1318 /* Wakeup all the processors which are spinning in the 1319 * rendezvous loop. They will leave SAL, then spin in the OS 1320 * with interrupts disabled until this monarch cpu leaves the 1321 * MCA handler. That gets control back to the OS so we can 1322 * backtrace the other cpus, backtrace when spinning in SAL 1323 * does not work. 1324 */ 1325 ia64_mca_wakeup_all(); 1326 } else { 1327 while (cpumask_test_cpu(cpu, &mca_cpu)) 1328 cpu_relax(); /* spin until monarch wakes us */ 1329 } 1330 1331 NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1); 1332 1333 /* Get the MCA error record and log it */ 1334 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA); 1335 1336 /* MCA error recovery */ 1337 recover = (ia64_mca_ucmc_extension 1338 && ia64_mca_ucmc_extension( 1339 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA), 1340 sos)); 1341 1342 if (recover) { 1343 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA); 1344 rh->severity = sal_log_severity_corrected; 1345 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA); 1346 sos->os_status = IA64_MCA_CORRECTED; 1347 } else { 1348 /* Dump buffered message to console */ 1349 ia64_mlogbuf_finish(1); 1350 } 1351 1352 if (__this_cpu_read(ia64_mca_tr_reload)) { 1353 mca_insert_tr(0x1); /*Reload dynamic itrs*/ 1354 mca_insert_tr(0x2); /*Reload dynamic itrs*/ 1355 } 1356 1357 NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1); 1358 1359 if (atomic_dec_return(&mca_count) > 0) { 1360 int i; 1361 1362 /* wake up the next monarch cpu, 1363 * and put this cpu in the rendez loop. 1364 */ 1365 for_each_online_cpu(i) { 1366 if (cpumask_test_cpu(i, &mca_cpu)) { 1367 monarch_cpu = i; 1368 cpumask_clear_cpu(i, &mca_cpu); /* wake next cpu */ 1369 while (monarch_cpu != -1) 1370 cpu_relax(); /* spin until last cpu leaves */ 1371 ia64_set_curr_task(cpu, previous_current); 1372 ia64_mc_info.imi_rendez_checkin[cpu] 1373 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 1374 return; 1375 } 1376 } 1377 } 1378 ia64_set_curr_task(cpu, previous_current); 1379 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 1380 monarch_cpu = -1; /* This frees the slaves and previous monarchs */ 1381 } 1382 1383 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd); 1384 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd); 1385 1386 /* 1387 * ia64_mca_cmc_int_handler 1388 * 1389 * This is corrected machine check interrupt handler. 1390 * Right now the logs are extracted and displayed in a well-defined 1391 * format. 1392 * 1393 * Inputs 1394 * interrupt number 1395 * client data arg ptr 1396 * 1397 * Outputs 1398 * None 1399 */ 1400 static irqreturn_t 1401 ia64_mca_cmc_int_handler(int cmc_irq, void *arg) 1402 { 1403 static unsigned long cmc_history[CMC_HISTORY_LENGTH]; 1404 static int index; 1405 static DEFINE_SPINLOCK(cmc_history_lock); 1406 1407 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n", 1408 __func__, cmc_irq, smp_processor_id()); 1409 1410 /* SAL spec states this should run w/ interrupts enabled */ 1411 local_irq_enable(); 1412 1413 spin_lock(&cmc_history_lock); 1414 if (!cmc_polling_enabled) { 1415 int i, count = 1; /* we know 1 happened now */ 1416 unsigned long now = jiffies; 1417 1418 for (i = 0; i < CMC_HISTORY_LENGTH; i++) { 1419 if (now - cmc_history[i] <= HZ) 1420 count++; 1421 } 1422 1423 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH); 1424 if (count >= CMC_HISTORY_LENGTH) { 1425 1426 cmc_polling_enabled = 1; 1427 spin_unlock(&cmc_history_lock); 1428 /* If we're being hit with CMC interrupts, we won't 1429 * ever execute the schedule_work() below. Need to 1430 * disable CMC interrupts on this processor now. 1431 */ 1432 ia64_mca_cmc_vector_disable(NULL); 1433 schedule_work(&cmc_disable_work); 1434 1435 /* 1436 * Corrected errors will still be corrected, but 1437 * make sure there's a log somewhere that indicates 1438 * something is generating more than we can handle. 1439 */ 1440 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n"); 1441 1442 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL); 1443 1444 /* lock already released, get out now */ 1445 goto out; 1446 } else { 1447 cmc_history[index++] = now; 1448 if (index == CMC_HISTORY_LENGTH) 1449 index = 0; 1450 } 1451 } 1452 spin_unlock(&cmc_history_lock); 1453 out: 1454 /* Get the CMC error record and log it */ 1455 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC); 1456 1457 local_irq_disable(); 1458 1459 return IRQ_HANDLED; 1460 } 1461 1462 /* 1463 * ia64_mca_cmc_int_caller 1464 * 1465 * Triggered by sw interrupt from CMC polling routine. Calls 1466 * real interrupt handler and either triggers a sw interrupt 1467 * on the next cpu or does cleanup at the end. 1468 * 1469 * Inputs 1470 * interrupt number 1471 * client data arg ptr 1472 * Outputs 1473 * handled 1474 */ 1475 static irqreturn_t 1476 ia64_mca_cmc_int_caller(int cmc_irq, void *arg) 1477 { 1478 static int start_count = -1; 1479 unsigned int cpuid; 1480 1481 cpuid = smp_processor_id(); 1482 1483 /* If first cpu, update count */ 1484 if (start_count == -1) 1485 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC); 1486 1487 ia64_mca_cmc_int_handler(cmc_irq, arg); 1488 1489 cpuid = cpumask_next(cpuid+1, cpu_online_mask); 1490 1491 if (cpuid < nr_cpu_ids) { 1492 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); 1493 } else { 1494 /* If no log record, switch out of polling mode */ 1495 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) { 1496 1497 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n"); 1498 schedule_work(&cmc_enable_work); 1499 cmc_polling_enabled = 0; 1500 1501 } else { 1502 1503 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL); 1504 } 1505 1506 start_count = -1; 1507 } 1508 1509 return IRQ_HANDLED; 1510 } 1511 1512 /* 1513 * ia64_mca_cmc_poll 1514 * 1515 * Poll for Corrected Machine Checks (CMCs) 1516 * 1517 * Inputs : dummy(unused) 1518 * Outputs : None 1519 * 1520 */ 1521 static void 1522 ia64_mca_cmc_poll (struct timer_list *unused) 1523 { 1524 /* Trigger a CMC interrupt cascade */ 1525 platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR, 1526 IA64_IPI_DM_INT, 0); 1527 } 1528 1529 /* 1530 * ia64_mca_cpe_int_caller 1531 * 1532 * Triggered by sw interrupt from CPE polling routine. Calls 1533 * real interrupt handler and either triggers a sw interrupt 1534 * on the next cpu or does cleanup at the end. 1535 * 1536 * Inputs 1537 * interrupt number 1538 * client data arg ptr 1539 * Outputs 1540 * handled 1541 */ 1542 #ifdef CONFIG_ACPI 1543 1544 static irqreturn_t 1545 ia64_mca_cpe_int_caller(int cpe_irq, void *arg) 1546 { 1547 static int start_count = -1; 1548 static int poll_time = MIN_CPE_POLL_INTERVAL; 1549 unsigned int cpuid; 1550 1551 cpuid = smp_processor_id(); 1552 1553 /* If first cpu, update count */ 1554 if (start_count == -1) 1555 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE); 1556 1557 ia64_mca_cpe_int_handler(cpe_irq, arg); 1558 1559 cpuid = cpumask_next(cpuid+1, cpu_online_mask); 1560 1561 if (cpuid < NR_CPUS) { 1562 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); 1563 } else { 1564 /* 1565 * If a log was recorded, increase our polling frequency, 1566 * otherwise, backoff or return to interrupt mode. 1567 */ 1568 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) { 1569 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2); 1570 } else if (cpe_vector < 0) { 1571 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2); 1572 } else { 1573 poll_time = MIN_CPE_POLL_INTERVAL; 1574 1575 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n"); 1576 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR)); 1577 cpe_poll_enabled = 0; 1578 } 1579 1580 if (cpe_poll_enabled) 1581 mod_timer(&cpe_poll_timer, jiffies + poll_time); 1582 start_count = -1; 1583 } 1584 1585 return IRQ_HANDLED; 1586 } 1587 1588 /* 1589 * ia64_mca_cpe_poll 1590 * 1591 * Poll for Corrected Platform Errors (CPEs), trigger interrupt 1592 * on first cpu, from there it will trickle through all the cpus. 1593 * 1594 * Inputs : dummy(unused) 1595 * Outputs : None 1596 * 1597 */ 1598 static void 1599 ia64_mca_cpe_poll (struct timer_list *unused) 1600 { 1601 /* Trigger a CPE interrupt cascade */ 1602 platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR, 1603 IA64_IPI_DM_INT, 0); 1604 } 1605 1606 #endif /* CONFIG_ACPI */ 1607 1608 static int 1609 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data) 1610 { 1611 int c; 1612 struct task_struct *g, *t; 1613 if (val != DIE_INIT_MONARCH_PROCESS) 1614 return NOTIFY_DONE; 1615 #ifdef CONFIG_KEXEC 1616 if (atomic_read(&kdump_in_progress)) 1617 return NOTIFY_DONE; 1618 #endif 1619 1620 /* 1621 * FIXME: mlogbuf will brim over with INIT stack dumps. 1622 * To enable show_stack from INIT, we use oops_in_progress which should 1623 * be used in real oops. This would cause something wrong after INIT. 1624 */ 1625 BREAK_LOGLEVEL(console_loglevel); 1626 ia64_mlogbuf_dump_from_init(); 1627 1628 printk(KERN_ERR "Processes interrupted by INIT -"); 1629 for_each_online_cpu(c) { 1630 struct ia64_sal_os_state *s; 1631 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET); 1632 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET); 1633 g = s->prev_task; 1634 if (g) { 1635 if (g->pid) 1636 printk(" %d", g->pid); 1637 else 1638 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g); 1639 } 1640 } 1641 printk("\n\n"); 1642 if (read_trylock(&tasklist_lock)) { 1643 do_each_thread (g, t) { 1644 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm); 1645 show_stack(t, NULL); 1646 } while_each_thread (g, t); 1647 read_unlock(&tasklist_lock); 1648 } 1649 /* FIXME: This will not restore zapped printk locks. */ 1650 RESTORE_LOGLEVEL(console_loglevel); 1651 return NOTIFY_DONE; 1652 } 1653 1654 /* 1655 * C portion of the OS INIT handler 1656 * 1657 * Called from ia64_os_init_dispatch 1658 * 1659 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for 1660 * this event. This code is used for both monarch and slave INIT events, see 1661 * sos->monarch. 1662 * 1663 * All INIT events switch to the INIT stack and change the previous process to 1664 * blocked status. If one of the INIT events is the monarch then we are 1665 * probably processing the nmi button/command. Use the monarch cpu to dump all 1666 * the processes. The slave INIT events all spin until the monarch cpu 1667 * returns. We can also get INIT slave events for MCA, in which case the MCA 1668 * process is the monarch. 1669 */ 1670 1671 void 1672 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw, 1673 struct ia64_sal_os_state *sos) 1674 { 1675 static atomic_t slaves; 1676 static atomic_t monarchs; 1677 struct task_struct *previous_current; 1678 int cpu = smp_processor_id(); 1679 struct ia64_mca_notify_die nd = 1680 { .sos = sos, .monarch_cpu = &monarch_cpu }; 1681 1682 NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0); 1683 1684 mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n", 1685 sos->proc_state_param, cpu, sos->monarch); 1686 salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0); 1687 1688 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT"); 1689 sos->os_status = IA64_INIT_RESUME; 1690 1691 /* FIXME: Workaround for broken proms that drive all INIT events as 1692 * slaves. The last slave that enters is promoted to be a monarch. 1693 * Remove this code in September 2006, that gives platforms a year to 1694 * fix their proms and get their customers updated. 1695 */ 1696 if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) { 1697 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n", 1698 __func__, cpu); 1699 atomic_dec(&slaves); 1700 sos->monarch = 1; 1701 } 1702 1703 /* FIXME: Workaround for broken proms that drive all INIT events as 1704 * monarchs. Second and subsequent monarchs are demoted to slaves. 1705 * Remove this code in September 2006, that gives platforms a year to 1706 * fix their proms and get their customers updated. 1707 */ 1708 if (sos->monarch && atomic_add_return(1, &monarchs) > 1) { 1709 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n", 1710 __func__, cpu); 1711 atomic_dec(&monarchs); 1712 sos->monarch = 0; 1713 } 1714 1715 if (!sos->monarch) { 1716 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT; 1717 1718 #ifdef CONFIG_KEXEC 1719 while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress)) 1720 udelay(1000); 1721 #else 1722 while (monarch_cpu == -1) 1723 cpu_relax(); /* spin until monarch enters */ 1724 #endif 1725 1726 NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1); 1727 NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1); 1728 1729 #ifdef CONFIG_KEXEC 1730 while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress)) 1731 udelay(1000); 1732 #else 1733 while (monarch_cpu != -1) 1734 cpu_relax(); /* spin until monarch leaves */ 1735 #endif 1736 1737 NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1); 1738 1739 mprintk("Slave on cpu %d returning to normal service.\n", cpu); 1740 ia64_set_curr_task(cpu, previous_current); 1741 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 1742 atomic_dec(&slaves); 1743 return; 1744 } 1745 1746 monarch_cpu = cpu; 1747 NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1); 1748 1749 /* 1750 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be 1751 * generated via the BMC's command-line interface, but since the console is on the 1752 * same serial line, the user will need some time to switch out of the BMC before 1753 * the dump begins. 1754 */ 1755 mprintk("Delaying for 5 seconds...\n"); 1756 udelay(5*1000000); 1757 ia64_wait_for_slaves(cpu, "INIT"); 1758 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through 1759 * to default_monarch_init_process() above and just print all the 1760 * tasks. 1761 */ 1762 NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1); 1763 NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1); 1764 1765 mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu); 1766 atomic_dec(&monarchs); 1767 ia64_set_curr_task(cpu, previous_current); 1768 monarch_cpu = -1; 1769 return; 1770 } 1771 1772 static int __init 1773 ia64_mca_disable_cpe_polling(char *str) 1774 { 1775 cpe_poll_enabled = 0; 1776 return 1; 1777 } 1778 1779 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling); 1780 1781 static struct irqaction cmci_irqaction = { 1782 .handler = ia64_mca_cmc_int_handler, 1783 .name = "cmc_hndlr" 1784 }; 1785 1786 static struct irqaction cmcp_irqaction = { 1787 .handler = ia64_mca_cmc_int_caller, 1788 .name = "cmc_poll" 1789 }; 1790 1791 static struct irqaction mca_rdzv_irqaction = { 1792 .handler = ia64_mca_rendez_int_handler, 1793 .name = "mca_rdzv" 1794 }; 1795 1796 static struct irqaction mca_wkup_irqaction = { 1797 .handler = ia64_mca_wakeup_int_handler, 1798 .name = "mca_wkup" 1799 }; 1800 1801 #ifdef CONFIG_ACPI 1802 static struct irqaction mca_cpe_irqaction = { 1803 .handler = ia64_mca_cpe_int_handler, 1804 .name = "cpe_hndlr" 1805 }; 1806 1807 static struct irqaction mca_cpep_irqaction = { 1808 .handler = ia64_mca_cpe_int_caller, 1809 .name = "cpe_poll" 1810 }; 1811 #endif /* CONFIG_ACPI */ 1812 1813 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on 1814 * these stacks can never sleep, they cannot return from the kernel to user 1815 * space, they do not appear in a normal ps listing. So there is no need to 1816 * format most of the fields. 1817 */ 1818 1819 static void 1820 format_mca_init_stack(void *mca_data, unsigned long offset, 1821 const char *type, int cpu) 1822 { 1823 struct task_struct *p = (struct task_struct *)((char *)mca_data + offset); 1824 struct thread_info *ti; 1825 memset(p, 0, KERNEL_STACK_SIZE); 1826 ti = task_thread_info(p); 1827 ti->flags = _TIF_MCA_INIT; 1828 ti->preempt_count = 1; 1829 ti->task = p; 1830 ti->cpu = cpu; 1831 p->stack = ti; 1832 p->state = TASK_UNINTERRUPTIBLE; 1833 cpumask_set_cpu(cpu, &p->cpus_allowed); 1834 INIT_LIST_HEAD(&p->tasks); 1835 p->parent = p->real_parent = p->group_leader = p; 1836 INIT_LIST_HEAD(&p->children); 1837 INIT_LIST_HEAD(&p->sibling); 1838 strncpy(p->comm, type, sizeof(p->comm)-1); 1839 } 1840 1841 /* Caller prevents this from being called after init */ 1842 static void * __ref mca_bootmem(void) 1843 { 1844 return memblock_alloc(sizeof(struct ia64_mca_cpu), KERNEL_STACK_SIZE); 1845 } 1846 1847 /* Do per-CPU MCA-related initialization. */ 1848 void 1849 ia64_mca_cpu_init(void *cpu_data) 1850 { 1851 void *pal_vaddr; 1852 void *data; 1853 long sz = sizeof(struct ia64_mca_cpu); 1854 int cpu = smp_processor_id(); 1855 static int first_time = 1; 1856 1857 /* 1858 * Structure will already be allocated if cpu has been online, 1859 * then offlined. 1860 */ 1861 if (__per_cpu_mca[cpu]) { 1862 data = __va(__per_cpu_mca[cpu]); 1863 } else { 1864 if (first_time) { 1865 data = mca_bootmem(); 1866 first_time = 0; 1867 } else 1868 data = (void *)__get_free_pages(GFP_KERNEL, 1869 get_order(sz)); 1870 if (!data) 1871 panic("Could not allocate MCA memory for cpu %d\n", 1872 cpu); 1873 } 1874 format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack), 1875 "MCA", cpu); 1876 format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack), 1877 "INIT", cpu); 1878 __this_cpu_write(ia64_mca_data, (__per_cpu_mca[cpu] = __pa(data))); 1879 1880 /* 1881 * Stash away a copy of the PTE needed to map the per-CPU page. 1882 * We may need it during MCA recovery. 1883 */ 1884 __this_cpu_write(ia64_mca_per_cpu_pte, 1885 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL))); 1886 1887 /* 1888 * Also, stash away a copy of the PAL address and the PTE 1889 * needed to map it. 1890 */ 1891 pal_vaddr = efi_get_pal_addr(); 1892 if (!pal_vaddr) 1893 return; 1894 __this_cpu_write(ia64_mca_pal_base, 1895 GRANULEROUNDDOWN((unsigned long) pal_vaddr)); 1896 __this_cpu_write(ia64_mca_pal_pte, pte_val(mk_pte_phys(__pa(pal_vaddr), 1897 PAGE_KERNEL))); 1898 } 1899 1900 static int ia64_mca_cpu_online(unsigned int cpu) 1901 { 1902 unsigned long flags; 1903 1904 local_irq_save(flags); 1905 if (!cmc_polling_enabled) 1906 ia64_mca_cmc_vector_enable(NULL); 1907 local_irq_restore(flags); 1908 return 0; 1909 } 1910 1911 /* 1912 * ia64_mca_init 1913 * 1914 * Do all the system level mca specific initialization. 1915 * 1916 * 1. Register spinloop and wakeup request interrupt vectors 1917 * 1918 * 2. Register OS_MCA handler entry point 1919 * 1920 * 3. Register OS_INIT handler entry point 1921 * 1922 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS. 1923 * 1924 * Note that this initialization is done very early before some kernel 1925 * services are available. 1926 * 1927 * Inputs : None 1928 * 1929 * Outputs : None 1930 */ 1931 void __init 1932 ia64_mca_init(void) 1933 { 1934 ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch; 1935 ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave; 1936 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch; 1937 int i; 1938 long rc; 1939 struct ia64_sal_retval isrv; 1940 unsigned long timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */ 1941 static struct notifier_block default_init_monarch_nb = { 1942 .notifier_call = default_monarch_init_process, 1943 .priority = 0/* we need to notified last */ 1944 }; 1945 1946 IA64_MCA_DEBUG("%s: begin\n", __func__); 1947 1948 /* Clear the Rendez checkin flag for all cpus */ 1949 for(i = 0 ; i < NR_CPUS; i++) 1950 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE; 1951 1952 /* 1953 * Register the rendezvous spinloop and wakeup mechanism with SAL 1954 */ 1955 1956 /* Register the rendezvous interrupt vector with SAL */ 1957 while (1) { 1958 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT, 1959 SAL_MC_PARAM_MECHANISM_INT, 1960 IA64_MCA_RENDEZ_VECTOR, 1961 timeout, 1962 SAL_MC_PARAM_RZ_ALWAYS); 1963 rc = isrv.status; 1964 if (rc == 0) 1965 break; 1966 if (rc == -2) { 1967 printk(KERN_INFO "Increasing MCA rendezvous timeout from " 1968 "%ld to %ld milliseconds\n", timeout, isrv.v0); 1969 timeout = isrv.v0; 1970 NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0); 1971 continue; 1972 } 1973 printk(KERN_ERR "Failed to register rendezvous interrupt " 1974 "with SAL (status %ld)\n", rc); 1975 return; 1976 } 1977 1978 /* Register the wakeup interrupt vector with SAL */ 1979 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP, 1980 SAL_MC_PARAM_MECHANISM_INT, 1981 IA64_MCA_WAKEUP_VECTOR, 1982 0, 0); 1983 rc = isrv.status; 1984 if (rc) { 1985 printk(KERN_ERR "Failed to register wakeup interrupt with SAL " 1986 "(status %ld)\n", rc); 1987 return; 1988 } 1989 1990 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__); 1991 1992 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp); 1993 /* 1994 * XXX - disable SAL checksum by setting size to 0; should be 1995 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch); 1996 */ 1997 ia64_mc_info.imi_mca_handler_size = 0; 1998 1999 /* Register the os mca handler with SAL */ 2000 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA, 2001 ia64_mc_info.imi_mca_handler, 2002 ia64_tpa(mca_hldlr_ptr->gp), 2003 ia64_mc_info.imi_mca_handler_size, 2004 0, 0, 0))) 2005 { 2006 printk(KERN_ERR "Failed to register OS MCA handler with SAL " 2007 "(status %ld)\n", rc); 2008 return; 2009 } 2010 2011 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__, 2012 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp)); 2013 2014 /* 2015 * XXX - disable SAL checksum by setting size to 0, should be 2016 * size of the actual init handler in mca_asm.S. 2017 */ 2018 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp); 2019 ia64_mc_info.imi_monarch_init_handler_size = 0; 2020 ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp); 2021 ia64_mc_info.imi_slave_init_handler_size = 0; 2022 2023 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__, 2024 ia64_mc_info.imi_monarch_init_handler); 2025 2026 /* Register the os init handler with SAL */ 2027 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT, 2028 ia64_mc_info.imi_monarch_init_handler, 2029 ia64_tpa(ia64_getreg(_IA64_REG_GP)), 2030 ia64_mc_info.imi_monarch_init_handler_size, 2031 ia64_mc_info.imi_slave_init_handler, 2032 ia64_tpa(ia64_getreg(_IA64_REG_GP)), 2033 ia64_mc_info.imi_slave_init_handler_size))) 2034 { 2035 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL " 2036 "(status %ld)\n", rc); 2037 return; 2038 } 2039 if (register_die_notifier(&default_init_monarch_nb)) { 2040 printk(KERN_ERR "Failed to register default monarch INIT process\n"); 2041 return; 2042 } 2043 2044 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__); 2045 2046 /* Initialize the areas set aside by the OS to buffer the 2047 * platform/processor error states for MCA/INIT/CMC 2048 * handling. 2049 */ 2050 ia64_log_init(SAL_INFO_TYPE_MCA); 2051 ia64_log_init(SAL_INFO_TYPE_INIT); 2052 ia64_log_init(SAL_INFO_TYPE_CMC); 2053 ia64_log_init(SAL_INFO_TYPE_CPE); 2054 2055 mca_init = 1; 2056 printk(KERN_INFO "MCA related initialization done\n"); 2057 } 2058 2059 2060 /* 2061 * These pieces cannot be done in ia64_mca_init() because it is called before 2062 * early_irq_init() which would wipe out our percpu irq registrations. But we 2063 * cannot leave them until ia64_mca_late_init() because by then all the other 2064 * processors have been brought online and have set their own CMC vectors to 2065 * point at a non-existant action. Called from arch_early_irq_init(). 2066 */ 2067 void __init ia64_mca_irq_init(void) 2068 { 2069 /* 2070 * Configure the CMCI/P vector and handler. Interrupts for CMC are 2071 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c). 2072 */ 2073 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction); 2074 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction); 2075 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */ 2076 2077 /* Setup the MCA rendezvous interrupt vector */ 2078 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction); 2079 2080 /* Setup the MCA wakeup interrupt vector */ 2081 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction); 2082 2083 #ifdef CONFIG_ACPI 2084 /* Setup the CPEI/P handler */ 2085 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction); 2086 #endif 2087 } 2088 2089 /* 2090 * ia64_mca_late_init 2091 * 2092 * Opportunity to setup things that require initialization later 2093 * than ia64_mca_init. Setup a timer to poll for CPEs if the 2094 * platform doesn't support an interrupt driven mechanism. 2095 * 2096 * Inputs : None 2097 * Outputs : Status 2098 */ 2099 static int __init 2100 ia64_mca_late_init(void) 2101 { 2102 if (!mca_init) 2103 return 0; 2104 2105 /* Setup the CMCI/P vector and handler */ 2106 timer_setup(&cmc_poll_timer, ia64_mca_cmc_poll, 0); 2107 2108 /* Unmask/enable the vector */ 2109 cmc_polling_enabled = 0; 2110 cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "ia64/mca:online", 2111 ia64_mca_cpu_online, NULL); 2112 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__); 2113 2114 #ifdef CONFIG_ACPI 2115 /* Setup the CPEI/P vector and handler */ 2116 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI); 2117 timer_setup(&cpe_poll_timer, ia64_mca_cpe_poll, 0); 2118 2119 { 2120 unsigned int irq; 2121 2122 if (cpe_vector >= 0) { 2123 /* If platform supports CPEI, enable the irq. */ 2124 irq = local_vector_to_irq(cpe_vector); 2125 if (irq > 0) { 2126 cpe_poll_enabled = 0; 2127 irq_set_status_flags(irq, IRQ_PER_CPU); 2128 setup_irq(irq, &mca_cpe_irqaction); 2129 ia64_cpe_irq = irq; 2130 ia64_mca_register_cpev(cpe_vector); 2131 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", 2132 __func__); 2133 return 0; 2134 } 2135 printk(KERN_ERR "%s: Failed to find irq for CPE " 2136 "interrupt handler, vector %d\n", 2137 __func__, cpe_vector); 2138 } 2139 /* If platform doesn't support CPEI, get the timer going. */ 2140 if (cpe_poll_enabled) { 2141 ia64_mca_cpe_poll(0UL); 2142 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__); 2143 } 2144 } 2145 #endif 2146 2147 return 0; 2148 } 2149 2150 device_initcall(ia64_mca_late_init); 2151