1/* 2 * arch/ia64/kernel/ivt.S 3 * 4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co 5 * Stephane Eranian <eranian@hpl.hp.com> 6 * David Mosberger <davidm@hpl.hp.com> 7 * Copyright (C) 2000, 2002-2003 Intel Co 8 * Asit Mallick <asit.k.mallick@intel.com> 9 * Suresh Siddha <suresh.b.siddha@intel.com> 10 * Kenneth Chen <kenneth.w.chen@intel.com> 11 * Fenghua Yu <fenghua.yu@intel.com> 12 * 13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP 14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT. 15 */ 16/* 17 * This file defines the interruption vector table used by the CPU. 18 * It does not include one entry per possible cause of interruption. 19 * 20 * The first 20 entries of the table contain 64 bundles each while the 21 * remaining 48 entries contain only 16 bundles each. 22 * 23 * The 64 bundles are used to allow inlining the whole handler for critical 24 * interruptions like TLB misses. 25 * 26 * For each entry, the comment is as follows: 27 * 28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) 29 * entry offset ----/ / / / / 30 * entry number ---------/ / / / 31 * size of the entry -------------/ / / 32 * vector name -------------------------------------/ / 33 * interruptions triggering this vector ----------------------/ 34 * 35 * The table is 32KB in size and must be aligned on 32KB boundary. 36 * (The CPU ignores the 15 lower bits of the address) 37 * 38 * Table is based upon EAS2.6 (Oct 1999) 39 */ 40 41#include <linux/config.h> 42 43#include <asm/asmmacro.h> 44#include <asm/break.h> 45#include <asm/ia32.h> 46#include <asm/kregs.h> 47#include <asm/offsets.h> 48#include <asm/pgtable.h> 49#include <asm/processor.h> 50#include <asm/ptrace.h> 51#include <asm/system.h> 52#include <asm/thread_info.h> 53#include <asm/unistd.h> 54#include <asm/errno.h> 55 56#if 1 57# define PSR_DEFAULT_BITS psr.ac 58#else 59# define PSR_DEFAULT_BITS 0 60#endif 61 62#if 0 63 /* 64 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't 65 * needed for something else before enabling this... 66 */ 67# define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16 68#else 69# define DBG_FAULT(i) 70#endif 71 72#define MINSTATE_VIRT /* needed by minstate.h */ 73#include "minstate.h" 74 75#define FAULT(n) \ 76 mov r31=pr; \ 77 mov r19=n;; /* prepare to save predicates */ \ 78 br.sptk.many dispatch_to_fault_handler 79 80 .section .text.ivt,"ax" 81 82 .align 32768 // align on 32KB boundary 83 .global ia64_ivt 84ia64_ivt: 85///////////////////////////////////////////////////////////////////////////////////////// 86// 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47) 87ENTRY(vhpt_miss) 88 DBG_FAULT(0) 89 /* 90 * The VHPT vector is invoked when the TLB entry for the virtual page table 91 * is missing. This happens only as a result of a previous 92 * (the "original") TLB miss, which may either be caused by an instruction 93 * fetch or a data access (or non-access). 94 * 95 * What we do here is normal TLB miss handing for the _original_ miss, followed 96 * by inserting the TLB entry for the virtual page table page that the VHPT 97 * walker was attempting to access. The latter gets inserted as long 98 * as both L1 and L2 have valid mappings for the faulting address. 99 * The TLB entry for the original miss gets inserted only if 100 * the L3 entry indicates that the page is present. 101 * 102 * do_page_fault gets invoked in the following cases: 103 * - the faulting virtual address uses unimplemented address bits 104 * - the faulting virtual address has no L1, L2, or L3 mapping 105 */ 106 mov r16=cr.ifa // get address that caused the TLB miss 107#ifdef CONFIG_HUGETLB_PAGE 108 movl r18=PAGE_SHIFT 109 mov r25=cr.itir 110#endif 111 ;; 112 rsm psr.dt // use physical addressing for data 113 mov r31=pr // save the predicate registers 114 mov r19=IA64_KR(PT_BASE) // get page table base address 115 shl r21=r16,3 // shift bit 60 into sign bit 116 shr.u r17=r16,61 // get the region number into r17 117 ;; 118 shr r22=r21,3 119#ifdef CONFIG_HUGETLB_PAGE 120 extr.u r26=r25,2,6 121 ;; 122 cmp.ne p8,p0=r18,r26 123 sub r27=r26,r18 124 ;; 125(p8) dep r25=r18,r25,2,6 126(p8) shr r22=r22,r27 127#endif 128 ;; 129 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5? 130 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address 131 ;; 132(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place 133 134 srlz.d 135 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir 136 137 .pred.rel "mutex", p6, p7 138(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT 139(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 140 ;; 141(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8 142(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8) 143 cmp.eq p7,p6=0,r21 // unused address bits all zeroes? 144 shr.u r18=r22,PMD_SHIFT // shift L2 index into position 145 ;; 146 ld8 r17=[r17] // fetch the L1 entry (may be 0) 147 ;; 148(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL? 149 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry 150 ;; 151(p7) ld8 r20=[r17] // fetch the L2 entry (may be 0) 152 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position 153 ;; 154(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL? 155 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry 156 ;; 157(p7) ld8 r18=[r21] // read the L3 PTE 158 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss 159 ;; 160(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared? 161 mov r22=cr.iha // get the VHPT address that caused the TLB miss 162 ;; // avoid RAW on p7 163(p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss? 164 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address 165 ;; 166(p10) itc.i r18 // insert the instruction TLB entry 167(p11) itc.d r18 // insert the data TLB entry 168(p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault) 169 mov cr.ifa=r22 170 171#ifdef CONFIG_HUGETLB_PAGE 172(p8) mov cr.itir=r25 // change to default page-size for VHPT 173#endif 174 175 /* 176 * Now compute and insert the TLB entry for the virtual page table. We never 177 * execute in a page table page so there is no need to set the exception deferral 178 * bit. 179 */ 180 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23 181 ;; 182(p7) itc.d r24 183 ;; 184#ifdef CONFIG_SMP 185 /* 186 * Tell the assemblers dependency-violation checker that the above "itc" instructions 187 * cannot possibly affect the following loads: 188 */ 189 dv_serialize_data 190 191 /* 192 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g 193 * between reading the pagetable and the "itc". If so, flush the entry we 194 * inserted and retry. 195 */ 196 ld8 r25=[r21] // read L3 PTE again 197 ld8 r26=[r17] // read L2 entry again 198 ;; 199 cmp.ne p6,p7=r26,r20 // did L2 entry change 200 mov r27=PAGE_SHIFT<<2 201 ;; 202(p6) ptc.l r22,r27 // purge PTE page translation 203(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change 204 ;; 205(p6) ptc.l r16,r27 // purge translation 206#endif 207 208 mov pr=r31,-1 // restore predicate registers 209 rfi 210END(vhpt_miss) 211 212 .org ia64_ivt+0x400 213///////////////////////////////////////////////////////////////////////////////////////// 214// 0x0400 Entry 1 (size 64 bundles) ITLB (21) 215ENTRY(itlb_miss) 216 DBG_FAULT(1) 217 /* 218 * The ITLB handler accesses the L3 PTE via the virtually mapped linear 219 * page table. If a nested TLB miss occurs, we switch into physical 220 * mode, walk the page table, and then re-execute the L3 PTE read 221 * and go on normally after that. 222 */ 223 mov r16=cr.ifa // get virtual address 224 mov r29=b0 // save b0 225 mov r31=pr // save predicates 226.itlb_fault: 227 mov r17=cr.iha // get virtual address of L3 PTE 228 movl r30=1f // load nested fault continuation point 229 ;; 2301: ld8 r18=[r17] // read L3 PTE 231 ;; 232 mov b0=r29 233 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? 234(p6) br.cond.spnt page_fault 235 ;; 236 itc.i r18 237 ;; 238#ifdef CONFIG_SMP 239 /* 240 * Tell the assemblers dependency-violation checker that the above "itc" instructions 241 * cannot possibly affect the following loads: 242 */ 243 dv_serialize_data 244 245 ld8 r19=[r17] // read L3 PTE again and see if same 246 mov r20=PAGE_SHIFT<<2 // setup page size for purge 247 ;; 248 cmp.ne p7,p0=r18,r19 249 ;; 250(p7) ptc.l r16,r20 251#endif 252 mov pr=r31,-1 253 rfi 254END(itlb_miss) 255 256 .org ia64_ivt+0x0800 257///////////////////////////////////////////////////////////////////////////////////////// 258// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) 259ENTRY(dtlb_miss) 260 DBG_FAULT(2) 261 /* 262 * The DTLB handler accesses the L3 PTE via the virtually mapped linear 263 * page table. If a nested TLB miss occurs, we switch into physical 264 * mode, walk the page table, and then re-execute the L3 PTE read 265 * and go on normally after that. 266 */ 267 mov r16=cr.ifa // get virtual address 268 mov r29=b0 // save b0 269 mov r31=pr // save predicates 270dtlb_fault: 271 mov r17=cr.iha // get virtual address of L3 PTE 272 movl r30=1f // load nested fault continuation point 273 ;; 2741: ld8 r18=[r17] // read L3 PTE 275 ;; 276 mov b0=r29 277 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared? 278(p6) br.cond.spnt page_fault 279 ;; 280 itc.d r18 281 ;; 282#ifdef CONFIG_SMP 283 /* 284 * Tell the assemblers dependency-violation checker that the above "itc" instructions 285 * cannot possibly affect the following loads: 286 */ 287 dv_serialize_data 288 289 ld8 r19=[r17] // read L3 PTE again and see if same 290 mov r20=PAGE_SHIFT<<2 // setup page size for purge 291 ;; 292 cmp.ne p7,p0=r18,r19 293 ;; 294(p7) ptc.l r16,r20 295#endif 296 mov pr=r31,-1 297 rfi 298END(dtlb_miss) 299 300 .org ia64_ivt+0x0c00 301///////////////////////////////////////////////////////////////////////////////////////// 302// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) 303ENTRY(alt_itlb_miss) 304 DBG_FAULT(3) 305 mov r16=cr.ifa // get address that caused the TLB miss 306 movl r17=PAGE_KERNEL 307 mov r21=cr.ipsr 308 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) 309 mov r31=pr 310 ;; 311#ifdef CONFIG_DISABLE_VHPT 312 shr.u r22=r16,61 // get the region number into r21 313 ;; 314 cmp.gt p8,p0=6,r22 // user mode 315 ;; 316(p8) thash r17=r16 317 ;; 318(p8) mov cr.iha=r17 319(p8) mov r29=b0 // save b0 320(p8) br.cond.dptk .itlb_fault 321#endif 322 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl 323 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits 324 shr.u r18=r16,57 // move address bit 61 to bit 4 325 ;; 326 andcm r18=0x10,r18 // bit 4=~address-bit(61) 327 cmp.ne p8,p0=r0,r23 // psr.cpl != 0? 328 or r19=r17,r19 // insert PTE control bits into r19 329 ;; 330 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 331(p8) br.cond.spnt page_fault 332 ;; 333 itc.i r19 // insert the TLB entry 334 mov pr=r31,-1 335 rfi 336END(alt_itlb_miss) 337 338 .org ia64_ivt+0x1000 339///////////////////////////////////////////////////////////////////////////////////////// 340// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) 341ENTRY(alt_dtlb_miss) 342 DBG_FAULT(4) 343 mov r16=cr.ifa // get address that caused the TLB miss 344 movl r17=PAGE_KERNEL 345 mov r20=cr.isr 346 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) 347 mov r21=cr.ipsr 348 mov r31=pr 349 ;; 350#ifdef CONFIG_DISABLE_VHPT 351 shr.u r22=r16,61 // get the region number into r21 352 ;; 353 cmp.gt p8,p0=6,r22 // access to region 0-5 354 ;; 355(p8) thash r17=r16 356 ;; 357(p8) mov cr.iha=r17 358(p8) mov r29=b0 // save b0 359(p8) br.cond.dptk dtlb_fault 360#endif 361 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl 362 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field 363 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? 364 shr.u r18=r16,57 // move address bit 61 to bit 4 365 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits 366 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? 367 ;; 368 andcm r18=0x10,r18 // bit 4=~address-bit(61) 369 cmp.ne p8,p0=r0,r23 370(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field 371(p8) br.cond.spnt page_fault 372 373 dep r21=-1,r21,IA64_PSR_ED_BIT,1 374 or r19=r19,r17 // insert PTE control bits into r19 375 ;; 376 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 377(p6) mov cr.ipsr=r21 378 ;; 379(p7) itc.d r19 // insert the TLB entry 380 mov pr=r31,-1 381 rfi 382END(alt_dtlb_miss) 383 384 .org ia64_ivt+0x1400 385///////////////////////////////////////////////////////////////////////////////////////// 386// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45) 387ENTRY(nested_dtlb_miss) 388 /* 389 * In the absence of kernel bugs, we get here when the virtually mapped linear 390 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction 391 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page 392 * table is missing, a nested TLB miss fault is triggered and control is 393 * transferred to this point. When this happens, we lookup the pte for the 394 * faulting address by walking the page table in physical mode and return to the 395 * continuation point passed in register r30 (or call page_fault if the address is 396 * not mapped). 397 * 398 * Input: r16: faulting address 399 * r29: saved b0 400 * r30: continuation address 401 * r31: saved pr 402 * 403 * Output: r17: physical address of L3 PTE of faulting address 404 * r29: saved b0 405 * r30: continuation address 406 * r31: saved pr 407 * 408 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared) 409 */ 410 rsm psr.dt // switch to using physical data addressing 411 mov r19=IA64_KR(PT_BASE) // get the page table base address 412 shl r21=r16,3 // shift bit 60 into sign bit 413 mov r18=cr.itir 414 ;; 415 shr.u r17=r16,61 // get the region number into r17 416 extr.u r18=r18,2,6 // get the faulting page size 417 ;; 418 cmp.eq p6,p7=5,r17 // is faulting address in region 5? 419 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address 420 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18 421 ;; 422 shr.u r22=r16,r22 423 shr.u r18=r16,r18 424(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place 425 426 srlz.d 427 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir 428 429 .pred.rel "mutex", p6, p7 430(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT 431(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 432 ;; 433(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8 434(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8) 435 cmp.eq p7,p6=0,r21 // unused address bits all zeroes? 436 shr.u r18=r22,PMD_SHIFT // shift L2 index into position 437 ;; 438 ld8 r17=[r17] // fetch the L1 entry (may be 0) 439 ;; 440(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL? 441 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry 442 ;; 443(p7) ld8 r17=[r17] // fetch the L2 entry (may be 0) 444 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position 445 ;; 446(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL? 447 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry 448(p6) br.cond.spnt page_fault 449 mov b0=r30 450 br.sptk.many b0 // return to continuation point 451END(nested_dtlb_miss) 452 453 .org ia64_ivt+0x1800 454///////////////////////////////////////////////////////////////////////////////////////// 455// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) 456ENTRY(ikey_miss) 457 DBG_FAULT(6) 458 FAULT(6) 459END(ikey_miss) 460 461 //----------------------------------------------------------------------------------- 462 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address) 463ENTRY(page_fault) 464 ssm psr.dt 465 ;; 466 srlz.i 467 ;; 468 SAVE_MIN_WITH_COVER 469 alloc r15=ar.pfs,0,0,3,0 470 mov out0=cr.ifa 471 mov out1=cr.isr 472 adds r3=8,r2 // set up second base pointer 473 ;; 474 ssm psr.ic | PSR_DEFAULT_BITS 475 ;; 476 srlz.i // guarantee that interruption collectin is on 477 ;; 478(p15) ssm psr.i // restore psr.i 479 movl r14=ia64_leave_kernel 480 ;; 481 SAVE_REST 482 mov rp=r14 483 ;; 484 adds out2=16,r12 // out2 = pointer to pt_regs 485 br.call.sptk.many b6=ia64_do_page_fault // ignore return address 486END(page_fault) 487 488 .org ia64_ivt+0x1c00 489///////////////////////////////////////////////////////////////////////////////////////// 490// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) 491ENTRY(dkey_miss) 492 DBG_FAULT(7) 493 FAULT(7) 494END(dkey_miss) 495 496 .org ia64_ivt+0x2000 497///////////////////////////////////////////////////////////////////////////////////////// 498// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) 499ENTRY(dirty_bit) 500 DBG_FAULT(8) 501 /* 502 * What we do here is to simply turn on the dirty bit in the PTE. We need to 503 * update both the page-table and the TLB entry. To efficiently access the PTE, 504 * we address it through the virtual page table. Most likely, the TLB entry for 505 * the relevant virtual page table page is still present in the TLB so we can 506 * normally do this without additional TLB misses. In case the necessary virtual 507 * page table TLB entry isn't present, we take a nested TLB miss hit where we look 508 * up the physical address of the L3 PTE and then continue at label 1 below. 509 */ 510 mov r16=cr.ifa // get the address that caused the fault 511 movl r30=1f // load continuation point in case of nested fault 512 ;; 513 thash r17=r16 // compute virtual address of L3 PTE 514 mov r29=b0 // save b0 in case of nested fault 515 mov r31=pr // save pr 516#ifdef CONFIG_SMP 517 mov r28=ar.ccv // save ar.ccv 518 ;; 5191: ld8 r18=[r17] 520 ;; // avoid RAW on r18 521 mov ar.ccv=r18 // set compare value for cmpxchg 522 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits 523 ;; 524 cmpxchg8.acq r26=[r17],r25,ar.ccv 525 mov r24=PAGE_SHIFT<<2 526 ;; 527 cmp.eq p6,p7=r26,r18 528 ;; 529(p6) itc.d r25 // install updated PTE 530 ;; 531 /* 532 * Tell the assemblers dependency-violation checker that the above "itc" instructions 533 * cannot possibly affect the following loads: 534 */ 535 dv_serialize_data 536 537 ld8 r18=[r17] // read PTE again 538 ;; 539 cmp.eq p6,p7=r18,r25 // is it same as the newly installed 540 ;; 541(p7) ptc.l r16,r24 542 mov b0=r29 // restore b0 543 mov ar.ccv=r28 544#else 545 ;; 5461: ld8 r18=[r17] 547 ;; // avoid RAW on r18 548 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits 549 mov b0=r29 // restore b0 550 ;; 551 st8 [r17]=r18 // store back updated PTE 552 itc.d r18 // install updated PTE 553#endif 554 mov pr=r31,-1 // restore pr 555 rfi 556END(dirty_bit) 557 558 .org ia64_ivt+0x2400 559///////////////////////////////////////////////////////////////////////////////////////// 560// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) 561ENTRY(iaccess_bit) 562 DBG_FAULT(9) 563 // Like Entry 8, except for instruction access 564 mov r16=cr.ifa // get the address that caused the fault 565 movl r30=1f // load continuation point in case of nested fault 566 mov r31=pr // save predicates 567#ifdef CONFIG_ITANIUM 568 /* 569 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status. 570 */ 571 mov r17=cr.ipsr 572 ;; 573 mov r18=cr.iip 574 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set? 575 ;; 576(p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa 577#endif /* CONFIG_ITANIUM */ 578 ;; 579 thash r17=r16 // compute virtual address of L3 PTE 580 mov r29=b0 // save b0 in case of nested fault) 581#ifdef CONFIG_SMP 582 mov r28=ar.ccv // save ar.ccv 583 ;; 5841: ld8 r18=[r17] 585 ;; 586 mov ar.ccv=r18 // set compare value for cmpxchg 587 or r25=_PAGE_A,r18 // set the accessed bit 588 ;; 589 cmpxchg8.acq r26=[r17],r25,ar.ccv 590 mov r24=PAGE_SHIFT<<2 591 ;; 592 cmp.eq p6,p7=r26,r18 593 ;; 594(p6) itc.i r25 // install updated PTE 595 ;; 596 /* 597 * Tell the assemblers dependency-violation checker that the above "itc" instructions 598 * cannot possibly affect the following loads: 599 */ 600 dv_serialize_data 601 602 ld8 r18=[r17] // read PTE again 603 ;; 604 cmp.eq p6,p7=r18,r25 // is it same as the newly installed 605 ;; 606(p7) ptc.l r16,r24 607 mov b0=r29 // restore b0 608 mov ar.ccv=r28 609#else /* !CONFIG_SMP */ 610 ;; 6111: ld8 r18=[r17] 612 ;; 613 or r18=_PAGE_A,r18 // set the accessed bit 614 mov b0=r29 // restore b0 615 ;; 616 st8 [r17]=r18 // store back updated PTE 617 itc.i r18 // install updated PTE 618#endif /* !CONFIG_SMP */ 619 mov pr=r31,-1 620 rfi 621END(iaccess_bit) 622 623 .org ia64_ivt+0x2800 624///////////////////////////////////////////////////////////////////////////////////////// 625// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) 626ENTRY(daccess_bit) 627 DBG_FAULT(10) 628 // Like Entry 8, except for data access 629 mov r16=cr.ifa // get the address that caused the fault 630 movl r30=1f // load continuation point in case of nested fault 631 ;; 632 thash r17=r16 // compute virtual address of L3 PTE 633 mov r31=pr 634 mov r29=b0 // save b0 in case of nested fault) 635#ifdef CONFIG_SMP 636 mov r28=ar.ccv // save ar.ccv 637 ;; 6381: ld8 r18=[r17] 639 ;; // avoid RAW on r18 640 mov ar.ccv=r18 // set compare value for cmpxchg 641 or r25=_PAGE_A,r18 // set the dirty bit 642 ;; 643 cmpxchg8.acq r26=[r17],r25,ar.ccv 644 mov r24=PAGE_SHIFT<<2 645 ;; 646 cmp.eq p6,p7=r26,r18 647 ;; 648(p6) itc.d r25 // install updated PTE 649 /* 650 * Tell the assemblers dependency-violation checker that the above "itc" instructions 651 * cannot possibly affect the following loads: 652 */ 653 dv_serialize_data 654 ;; 655 ld8 r18=[r17] // read PTE again 656 ;; 657 cmp.eq p6,p7=r18,r25 // is it same as the newly installed 658 ;; 659(p7) ptc.l r16,r24 660 mov ar.ccv=r28 661#else 662 ;; 6631: ld8 r18=[r17] 664 ;; // avoid RAW on r18 665 or r18=_PAGE_A,r18 // set the accessed bit 666 ;; 667 st8 [r17]=r18 // store back updated PTE 668 itc.d r18 // install updated PTE 669#endif 670 mov b0=r29 // restore b0 671 mov pr=r31,-1 672 rfi 673END(daccess_bit) 674 675 .org ia64_ivt+0x2c00 676///////////////////////////////////////////////////////////////////////////////////////// 677// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33) 678ENTRY(break_fault) 679 /* 680 * The streamlined system call entry/exit paths only save/restore the initial part 681 * of pt_regs. This implies that the callers of system-calls must adhere to the 682 * normal procedure calling conventions. 683 * 684 * Registers to be saved & restored: 685 * CR registers: cr.ipsr, cr.iip, cr.ifs 686 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr 687 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15 688 * Registers to be restored only: 689 * r8-r11: output value from the system call. 690 * 691 * During system call exit, scratch registers (including r15) are modified/cleared 692 * to prevent leaking bits from kernel to user level. 693 */ 694 DBG_FAULT(11) 695 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat. 696 mov r17=cr.iim 697 mov r18=__IA64_BREAK_SYSCALL 698 mov r21=ar.fpsr 699 mov r29=cr.ipsr 700 mov r19=b6 701 mov r25=ar.unat 702 mov r27=ar.rsc 703 mov r26=ar.pfs 704 mov r28=cr.iip 705 mov r31=pr // prepare to save predicates 706 mov r20=r1 707 ;; 708 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 709 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so) 710(p7) br.cond.spnt non_syscall 711 ;; 712 ld1 r17=[r16] // load current->thread.on_ustack flag 713 st1 [r16]=r0 // clear current->thread.on_ustack flag 714 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT 715 ;; 716 invala 717 718 /* adjust return address so we skip over the break instruction: */ 719 720 extr.u r8=r29,41,2 // extract ei field from cr.ipsr 721 ;; 722 cmp.eq p6,p7=2,r8 // isr.ei==2? 723 mov r2=r1 // setup r2 for ia64_syscall_setup 724 ;; 725(p6) mov r8=0 // clear ei to 0 726(p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped 727(p7) adds r8=1,r8 // increment ei to next slot 728 ;; 729 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already? 730 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr 731 ;; 732 733 // switch from user to kernel RBS: 734 MINSTATE_START_SAVE_MIN_VIRT 735 br.call.sptk.many b7=ia64_syscall_setup 736 ;; 737 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1 738 ssm psr.ic | PSR_DEFAULT_BITS 739 ;; 740 srlz.i // guarantee that interruption collection is on 741 mov r3=NR_syscalls - 1 742 ;; 743(p15) ssm psr.i // restore psr.i 744 // p10==true means out registers are more than 8 or r15's Nat is true 745(p10) br.cond.spnt.many ia64_ret_from_syscall 746 ;; 747 movl r16=sys_call_table 748 749 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024 750 movl r2=ia64_ret_from_syscall 751 ;; 752 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024) 753 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ? 754 mov rp=r2 // set the real return addr 755 ;; 756(p6) ld8 r20=[r20] // load address of syscall entry point 757(p7) movl r20=sys_ni_syscall 758 759 add r2=TI_FLAGS+IA64_TASK_SIZE,r13 760 ;; 761 ld4 r2=[r2] // r2 = current_thread_info()->flags 762 ;; 763 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit 764 ;; 765 cmp.eq p8,p0=r2,r0 766 mov b6=r20 767 ;; 768(p8) br.call.sptk.many b6=b6 // ignore this return addr 769 br.cond.sptk ia64_trace_syscall 770 // NOT REACHED 771END(break_fault) 772 773 .org ia64_ivt+0x3000 774///////////////////////////////////////////////////////////////////////////////////////// 775// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) 776ENTRY(interrupt) 777 DBG_FAULT(12) 778 mov r31=pr // prepare to save predicates 779 ;; 780 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3 781 ssm psr.ic | PSR_DEFAULT_BITS 782 ;; 783 adds r3=8,r2 // set up second base pointer for SAVE_REST 784 srlz.i // ensure everybody knows psr.ic is back on 785 ;; 786 SAVE_REST 787 ;; 788 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group 789 mov out0=cr.ivr // pass cr.ivr as first arg 790 add out1=16,sp // pass pointer to pt_regs as second arg 791 ;; 792 srlz.d // make sure we see the effect of cr.ivr 793 movl r14=ia64_leave_kernel 794 ;; 795 mov rp=r14 796 br.call.sptk.many b6=ia64_handle_irq 797END(interrupt) 798 799 .org ia64_ivt+0x3400 800///////////////////////////////////////////////////////////////////////////////////////// 801// 0x3400 Entry 13 (size 64 bundles) Reserved 802 DBG_FAULT(13) 803 FAULT(13) 804 805 .org ia64_ivt+0x3800 806///////////////////////////////////////////////////////////////////////////////////////// 807// 0x3800 Entry 14 (size 64 bundles) Reserved 808 DBG_FAULT(14) 809 FAULT(14) 810 811 /* 812 * There is no particular reason for this code to be here, other than that 813 * there happens to be space here that would go unused otherwise. If this 814 * fault ever gets "unreserved", simply moved the following code to a more 815 * suitable spot... 816 * 817 * ia64_syscall_setup() is a separate subroutine so that it can 818 * allocate stacked registers so it can safely demine any 819 * potential NaT values from the input registers. 820 * 821 * On entry: 822 * - executing on bank 0 or bank 1 register set (doesn't matter) 823 * - r1: stack pointer 824 * - r2: current task pointer 825 * - r3: preserved 826 * - r11: original contents (saved ar.pfs to be saved) 827 * - r12: original contents (sp to be saved) 828 * - r13: original contents (tp to be saved) 829 * - r15: original contents (syscall # to be saved) 830 * - r18: saved bsp (after switching to kernel stack) 831 * - r19: saved b6 832 * - r20: saved r1 (gp) 833 * - r21: saved ar.fpsr 834 * - r22: kernel's register backing store base (krbs_base) 835 * - r23: saved ar.bspstore 836 * - r24: saved ar.rnat 837 * - r25: saved ar.unat 838 * - r26: saved ar.pfs 839 * - r27: saved ar.rsc 840 * - r28: saved cr.iip 841 * - r29: saved cr.ipsr 842 * - r31: saved pr 843 * - b0: original contents (to be saved) 844 * On exit: 845 * - executing on bank 1 registers 846 * - psr.ic enabled, interrupts restored 847 * - p10: TRUE if syscall is invoked with more than 8 out 848 * registers or r15's Nat is true 849 * - r1: kernel's gp 850 * - r3: preserved (same as on entry) 851 * - r8: -EINVAL if p10 is true 852 * - r12: points to kernel stack 853 * - r13: points to current task 854 * - p15: TRUE if interrupts need to be re-enabled 855 * - ar.fpsr: set to kernel settings 856 */ 857GLOBAL_ENTRY(ia64_syscall_setup) 858#if PT(B6) != 0 859# error This code assumes that b6 is the first field in pt_regs. 860#endif 861 st8 [r1]=r19 // save b6 862 add r16=PT(CR_IPSR),r1 // initialize first base pointer 863 add r17=PT(R11),r1 // initialize second base pointer 864 ;; 865 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable 866 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr 867 tnat.nz p8,p0=in0 868 869 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11 870 tnat.nz p9,p0=in1 871(pKStk) mov r18=r0 // make sure r18 isn't NaT 872 ;; 873 874 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs 875 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip 876 mov r28=b0 // save b0 (2 cyc) 877 ;; 878 879 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat 880 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0] 881(p8) mov in0=-1 882 ;; 883 884 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs 885 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs 886 and r8=0x7f,r19 // A // get sof of ar.pfs 887 888 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc 889 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0 890(p9) mov in1=-1 891 ;; 892 893(pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8 894 tnat.nz p10,p0=in2 895 add r11=8,r11 896 ;; 897(pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field 898(pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field 899 tnat.nz p11,p0=in3 900 ;; 901(p10) mov in2=-1 902 tnat.nz p12,p0=in4 // [I0] 903(p11) mov in3=-1 904 ;; 905(pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat 906(pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore 907 shl r18=r18,16 // compute ar.rsc to be used for "loadrs" 908 ;; 909 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates 910 st8 [r17]=r28,PT(R1)-PT(B0) // save b0 911 tnat.nz p13,p0=in5 // [I0] 912 ;; 913 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs" 914 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1 915(p12) mov in4=-1 916 ;; 917 918.mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12 919.mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13 920(p13) mov in5=-1 921 ;; 922 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr 923 tnat.nz p14,p0=in6 924 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8 925 ;; 926 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error) 927(p9) tnat.nz p10,p0=r15 928 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch) 929 930 st8.spill [r17]=r15 // save r15 931 tnat.nz p8,p0=in7 932 nop.i 0 933 934 mov r13=r2 // establish `current' 935 movl r1=__gp // establish kernel global pointer 936 ;; 937(p14) mov in6=-1 938(p8) mov in7=-1 939 nop.i 0 940 941 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 942 movl r17=FPSR_DEFAULT 943 ;; 944 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value 945(p10) mov r8=-EINVAL 946 br.ret.sptk.many b7 947END(ia64_syscall_setup) 948 949 .org ia64_ivt+0x3c00 950///////////////////////////////////////////////////////////////////////////////////////// 951// 0x3c00 Entry 15 (size 64 bundles) Reserved 952 DBG_FAULT(15) 953 FAULT(15) 954 955 /* 956 * Squatting in this space ... 957 * 958 * This special case dispatcher for illegal operation faults allows preserved 959 * registers to be modified through a callback function (asm only) that is handed 960 * back from the fault handler in r8. Up to three arguments can be passed to the 961 * callback function by returning an aggregate with the callback as its first 962 * element, followed by the arguments. 963 */ 964ENTRY(dispatch_illegal_op_fault) 965 .prologue 966 .body 967 SAVE_MIN_WITH_COVER 968 ssm psr.ic | PSR_DEFAULT_BITS 969 ;; 970 srlz.i // guarantee that interruption collection is on 971 ;; 972(p15) ssm psr.i // restore psr.i 973 adds r3=8,r2 // set up second base pointer for SAVE_REST 974 ;; 975 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group 976 mov out0=ar.ec 977 ;; 978 SAVE_REST 979 PT_REGS_UNWIND_INFO(0) 980 ;; 981 br.call.sptk.many rp=ia64_illegal_op_fault 982.ret0: ;; 983 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group 984 mov out0=r9 985 mov out1=r10 986 mov out2=r11 987 movl r15=ia64_leave_kernel 988 ;; 989 mov rp=r15 990 mov b6=r8 991 ;; 992 cmp.ne p6,p0=0,r8 993(p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel 994 br.sptk.many ia64_leave_kernel 995END(dispatch_illegal_op_fault) 996 997 .org ia64_ivt+0x4000 998///////////////////////////////////////////////////////////////////////////////////////// 999// 0x4000 Entry 16 (size 64 bundles) Reserved 1000 DBG_FAULT(16) 1001 FAULT(16) 1002 1003 .org ia64_ivt+0x4400 1004///////////////////////////////////////////////////////////////////////////////////////// 1005// 0x4400 Entry 17 (size 64 bundles) Reserved 1006 DBG_FAULT(17) 1007 FAULT(17) 1008 1009ENTRY(non_syscall) 1010 SAVE_MIN_WITH_COVER 1011 1012 // There is no particular reason for this code to be here, other than that 1013 // there happens to be space here that would go unused otherwise. If this 1014 // fault ever gets "unreserved", simply moved the following code to a more 1015 // suitable spot... 1016 1017 alloc r14=ar.pfs,0,0,2,0 1018 mov out0=cr.iim 1019 add out1=16,sp 1020 adds r3=8,r2 // set up second base pointer for SAVE_REST 1021 1022 ssm psr.ic | PSR_DEFAULT_BITS 1023 ;; 1024 srlz.i // guarantee that interruption collection is on 1025 ;; 1026(p15) ssm psr.i // restore psr.i 1027 movl r15=ia64_leave_kernel 1028 ;; 1029 SAVE_REST 1030 mov rp=r15 1031 ;; 1032 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr 1033END(non_syscall) 1034 1035 .org ia64_ivt+0x4800 1036///////////////////////////////////////////////////////////////////////////////////////// 1037// 0x4800 Entry 18 (size 64 bundles) Reserved 1038 DBG_FAULT(18) 1039 FAULT(18) 1040 1041 /* 1042 * There is no particular reason for this code to be here, other than that 1043 * there happens to be space here that would go unused otherwise. If this 1044 * fault ever gets "unreserved", simply moved the following code to a more 1045 * suitable spot... 1046 */ 1047 1048ENTRY(dispatch_unaligned_handler) 1049 SAVE_MIN_WITH_COVER 1050 ;; 1051 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!) 1052 mov out0=cr.ifa 1053 adds out1=16,sp 1054 1055 ssm psr.ic | PSR_DEFAULT_BITS 1056 ;; 1057 srlz.i // guarantee that interruption collection is on 1058 ;; 1059(p15) ssm psr.i // restore psr.i 1060 adds r3=8,r2 // set up second base pointer 1061 ;; 1062 SAVE_REST 1063 movl r14=ia64_leave_kernel 1064 ;; 1065 mov rp=r14 1066 br.sptk.many ia64_prepare_handle_unaligned 1067END(dispatch_unaligned_handler) 1068 1069 .org ia64_ivt+0x4c00 1070///////////////////////////////////////////////////////////////////////////////////////// 1071// 0x4c00 Entry 19 (size 64 bundles) Reserved 1072 DBG_FAULT(19) 1073 FAULT(19) 1074 1075 /* 1076 * There is no particular reason for this code to be here, other than that 1077 * there happens to be space here that would go unused otherwise. If this 1078 * fault ever gets "unreserved", simply moved the following code to a more 1079 * suitable spot... 1080 */ 1081 1082ENTRY(dispatch_to_fault_handler) 1083 /* 1084 * Input: 1085 * psr.ic: off 1086 * r19: fault vector number (e.g., 24 for General Exception) 1087 * r31: contains saved predicates (pr) 1088 */ 1089 SAVE_MIN_WITH_COVER_R19 1090 alloc r14=ar.pfs,0,0,5,0 1091 mov out0=r15 1092 mov out1=cr.isr 1093 mov out2=cr.ifa 1094 mov out3=cr.iim 1095 mov out4=cr.itir 1096 ;; 1097 ssm psr.ic | PSR_DEFAULT_BITS 1098 ;; 1099 srlz.i // guarantee that interruption collection is on 1100 ;; 1101(p15) ssm psr.i // restore psr.i 1102 adds r3=8,r2 // set up second base pointer for SAVE_REST 1103 ;; 1104 SAVE_REST 1105 movl r14=ia64_leave_kernel 1106 ;; 1107 mov rp=r14 1108 br.call.sptk.many b6=ia64_fault 1109END(dispatch_to_fault_handler) 1110 1111// 1112// --- End of long entries, Beginning of short entries 1113// 1114 1115 .org ia64_ivt+0x5000 1116///////////////////////////////////////////////////////////////////////////////////////// 1117// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) 1118ENTRY(page_not_present) 1119 DBG_FAULT(20) 1120 mov r16=cr.ifa 1121 rsm psr.dt 1122 /* 1123 * The Linux page fault handler doesn't expect non-present pages to be in 1124 * the TLB. Flush the existing entry now, so we meet that expectation. 1125 */ 1126 mov r17=PAGE_SHIFT<<2 1127 ;; 1128 ptc.l r16,r17 1129 ;; 1130 mov r31=pr 1131 srlz.d 1132 br.sptk.many page_fault 1133END(page_not_present) 1134 1135 .org ia64_ivt+0x5100 1136///////////////////////////////////////////////////////////////////////////////////////// 1137// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) 1138ENTRY(key_permission) 1139 DBG_FAULT(21) 1140 mov r16=cr.ifa 1141 rsm psr.dt 1142 mov r31=pr 1143 ;; 1144 srlz.d 1145 br.sptk.many page_fault 1146END(key_permission) 1147 1148 .org ia64_ivt+0x5200 1149///////////////////////////////////////////////////////////////////////////////////////// 1150// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) 1151ENTRY(iaccess_rights) 1152 DBG_FAULT(22) 1153 mov r16=cr.ifa 1154 rsm psr.dt 1155 mov r31=pr 1156 ;; 1157 srlz.d 1158 br.sptk.many page_fault 1159END(iaccess_rights) 1160 1161 .org ia64_ivt+0x5300 1162///////////////////////////////////////////////////////////////////////////////////////// 1163// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) 1164ENTRY(daccess_rights) 1165 DBG_FAULT(23) 1166 mov r16=cr.ifa 1167 rsm psr.dt 1168 mov r31=pr 1169 ;; 1170 srlz.d 1171 br.sptk.many page_fault 1172END(daccess_rights) 1173 1174 .org ia64_ivt+0x5400 1175///////////////////////////////////////////////////////////////////////////////////////// 1176// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39) 1177ENTRY(general_exception) 1178 DBG_FAULT(24) 1179 mov r16=cr.isr 1180 mov r31=pr 1181 ;; 1182 cmp4.eq p6,p0=0,r16 1183(p6) br.sptk.many dispatch_illegal_op_fault 1184 ;; 1185 mov r19=24 // fault number 1186 br.sptk.many dispatch_to_fault_handler 1187END(general_exception) 1188 1189 .org ia64_ivt+0x5500 1190///////////////////////////////////////////////////////////////////////////////////////// 1191// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) 1192ENTRY(disabled_fp_reg) 1193 DBG_FAULT(25) 1194 rsm psr.dfh // ensure we can access fph 1195 ;; 1196 srlz.d 1197 mov r31=pr 1198 mov r19=25 1199 br.sptk.many dispatch_to_fault_handler 1200END(disabled_fp_reg) 1201 1202 .org ia64_ivt+0x5600 1203///////////////////////////////////////////////////////////////////////////////////////// 1204// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) 1205ENTRY(nat_consumption) 1206 DBG_FAULT(26) 1207 FAULT(26) 1208END(nat_consumption) 1209 1210 .org ia64_ivt+0x5700 1211///////////////////////////////////////////////////////////////////////////////////////// 1212// 0x5700 Entry 27 (size 16 bundles) Speculation (40) 1213ENTRY(speculation_vector) 1214 DBG_FAULT(27) 1215 /* 1216 * A [f]chk.[as] instruction needs to take the branch to the recovery code but 1217 * this part of the architecture is not implemented in hardware on some CPUs, such 1218 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains 1219 * the relative target (not yet sign extended). So after sign extending it we 1220 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero, 1221 * i.e., the slot to restart into. 1222 * 1223 * cr.imm contains zero_ext(imm21) 1224 */ 1225 mov r18=cr.iim 1226 ;; 1227 mov r17=cr.iip 1228 shl r18=r18,43 // put sign bit in position (43=64-21) 1229 ;; 1230 1231 mov r16=cr.ipsr 1232 shr r18=r18,39 // sign extend (39=43-4) 1233 ;; 1234 1235 add r17=r17,r18 // now add the offset 1236 ;; 1237 mov cr.iip=r17 1238 dep r16=0,r16,41,2 // clear EI 1239 ;; 1240 1241 mov cr.ipsr=r16 1242 ;; 1243 1244 rfi // and go back 1245END(speculation_vector) 1246 1247 .org ia64_ivt+0x5800 1248///////////////////////////////////////////////////////////////////////////////////////// 1249// 0x5800 Entry 28 (size 16 bundles) Reserved 1250 DBG_FAULT(28) 1251 FAULT(28) 1252 1253 .org ia64_ivt+0x5900 1254///////////////////////////////////////////////////////////////////////////////////////// 1255// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) 1256ENTRY(debug_vector) 1257 DBG_FAULT(29) 1258 FAULT(29) 1259END(debug_vector) 1260 1261 .org ia64_ivt+0x5a00 1262///////////////////////////////////////////////////////////////////////////////////////// 1263// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) 1264ENTRY(unaligned_access) 1265 DBG_FAULT(30) 1266 mov r16=cr.ipsr 1267 mov r31=pr // prepare to save predicates 1268 ;; 1269 br.sptk.many dispatch_unaligned_handler 1270END(unaligned_access) 1271 1272 .org ia64_ivt+0x5b00 1273///////////////////////////////////////////////////////////////////////////////////////// 1274// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) 1275ENTRY(unsupported_data_reference) 1276 DBG_FAULT(31) 1277 FAULT(31) 1278END(unsupported_data_reference) 1279 1280 .org ia64_ivt+0x5c00 1281///////////////////////////////////////////////////////////////////////////////////////// 1282// 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) 1283ENTRY(floating_point_fault) 1284 DBG_FAULT(32) 1285 FAULT(32) 1286END(floating_point_fault) 1287 1288 .org ia64_ivt+0x5d00 1289///////////////////////////////////////////////////////////////////////////////////////// 1290// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) 1291ENTRY(floating_point_trap) 1292 DBG_FAULT(33) 1293 FAULT(33) 1294END(floating_point_trap) 1295 1296 .org ia64_ivt+0x5e00 1297///////////////////////////////////////////////////////////////////////////////////////// 1298// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66) 1299ENTRY(lower_privilege_trap) 1300 DBG_FAULT(34) 1301 FAULT(34) 1302END(lower_privilege_trap) 1303 1304 .org ia64_ivt+0x5f00 1305///////////////////////////////////////////////////////////////////////////////////////// 1306// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) 1307ENTRY(taken_branch_trap) 1308 DBG_FAULT(35) 1309 FAULT(35) 1310END(taken_branch_trap) 1311 1312 .org ia64_ivt+0x6000 1313///////////////////////////////////////////////////////////////////////////////////////// 1314// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) 1315ENTRY(single_step_trap) 1316 DBG_FAULT(36) 1317 FAULT(36) 1318END(single_step_trap) 1319 1320 .org ia64_ivt+0x6100 1321///////////////////////////////////////////////////////////////////////////////////////// 1322// 0x6100 Entry 37 (size 16 bundles) Reserved 1323 DBG_FAULT(37) 1324 FAULT(37) 1325 1326 .org ia64_ivt+0x6200 1327///////////////////////////////////////////////////////////////////////////////////////// 1328// 0x6200 Entry 38 (size 16 bundles) Reserved 1329 DBG_FAULT(38) 1330 FAULT(38) 1331 1332 .org ia64_ivt+0x6300 1333///////////////////////////////////////////////////////////////////////////////////////// 1334// 0x6300 Entry 39 (size 16 bundles) Reserved 1335 DBG_FAULT(39) 1336 FAULT(39) 1337 1338 .org ia64_ivt+0x6400 1339///////////////////////////////////////////////////////////////////////////////////////// 1340// 0x6400 Entry 40 (size 16 bundles) Reserved 1341 DBG_FAULT(40) 1342 FAULT(40) 1343 1344 .org ia64_ivt+0x6500 1345///////////////////////////////////////////////////////////////////////////////////////// 1346// 0x6500 Entry 41 (size 16 bundles) Reserved 1347 DBG_FAULT(41) 1348 FAULT(41) 1349 1350 .org ia64_ivt+0x6600 1351///////////////////////////////////////////////////////////////////////////////////////// 1352// 0x6600 Entry 42 (size 16 bundles) Reserved 1353 DBG_FAULT(42) 1354 FAULT(42) 1355 1356 .org ia64_ivt+0x6700 1357///////////////////////////////////////////////////////////////////////////////////////// 1358// 0x6700 Entry 43 (size 16 bundles) Reserved 1359 DBG_FAULT(43) 1360 FAULT(43) 1361 1362 .org ia64_ivt+0x6800 1363///////////////////////////////////////////////////////////////////////////////////////// 1364// 0x6800 Entry 44 (size 16 bundles) Reserved 1365 DBG_FAULT(44) 1366 FAULT(44) 1367 1368 .org ia64_ivt+0x6900 1369///////////////////////////////////////////////////////////////////////////////////////// 1370// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) 1371ENTRY(ia32_exception) 1372 DBG_FAULT(45) 1373 FAULT(45) 1374END(ia32_exception) 1375 1376 .org ia64_ivt+0x6a00 1377///////////////////////////////////////////////////////////////////////////////////////// 1378// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) 1379ENTRY(ia32_intercept) 1380 DBG_FAULT(46) 1381#ifdef CONFIG_IA32_SUPPORT 1382 mov r31=pr 1383 mov r16=cr.isr 1384 ;; 1385 extr.u r17=r16,16,8 // get ISR.code 1386 mov r18=ar.eflag 1387 mov r19=cr.iim // old eflag value 1388 ;; 1389 cmp.ne p6,p0=2,r17 1390(p6) br.cond.spnt 1f // not a system flag fault 1391 xor r16=r18,r19 1392 ;; 1393 extr.u r17=r16,18,1 // get the eflags.ac bit 1394 ;; 1395 cmp.eq p6,p0=0,r17 1396(p6) br.cond.spnt 1f // eflags.ac bit didn't change 1397 ;; 1398 mov pr=r31,-1 // restore predicate registers 1399 rfi 1400 14011: 1402#endif // CONFIG_IA32_SUPPORT 1403 FAULT(46) 1404END(ia32_intercept) 1405 1406 .org ia64_ivt+0x6b00 1407///////////////////////////////////////////////////////////////////////////////////////// 1408// 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) 1409ENTRY(ia32_interrupt) 1410 DBG_FAULT(47) 1411#ifdef CONFIG_IA32_SUPPORT 1412 mov r31=pr 1413 br.sptk.many dispatch_to_ia32_handler 1414#else 1415 FAULT(47) 1416#endif 1417END(ia32_interrupt) 1418 1419 .org ia64_ivt+0x6c00 1420///////////////////////////////////////////////////////////////////////////////////////// 1421// 0x6c00 Entry 48 (size 16 bundles) Reserved 1422 DBG_FAULT(48) 1423 FAULT(48) 1424 1425 .org ia64_ivt+0x6d00 1426///////////////////////////////////////////////////////////////////////////////////////// 1427// 0x6d00 Entry 49 (size 16 bundles) Reserved 1428 DBG_FAULT(49) 1429 FAULT(49) 1430 1431 .org ia64_ivt+0x6e00 1432///////////////////////////////////////////////////////////////////////////////////////// 1433// 0x6e00 Entry 50 (size 16 bundles) Reserved 1434 DBG_FAULT(50) 1435 FAULT(50) 1436 1437 .org ia64_ivt+0x6f00 1438///////////////////////////////////////////////////////////////////////////////////////// 1439// 0x6f00 Entry 51 (size 16 bundles) Reserved 1440 DBG_FAULT(51) 1441 FAULT(51) 1442 1443 .org ia64_ivt+0x7000 1444///////////////////////////////////////////////////////////////////////////////////////// 1445// 0x7000 Entry 52 (size 16 bundles) Reserved 1446 DBG_FAULT(52) 1447 FAULT(52) 1448 1449 .org ia64_ivt+0x7100 1450///////////////////////////////////////////////////////////////////////////////////////// 1451// 0x7100 Entry 53 (size 16 bundles) Reserved 1452 DBG_FAULT(53) 1453 FAULT(53) 1454 1455 .org ia64_ivt+0x7200 1456///////////////////////////////////////////////////////////////////////////////////////// 1457// 0x7200 Entry 54 (size 16 bundles) Reserved 1458 DBG_FAULT(54) 1459 FAULT(54) 1460 1461 .org ia64_ivt+0x7300 1462///////////////////////////////////////////////////////////////////////////////////////// 1463// 0x7300 Entry 55 (size 16 bundles) Reserved 1464 DBG_FAULT(55) 1465 FAULT(55) 1466 1467 .org ia64_ivt+0x7400 1468///////////////////////////////////////////////////////////////////////////////////////// 1469// 0x7400 Entry 56 (size 16 bundles) Reserved 1470 DBG_FAULT(56) 1471 FAULT(56) 1472 1473 .org ia64_ivt+0x7500 1474///////////////////////////////////////////////////////////////////////////////////////// 1475// 0x7500 Entry 57 (size 16 bundles) Reserved 1476 DBG_FAULT(57) 1477 FAULT(57) 1478 1479 .org ia64_ivt+0x7600 1480///////////////////////////////////////////////////////////////////////////////////////// 1481// 0x7600 Entry 58 (size 16 bundles) Reserved 1482 DBG_FAULT(58) 1483 FAULT(58) 1484 1485 .org ia64_ivt+0x7700 1486///////////////////////////////////////////////////////////////////////////////////////// 1487// 0x7700 Entry 59 (size 16 bundles) Reserved 1488 DBG_FAULT(59) 1489 FAULT(59) 1490 1491 .org ia64_ivt+0x7800 1492///////////////////////////////////////////////////////////////////////////////////////// 1493// 0x7800 Entry 60 (size 16 bundles) Reserved 1494 DBG_FAULT(60) 1495 FAULT(60) 1496 1497 .org ia64_ivt+0x7900 1498///////////////////////////////////////////////////////////////////////////////////////// 1499// 0x7900 Entry 61 (size 16 bundles) Reserved 1500 DBG_FAULT(61) 1501 FAULT(61) 1502 1503 .org ia64_ivt+0x7a00 1504///////////////////////////////////////////////////////////////////////////////////////// 1505// 0x7a00 Entry 62 (size 16 bundles) Reserved 1506 DBG_FAULT(62) 1507 FAULT(62) 1508 1509 .org ia64_ivt+0x7b00 1510///////////////////////////////////////////////////////////////////////////////////////// 1511// 0x7b00 Entry 63 (size 16 bundles) Reserved 1512 DBG_FAULT(63) 1513 FAULT(63) 1514 1515 .org ia64_ivt+0x7c00 1516///////////////////////////////////////////////////////////////////////////////////////// 1517// 0x7c00 Entry 64 (size 16 bundles) Reserved 1518 DBG_FAULT(64) 1519 FAULT(64) 1520 1521 .org ia64_ivt+0x7d00 1522///////////////////////////////////////////////////////////////////////////////////////// 1523// 0x7d00 Entry 65 (size 16 bundles) Reserved 1524 DBG_FAULT(65) 1525 FAULT(65) 1526 1527 .org ia64_ivt+0x7e00 1528///////////////////////////////////////////////////////////////////////////////////////// 1529// 0x7e00 Entry 66 (size 16 bundles) Reserved 1530 DBG_FAULT(66) 1531 FAULT(66) 1532 1533 .org ia64_ivt+0x7f00 1534///////////////////////////////////////////////////////////////////////////////////////// 1535// 0x7f00 Entry 67 (size 16 bundles) Reserved 1536 DBG_FAULT(67) 1537 FAULT(67) 1538 1539#ifdef CONFIG_IA32_SUPPORT 1540 1541 /* 1542 * There is no particular reason for this code to be here, other than that 1543 * there happens to be space here that would go unused otherwise. If this 1544 * fault ever gets "unreserved", simply moved the following code to a more 1545 * suitable spot... 1546 */ 1547 1548 // IA32 interrupt entry point 1549 1550ENTRY(dispatch_to_ia32_handler) 1551 SAVE_MIN 1552 ;; 1553 mov r14=cr.isr 1554 ssm psr.ic | PSR_DEFAULT_BITS 1555 ;; 1556 srlz.i // guarantee that interruption collection is on 1557 ;; 1558(p15) ssm psr.i 1559 adds r3=8,r2 // Base pointer for SAVE_REST 1560 ;; 1561 SAVE_REST 1562 ;; 1563 mov r15=0x80 1564 shr r14=r14,16 // Get interrupt number 1565 ;; 1566 cmp.ne p6,p0=r14,r15 1567(p6) br.call.dpnt.many b6=non_ia32_syscall 1568 1569 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions 1570 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp 1571 ;; 1572 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 1573 ld8 r8=[r14] // get r8 1574 ;; 1575 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP) 1576 ;; 1577 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group 1578 ;; 1579 ld4 r8=[r14],8 // r8 == eax (syscall number) 1580 mov r15=IA32_NR_syscalls 1581 ;; 1582 cmp.ltu.unc p6,p7=r8,r15 1583 ld4 out1=[r14],8 // r9 == ecx 1584 ;; 1585 ld4 out2=[r14],8 // r10 == edx 1586 ;; 1587 ld4 out0=[r14] // r11 == ebx 1588 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp 1589 ;; 1590 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp 1591 ;; 1592 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi 1593 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 1594 ;; 1595 ld4 out4=[r14] // r15 == edi 1596 movl r16=ia32_syscall_table 1597 ;; 1598(p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number 1599 ld4 r2=[r2] // r2 = current_thread_info()->flags 1600 ;; 1601 ld8 r16=[r16] 1602 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit 1603 ;; 1604 mov b6=r16 1605 movl r15=ia32_ret_from_syscall 1606 cmp.eq p8,p0=r2,r0 1607 ;; 1608 mov rp=r15 1609(p8) br.call.sptk.many b6=b6 1610 br.cond.sptk ia32_trace_syscall 1611 1612non_ia32_syscall: 1613 alloc r15=ar.pfs,0,0,2,0 1614 mov out0=r14 // interrupt # 1615 add out1=16,sp // pointer to pt_regs 1616 ;; // avoid WAW on CFM 1617 br.call.sptk.many rp=ia32_bad_interrupt 1618.ret1: movl r15=ia64_leave_kernel 1619 ;; 1620 mov rp=r15 1621 br.ret.sptk.many rp 1622END(dispatch_to_ia32_handler) 1623 1624#endif /* CONFIG_IA32_SUPPORT */ 1625